tree 0480857ae9232779f07af7f309e6ffcaee0bcfa0
parent 121643c2c9f8d424d1e66ca635828361b687e903
author Satheeshakrishna M <satheeshakrishna.m@intel.com> 1415890516 +0000
committer Daniel Vetter <daniel.vetter@ffwll.ch> 1415960293 +0100

drm/i915/skl: Determine enabled PLL and its linkrate/pixel clock

v2: Fixup compilation due to the removal of the intel_ddi_dpll_id enum.
And add a fixme about the abuse of pipe_config here.

v3: Rebase on top of the hsw_ddi_clock_get() rename (Damien)

v4: Modified as per review comments from Paulo

Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Satheeshakrishna M <satheeshakrishna.m@intel.com> (v1)
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> (v3)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> (v2)
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>