drm/msm/sde: refactor qseed3 configuration code
Since qseed3 block is common to both sspp and destination scaler,
the configuration code has been moved to hw_util.* from hw_sspp.*
Change-Id: I4eb4266e22716368c578ab453cb54972e94f3135
Signed-off-by: Sravanthi Kollukuduru <skolluku@codeaurora.org>
diff --git a/drivers/gpu/drm/msm/sde/sde_hw_sspp.c b/drivers/gpu/drm/msm/sde/sde_hw_sspp.c
index a4564c1..109fe8b 100644
--- a/drivers/gpu/drm/msm/sde/sde_hw_sspp.c
+++ b/drivers/gpu/drm/msm/sde/sde_hw_sspp.c
@@ -119,57 +119,6 @@
#define COMP1_2_INIT_PHASE_Y 0x2C
#define VIG_0_QSEED2_SHARP 0x30
-/* SDE_SSPP_SCALER_QSEED3 */
-#define QSEED3_HW_VERSION 0x00
-#define QSEED3_OP_MODE 0x04
-#define QSEED3_RGB2Y_COEFF 0x08
-#define QSEED3_PHASE_INIT 0x0C
-#define QSEED3_PHASE_STEP_Y_H 0x10
-#define QSEED3_PHASE_STEP_Y_V 0x14
-#define QSEED3_PHASE_STEP_UV_H 0x18
-#define QSEED3_PHASE_STEP_UV_V 0x1C
-#define QSEED3_PRELOAD 0x20
-#define QSEED3_DE_SHARPEN 0x24
-#define QSEED3_DE_SHARPEN_CTL 0x28
-#define QSEED3_DE_SHAPE_CTL 0x2C
-#define QSEED3_DE_THRESHOLD 0x30
-#define QSEED3_DE_ADJUST_DATA_0 0x34
-#define QSEED3_DE_ADJUST_DATA_1 0x38
-#define QSEED3_DE_ADJUST_DATA_2 0x3C
-#define QSEED3_SRC_SIZE_Y_RGB_A 0x40
-#define QSEED3_SRC_SIZE_UV 0x44
-#define QSEED3_DST_SIZE 0x48
-#define QSEED3_COEF_LUT_CTRL 0x4C
-#define QSEED3_COEF_LUT_SWAP_BIT 0
-#define QSEED3_COEF_LUT_DIR_BIT 1
-#define QSEED3_COEF_LUT_Y_CIR_BIT 2
-#define QSEED3_COEF_LUT_UV_CIR_BIT 3
-#define QSEED3_COEF_LUT_Y_SEP_BIT 4
-#define QSEED3_COEF_LUT_UV_SEP_BIT 5
-#define QSEED3_BUFFER_CTRL 0x50
-#define QSEED3_CLK_CTRL0 0x54
-#define QSEED3_CLK_CTRL1 0x58
-#define QSEED3_CLK_STATUS 0x5C
-#define QSEED3_MISR_CTRL 0x70
-#define QSEED3_MISR_SIGNATURE_0 0x74
-#define QSEED3_MISR_SIGNATURE_1 0x78
-#define QSEED3_PHASE_INIT_Y_H 0x90
-#define QSEED3_PHASE_INIT_Y_V 0x94
-#define QSEED3_PHASE_INIT_UV_H 0x98
-#define QSEED3_PHASE_INIT_UV_V 0x9C
-#define QSEED3_COEF_LUT 0x100
-#define QSEED3_FILTERS 5
-#define QSEED3_LUT_REGIONS 4
-#define QSEED3_CIRCULAR_LUTS 9
-#define QSEED3_SEPARABLE_LUTS 10
-#define QSEED3_LUT_SIZE 60
-#define QSEED3_ENABLE 2
-#define QSEED3_DIR_LUT_SIZE (200 * sizeof(u32))
-#define QSEED3_CIR_LUT_SIZE \
- (QSEED3_LUT_SIZE * QSEED3_CIRCULAR_LUTS * sizeof(u32))
-#define QSEED3_SEP_LUT_SIZE \
- (QSEED3_LUT_SIZE * QSEED3_SEPARABLE_LUTS * sizeof(u32))
-
/*
* Definitions for ViG op modes
*/
@@ -556,144 +505,12 @@
pe->phase_step_y[SDE_SSPP_COMP_1_2]);
}
-static void _sde_hw_sspp_setup_scaler3_lut(struct sde_hw_pipe *ctx,
- struct sde_hw_scaler3_cfg *scaler3_cfg)
-{
- u32 idx;
- int i, j, filter;
- int config_lut = 0x0;
- unsigned long lut_flags;
- u32 lut_addr, lut_offset, lut_len;
- u32 *lut[QSEED3_FILTERS] = {NULL, NULL, NULL, NULL, NULL};
- static const uint32_t offset[QSEED3_FILTERS][QSEED3_LUT_REGIONS][2] = {
- {{18, 0x000}, {12, 0x120}, {12, 0x1E0}, {8, 0x2A0} },
- {{6, 0x320}, {3, 0x3E0}, {3, 0x440}, {3, 0x4A0} },
- {{6, 0x500}, {3, 0x5c0}, {3, 0x620}, {3, 0x680} },
- {{6, 0x380}, {3, 0x410}, {3, 0x470}, {3, 0x4d0} },
- {{6, 0x560}, {3, 0x5f0}, {3, 0x650}, {3, 0x6b0} },
- };
-
- if (_sspp_subblk_offset(ctx, SDE_SSPP_SCALER_QSEED3, &idx) ||
- !scaler3_cfg)
- return;
-
- lut_flags = (unsigned long) scaler3_cfg->lut_flag;
- if (test_bit(QSEED3_COEF_LUT_DIR_BIT, &lut_flags) &&
- (scaler3_cfg->dir_len == QSEED3_DIR_LUT_SIZE)) {
- lut[0] = scaler3_cfg->dir_lut;
- config_lut = 1;
- }
- if (test_bit(QSEED3_COEF_LUT_Y_CIR_BIT, &lut_flags) &&
- (scaler3_cfg->y_rgb_cir_lut_idx < QSEED3_CIRCULAR_LUTS) &&
- (scaler3_cfg->cir_len == QSEED3_CIR_LUT_SIZE)) {
- lut[1] = scaler3_cfg->cir_lut +
- scaler3_cfg->y_rgb_cir_lut_idx * QSEED3_LUT_SIZE;
- config_lut = 1;
- }
- if (test_bit(QSEED3_COEF_LUT_UV_CIR_BIT, &lut_flags) &&
- (scaler3_cfg->uv_cir_lut_idx < QSEED3_CIRCULAR_LUTS) &&
- (scaler3_cfg->cir_len == QSEED3_CIR_LUT_SIZE)) {
- lut[2] = scaler3_cfg->cir_lut +
- scaler3_cfg->uv_cir_lut_idx * QSEED3_LUT_SIZE;
- config_lut = 1;
- }
- if (test_bit(QSEED3_COEF_LUT_Y_SEP_BIT, &lut_flags) &&
- (scaler3_cfg->y_rgb_sep_lut_idx < QSEED3_SEPARABLE_LUTS) &&
- (scaler3_cfg->sep_len == QSEED3_SEP_LUT_SIZE)) {
- lut[3] = scaler3_cfg->sep_lut +
- scaler3_cfg->y_rgb_sep_lut_idx * QSEED3_LUT_SIZE;
- config_lut = 1;
- }
- if (test_bit(QSEED3_COEF_LUT_UV_SEP_BIT, &lut_flags) &&
- (scaler3_cfg->uv_sep_lut_idx < QSEED3_SEPARABLE_LUTS) &&
- (scaler3_cfg->sep_len == QSEED3_SEP_LUT_SIZE)) {
- lut[4] = scaler3_cfg->sep_lut +
- scaler3_cfg->uv_sep_lut_idx * QSEED3_LUT_SIZE;
- config_lut = 1;
- }
-
- if (config_lut) {
- for (filter = 0; filter < QSEED3_FILTERS; filter++) {
- if (!lut[filter])
- continue;
- lut_offset = 0;
- for (i = 0; i < QSEED3_LUT_REGIONS; i++) {
- lut_addr = QSEED3_COEF_LUT + idx
- + offset[filter][i][1];
- lut_len = offset[filter][i][0] << 2;
- for (j = 0; j < lut_len; j++) {
- SDE_REG_WRITE(&ctx->hw,
- lut_addr,
- (lut[filter])[lut_offset++]);
- lut_addr += 4;
- }
- }
- }
- }
-
- if (test_bit(QSEED3_COEF_LUT_SWAP_BIT, &lut_flags))
- SDE_REG_WRITE(&ctx->hw, QSEED3_COEF_LUT_CTRL + idx, BIT(0));
-
-}
-
-static void _sde_hw_sspp_setup_scaler3_de(struct sde_hw_pipe *ctx,
- struct sde_hw_scaler3_de_cfg *de_cfg)
-{
- u32 idx;
- u32 sharp_lvl, sharp_ctl, shape_ctl, de_thr;
- u32 adjust_a, adjust_b, adjust_c;
- struct sde_hw_blk_reg_map *hw;
-
- if (_sspp_subblk_offset(ctx, SDE_SSPP_SCALER_QSEED3, &idx) || !de_cfg)
- return;
-
- if (!de_cfg->enable)
- return;
-
- hw = &ctx->hw;
- sharp_lvl = (de_cfg->sharpen_level1 & 0x1FF) |
- ((de_cfg->sharpen_level2 & 0x1FF) << 16);
-
- sharp_ctl = ((de_cfg->limit & 0xF) << 9) |
- ((de_cfg->prec_shift & 0x7) << 13) |
- ((de_cfg->clip & 0x7) << 16);
-
- shape_ctl = (de_cfg->thr_quiet & 0xFF) |
- ((de_cfg->thr_dieout & 0x3FF) << 16);
-
- de_thr = (de_cfg->thr_low & 0x3FF) |
- ((de_cfg->thr_high & 0x3FF) << 16);
-
- adjust_a = (de_cfg->adjust_a[0] & 0x3FF) |
- ((de_cfg->adjust_a[1] & 0x3FF) << 10) |
- ((de_cfg->adjust_a[2] & 0x3FF) << 20);
-
- adjust_b = (de_cfg->adjust_b[0] & 0x3FF) |
- ((de_cfg->adjust_b[1] & 0x3FF) << 10) |
- ((de_cfg->adjust_b[2] & 0x3FF) << 20);
-
- adjust_c = (de_cfg->adjust_c[0] & 0x3FF) |
- ((de_cfg->adjust_c[1] & 0x3FF) << 10) |
- ((de_cfg->adjust_c[2] & 0x3FF) << 20);
-
- SDE_REG_WRITE(hw, QSEED3_DE_SHARPEN + idx, sharp_lvl);
- SDE_REG_WRITE(hw, QSEED3_DE_SHARPEN_CTL + idx, sharp_ctl);
- SDE_REG_WRITE(hw, QSEED3_DE_SHAPE_CTL + idx, shape_ctl);
- SDE_REG_WRITE(hw, QSEED3_DE_THRESHOLD + idx, de_thr);
- SDE_REG_WRITE(hw, QSEED3_DE_ADJUST_DATA_0 + idx, adjust_a);
- SDE_REG_WRITE(hw, QSEED3_DE_ADJUST_DATA_1 + idx, adjust_b);
- SDE_REG_WRITE(hw, QSEED3_DE_ADJUST_DATA_2 + idx, adjust_c);
-
-}
-
static void _sde_hw_sspp_setup_scaler3(struct sde_hw_pipe *ctx,
struct sde_hw_pipe_cfg *sspp,
struct sde_hw_pixel_ext *pe,
void *scaler_cfg)
{
u32 idx;
- u32 op_mode = 0;
- u32 phase_init, preload, src_y_rgb, src_uv, dst;
struct sde_hw_scaler3_cfg *scaler3_cfg = scaler_cfg;
(void)pe;
@@ -701,93 +518,9 @@
|| !scaler3_cfg || !ctx || !ctx->cap || !ctx->cap->sblk)
return;
- if (!scaler3_cfg->enable)
- goto end;
-
- op_mode |= BIT(0);
- op_mode |= (scaler3_cfg->y_rgb_filter_cfg & 0x3) << 16;
-
- if (SDE_FORMAT_IS_YUV(sspp->layout.format)) {
- op_mode |= BIT(12);
- op_mode |= (scaler3_cfg->uv_filter_cfg & 0x3) << 24;
- }
-
- op_mode |= (scaler3_cfg->blend_cfg & 1) << 31;
- op_mode |= (scaler3_cfg->dir_en) ? BIT(4) : 0;
-
- preload =
- ((scaler3_cfg->preload_x[0] & 0x7F) << 0) |
- ((scaler3_cfg->preload_y[0] & 0x7F) << 8) |
- ((scaler3_cfg->preload_x[1] & 0x7F) << 16) |
- ((scaler3_cfg->preload_y[1] & 0x7F) << 24);
-
- src_y_rgb = (scaler3_cfg->src_width[0] & 0x1FFFF) |
- ((scaler3_cfg->src_height[0] & 0x1FFFF) << 16);
-
- src_uv = (scaler3_cfg->src_width[1] & 0x1FFFF) |
- ((scaler3_cfg->src_height[1] & 0x1FFFF) << 16);
-
- dst = (scaler3_cfg->dst_width & 0x1FFFF) |
- ((scaler3_cfg->dst_height & 0x1FFFF) << 16);
-
- if (scaler3_cfg->de.enable) {
- _sde_hw_sspp_setup_scaler3_de(ctx, &scaler3_cfg->de);
- op_mode |= BIT(8);
- }
-
- if (scaler3_cfg->lut_flag)
- _sde_hw_sspp_setup_scaler3_lut(ctx, scaler3_cfg);
-
- if (ctx->cap->sblk->scaler_blk.version == 0x1002) {
- phase_init =
- ((scaler3_cfg->init_phase_x[0] & 0x3F) << 0) |
- ((scaler3_cfg->init_phase_y[0] & 0x3F) << 8) |
- ((scaler3_cfg->init_phase_x[1] & 0x3F) << 16) |
- ((scaler3_cfg->init_phase_y[1] & 0x3F) << 24);
- SDE_REG_WRITE(&ctx->hw, QSEED3_PHASE_INIT + idx, phase_init);
- } else {
- SDE_REG_WRITE(&ctx->hw, QSEED3_PHASE_INIT_Y_H + idx,
- scaler3_cfg->init_phase_x[0] & 0x1FFFFF);
- SDE_REG_WRITE(&ctx->hw, QSEED3_PHASE_INIT_Y_V + idx,
- scaler3_cfg->init_phase_y[0] & 0x1FFFFF);
- SDE_REG_WRITE(&ctx->hw, QSEED3_PHASE_INIT_UV_H + idx,
- scaler3_cfg->init_phase_x[1] & 0x1FFFFF);
- SDE_REG_WRITE(&ctx->hw, QSEED3_PHASE_INIT_UV_V + idx,
- scaler3_cfg->init_phase_y[1] & 0x1FFFFF);
- }
-
- SDE_REG_WRITE(&ctx->hw, QSEED3_PHASE_STEP_Y_H + idx,
- scaler3_cfg->phase_step_x[0] & 0xFFFFFF);
-
- SDE_REG_WRITE(&ctx->hw, QSEED3_PHASE_STEP_Y_V + idx,
- scaler3_cfg->phase_step_y[0] & 0xFFFFFF);
-
- SDE_REG_WRITE(&ctx->hw, QSEED3_PHASE_STEP_UV_H + idx,
- scaler3_cfg->phase_step_x[1] & 0xFFFFFF);
-
- SDE_REG_WRITE(&ctx->hw, QSEED3_PHASE_STEP_UV_V + idx,
- scaler3_cfg->phase_step_y[1] & 0xFFFFFF);
-
- SDE_REG_WRITE(&ctx->hw, QSEED3_PRELOAD + idx, preload);
-
- SDE_REG_WRITE(&ctx->hw, QSEED3_SRC_SIZE_Y_RGB_A + idx, src_y_rgb);
-
- SDE_REG_WRITE(&ctx->hw, QSEED3_SRC_SIZE_UV + idx, src_uv);
-
- SDE_REG_WRITE(&ctx->hw, QSEED3_DST_SIZE + idx, dst);
-
-end:
- if (!SDE_FORMAT_IS_DX(sspp->layout.format))
- op_mode |= BIT(14);
-
- if (sspp->layout.format->alpha_enable) {
- op_mode |= BIT(10);
- if (ctx->cap->sblk->scaler_blk.version == 0x1002)
- op_mode |= (scaler3_cfg->alpha_filter_cfg & 0x1) << 30;
- else
- op_mode |= (scaler3_cfg->alpha_filter_cfg & 0x3) << 29;
- }
- SDE_REG_WRITE(&ctx->hw, QSEED3_OP_MODE + idx, op_mode);
+ sde_hw_setup_scaler3(&ctx->hw, scaler3_cfg, idx,
+ ctx->cap->sblk->scaler_blk.version,
+ sspp->layout.format);
}
static u32 _sde_hw_sspp_get_scaler3_ver(struct sde_hw_pipe *ctx)
@@ -797,7 +530,7 @@
if (!ctx || _sspp_subblk_offset(ctx, SDE_SSPP_SCALER_QSEED3, &idx))
return 0;
- return SDE_REG_READ(&ctx->hw, QSEED3_HW_VERSION + idx);
+ return sde_hw_get_scaler3_ver(&ctx->hw, idx);
}
/**
diff --git a/drivers/gpu/drm/msm/sde/sde_hw_sspp.h b/drivers/gpu/drm/msm/sde/sde_hw_sspp.h
index 8700627..6e03ab1 100644
--- a/drivers/gpu/drm/msm/sde/sde_hw_sspp.h
+++ b/drivers/gpu/drm/msm/sde/sde_hw_sspp.h
@@ -156,114 +156,6 @@
};
/**
- * struct sde_hw_scaler3_de_cfg : QSEEDv3 detail enhancer configuration
- * @enable: detail enhancer enable/disable
- * @sharpen_level1: sharpening strength for noise
- * @sharpen_level2: sharpening strength for signal
- * @ clip: clip shift
- * @ limit: limit value
- * @ thr_quiet: quiet threshold
- * @ thr_dieout: dieout threshold
- * @ thr_high: low threshold
- * @ thr_high: high threshold
- * @ prec_shift: precision shift
- * @ adjust_a: A-coefficients for mapping curve
- * @ adjust_b: B-coefficients for mapping curve
- * @ adjust_c: C-coefficients for mapping curve
- */
-struct sde_hw_scaler3_de_cfg {
- u32 enable;
- int16_t sharpen_level1;
- int16_t sharpen_level2;
- uint16_t clip;
- uint16_t limit;
- uint16_t thr_quiet;
- uint16_t thr_dieout;
- uint16_t thr_low;
- uint16_t thr_high;
- uint16_t prec_shift;
- int16_t adjust_a[SDE_MAX_DE_CURVES];
- int16_t adjust_b[SDE_MAX_DE_CURVES];
- int16_t adjust_c[SDE_MAX_DE_CURVES];
-};
-
-/**
- * struct sde_hw_scaler3_cfg : QSEEDv3 configuration
- * @enable: scaler enable
- * @dir_en: direction detection block enable
- * @ init_phase_x: horizontal initial phase
- * @ phase_step_x: horizontal phase step
- * @ init_phase_y: vertical initial phase
- * @ phase_step_y: vertical phase step
- * @ preload_x: horizontal preload value
- * @ preload_y: vertical preload value
- * @ src_width: source width
- * @ src_height: source height
- * @ dst_width: destination width
- * @ dst_height: destination height
- * @ y_rgb_filter_cfg: y/rgb plane filter configuration
- * @ uv_filter_cfg: uv plane filter configuration
- * @ alpha_filter_cfg: alpha filter configuration
- * @ blend_cfg: blend coefficients configuration
- * @ lut_flag: scaler LUT update flags
- * 0x1 swap LUT bank
- * 0x2 update 2D filter LUT
- * 0x4 update y circular filter LUT
- * 0x8 update uv circular filter LUT
- * 0x10 update y separable filter LUT
- * 0x20 update uv separable filter LUT
- * @ dir_lut_idx: 2D filter LUT index
- * @ y_rgb_cir_lut_idx: y circular filter LUT index
- * @ uv_cir_lut_idx: uv circular filter LUT index
- * @ y_rgb_sep_lut_idx: y circular filter LUT index
- * @ uv_sep_lut_idx: uv separable filter LUT index
- * @ dir_lut: pointer to 2D LUT
- * @ cir_lut: pointer to circular filter LUT
- * @ sep_lut: pointer to separable filter LUT
- * @ de: detail enhancer configuration
- */
-struct sde_hw_scaler3_cfg {
- u32 enable;
- u32 dir_en;
- int32_t init_phase_x[SDE_MAX_PLANES];
- int32_t phase_step_x[SDE_MAX_PLANES];
- int32_t init_phase_y[SDE_MAX_PLANES];
- int32_t phase_step_y[SDE_MAX_PLANES];
-
- u32 preload_x[SDE_MAX_PLANES];
- u32 preload_y[SDE_MAX_PLANES];
- u32 src_width[SDE_MAX_PLANES];
- u32 src_height[SDE_MAX_PLANES];
-
- u32 dst_width;
- u32 dst_height;
-
- u32 y_rgb_filter_cfg;
- u32 uv_filter_cfg;
- u32 alpha_filter_cfg;
- u32 blend_cfg;
-
- u32 lut_flag;
- u32 dir_lut_idx;
-
- u32 y_rgb_cir_lut_idx;
- u32 uv_cir_lut_idx;
- u32 y_rgb_sep_lut_idx;
- u32 uv_sep_lut_idx;
- u32 *dir_lut;
- size_t dir_len;
- u32 *cir_lut;
- size_t cir_len;
- u32 *sep_lut;
- size_t sep_len;
-
- /*
- * Detail enhancer settings
- */
- struct sde_hw_scaler3_de_cfg de;
-};
-
-/**
* struct sde_hw_pipe_cfg : Pipe description
* @layout: format layout information for programming buffer to hardware
* @src_rect: src ROI, caller takes into account the different operations
diff --git a/drivers/gpu/drm/msm/sde/sde_hw_util.c b/drivers/gpu/drm/msm/sde/sde_hw_util.c
index 7df5736..08fe5e1 100644
--- a/drivers/gpu/drm/msm/sde/sde_hw_util.c
+++ b/drivers/gpu/drm/msm/sde/sde_hw_util.c
@@ -10,6 +10,8 @@
* GNU General Public License for more details.
*/
#define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__
+
+#include <uapi/drm/sde_drm.h>
#include "msm_drv.h"
#include "sde_kms.h"
#include "sde_hw_mdss.h"
@@ -18,6 +20,57 @@
/* using a file static variables for debugfs access */
static u32 sde_hw_util_log_mask = SDE_DBG_MASK_NONE;
+/* SDE_SCALER_QSEED3 */
+#define QSEED3_HW_VERSION 0x00
+#define QSEED3_OP_MODE 0x04
+#define QSEED3_RGB2Y_COEFF 0x08
+#define QSEED3_PHASE_INIT 0x0C
+#define QSEED3_PHASE_STEP_Y_H 0x10
+#define QSEED3_PHASE_STEP_Y_V 0x14
+#define QSEED3_PHASE_STEP_UV_H 0x18
+#define QSEED3_PHASE_STEP_UV_V 0x1C
+#define QSEED3_PRELOAD 0x20
+#define QSEED3_DE_SHARPEN 0x24
+#define QSEED3_DE_SHARPEN_CTL 0x28
+#define QSEED3_DE_SHAPE_CTL 0x2C
+#define QSEED3_DE_THRESHOLD 0x30
+#define QSEED3_DE_ADJUST_DATA_0 0x34
+#define QSEED3_DE_ADJUST_DATA_1 0x38
+#define QSEED3_DE_ADJUST_DATA_2 0x3C
+#define QSEED3_SRC_SIZE_Y_RGB_A 0x40
+#define QSEED3_SRC_SIZE_UV 0x44
+#define QSEED3_DST_SIZE 0x48
+#define QSEED3_COEF_LUT_CTRL 0x4C
+#define QSEED3_COEF_LUT_SWAP_BIT 0
+#define QSEED3_COEF_LUT_DIR_BIT 1
+#define QSEED3_COEF_LUT_Y_CIR_BIT 2
+#define QSEED3_COEF_LUT_UV_CIR_BIT 3
+#define QSEED3_COEF_LUT_Y_SEP_BIT 4
+#define QSEED3_COEF_LUT_UV_SEP_BIT 5
+#define QSEED3_BUFFER_CTRL 0x50
+#define QSEED3_CLK_CTRL0 0x54
+#define QSEED3_CLK_CTRL1 0x58
+#define QSEED3_CLK_STATUS 0x5C
+#define QSEED3_MISR_CTRL 0x70
+#define QSEED3_MISR_SIGNATURE_0 0x74
+#define QSEED3_MISR_SIGNATURE_1 0x78
+#define QSEED3_PHASE_INIT_Y_H 0x90
+#define QSEED3_PHASE_INIT_Y_V 0x94
+#define QSEED3_PHASE_INIT_UV_H 0x98
+#define QSEED3_PHASE_INIT_UV_V 0x9C
+#define QSEED3_COEF_LUT 0x100
+#define QSEED3_FILTERS 5
+#define QSEED3_LUT_REGIONS 4
+#define QSEED3_CIRCULAR_LUTS 9
+#define QSEED3_SEPARABLE_LUTS 10
+#define QSEED3_LUT_SIZE 60
+#define QSEED3_ENABLE 2
+#define QSEED3_DIR_LUT_SIZE (200 * sizeof(u32))
+#define QSEED3_CIR_LUT_SIZE \
+ (QSEED3_LUT_SIZE * QSEED3_CIRCULAR_LUTS * sizeof(u32))
+#define QSEED3_SEP_LUT_SIZE \
+ (QSEED3_LUT_SIZE * QSEED3_SEPARABLE_LUTS * sizeof(u32))
+
void sde_reg_write(struct sde_hw_blk_reg_map *c,
u32 reg_off,
u32 val,
@@ -40,6 +93,283 @@
return &sde_hw_util_log_mask;
}
+void sde_set_scaler_v2(struct sde_hw_scaler3_cfg *cfg,
+ const struct sde_drm_scaler_v2 *scale_v2)
+{
+ int i;
+
+ cfg->enable = scale_v2->enable;
+ cfg->dir_en = scale_v2->dir_en;
+
+ for (i = 0; i < SDE_MAX_PLANES; i++) {
+ cfg->init_phase_x[i] = scale_v2->init_phase_x[i];
+ cfg->phase_step_x[i] = scale_v2->phase_step_x[i];
+ cfg->init_phase_y[i] = scale_v2->init_phase_y[i];
+ cfg->phase_step_y[i] = scale_v2->phase_step_y[i];
+
+ cfg->preload_x[i] = scale_v2->preload_x[i];
+ cfg->preload_y[i] = scale_v2->preload_y[i];
+ cfg->src_width[i] = scale_v2->src_width[i];
+ cfg->src_height[i] = scale_v2->src_height[i];
+ }
+
+ cfg->dst_width = scale_v2->dst_width;
+ cfg->dst_height = scale_v2->dst_height;
+
+ cfg->y_rgb_filter_cfg = scale_v2->y_rgb_filter_cfg;
+ cfg->uv_filter_cfg = scale_v2->uv_filter_cfg;
+ cfg->alpha_filter_cfg = scale_v2->alpha_filter_cfg;
+ cfg->blend_cfg = scale_v2->blend_cfg;
+
+ cfg->lut_flag = scale_v2->lut_flag;
+ cfg->dir_lut_idx = scale_v2->dir_lut_idx;
+ cfg->y_rgb_cir_lut_idx = scale_v2->y_rgb_cir_lut_idx;
+ cfg->uv_cir_lut_idx = scale_v2->uv_cir_lut_idx;
+ cfg->y_rgb_sep_lut_idx = scale_v2->y_rgb_sep_lut_idx;
+ cfg->uv_sep_lut_idx = scale_v2->uv_sep_lut_idx;
+
+ cfg->de.enable = scale_v2->de.enable;
+ cfg->de.sharpen_level1 = scale_v2->de.sharpen_level1;
+ cfg->de.sharpen_level2 = scale_v2->de.sharpen_level2;
+ cfg->de.clip = scale_v2->de.clip;
+ cfg->de.limit = scale_v2->de.limit;
+ cfg->de.thr_quiet = scale_v2->de.thr_quiet;
+ cfg->de.thr_dieout = scale_v2->de.thr_dieout;
+ cfg->de.thr_low = scale_v2->de.thr_low;
+ cfg->de.thr_high = scale_v2->de.thr_high;
+ cfg->de.prec_shift = scale_v2->de.prec_shift;
+
+ for (i = 0; i < SDE_MAX_DE_CURVES; i++) {
+ cfg->de.adjust_a[i] = scale_v2->de.adjust_a[i];
+ cfg->de.adjust_b[i] = scale_v2->de.adjust_b[i];
+ cfg->de.adjust_c[i] = scale_v2->de.adjust_c[i];
+ }
+}
+
+static void _sde_hw_setup_scaler3_lut(struct sde_hw_blk_reg_map *c,
+ struct sde_hw_scaler3_cfg *scaler3_cfg, u32 offset)
+{
+ int i, j, filter;
+ int config_lut = 0x0;
+ unsigned long lut_flags;
+ u32 lut_addr, lut_offset, lut_len;
+ u32 *lut[QSEED3_FILTERS] = {NULL, NULL, NULL, NULL, NULL};
+ static const uint32_t off_tbl[QSEED3_FILTERS][QSEED3_LUT_REGIONS][2] = {
+ {{18, 0x000}, {12, 0x120}, {12, 0x1E0}, {8, 0x2A0} },
+ {{6, 0x320}, {3, 0x3E0}, {3, 0x440}, {3, 0x4A0} },
+ {{6, 0x500}, {3, 0x5c0}, {3, 0x620}, {3, 0x680} },
+ {{6, 0x380}, {3, 0x410}, {3, 0x470}, {3, 0x4d0} },
+ {{6, 0x560}, {3, 0x5f0}, {3, 0x650}, {3, 0x6b0} },
+ };
+
+ lut_flags = (unsigned long) scaler3_cfg->lut_flag;
+ if (test_bit(QSEED3_COEF_LUT_DIR_BIT, &lut_flags) &&
+ (scaler3_cfg->dir_len == QSEED3_DIR_LUT_SIZE)) {
+ lut[0] = scaler3_cfg->dir_lut;
+ config_lut = 1;
+ }
+ if (test_bit(QSEED3_COEF_LUT_Y_CIR_BIT, &lut_flags) &&
+ (scaler3_cfg->y_rgb_cir_lut_idx < QSEED3_CIRCULAR_LUTS) &&
+ (scaler3_cfg->cir_len == QSEED3_CIR_LUT_SIZE)) {
+ lut[1] = scaler3_cfg->cir_lut +
+ scaler3_cfg->y_rgb_cir_lut_idx * QSEED3_LUT_SIZE;
+ config_lut = 1;
+ }
+ if (test_bit(QSEED3_COEF_LUT_UV_CIR_BIT, &lut_flags) &&
+ (scaler3_cfg->uv_cir_lut_idx < QSEED3_CIRCULAR_LUTS) &&
+ (scaler3_cfg->cir_len == QSEED3_CIR_LUT_SIZE)) {
+ lut[2] = scaler3_cfg->cir_lut +
+ scaler3_cfg->uv_cir_lut_idx * QSEED3_LUT_SIZE;
+ config_lut = 1;
+ }
+ if (test_bit(QSEED3_COEF_LUT_Y_SEP_BIT, &lut_flags) &&
+ (scaler3_cfg->y_rgb_sep_lut_idx < QSEED3_SEPARABLE_LUTS) &&
+ (scaler3_cfg->sep_len == QSEED3_SEP_LUT_SIZE)) {
+ lut[3] = scaler3_cfg->sep_lut +
+ scaler3_cfg->y_rgb_sep_lut_idx * QSEED3_LUT_SIZE;
+ config_lut = 1;
+ }
+ if (test_bit(QSEED3_COEF_LUT_UV_SEP_BIT, &lut_flags) &&
+ (scaler3_cfg->uv_sep_lut_idx < QSEED3_SEPARABLE_LUTS) &&
+ (scaler3_cfg->sep_len == QSEED3_SEP_LUT_SIZE)) {
+ lut[4] = scaler3_cfg->sep_lut +
+ scaler3_cfg->uv_sep_lut_idx * QSEED3_LUT_SIZE;
+ config_lut = 1;
+ }
+
+ if (config_lut) {
+ for (filter = 0; filter < QSEED3_FILTERS; filter++) {
+ if (!lut[filter])
+ continue;
+ lut_offset = 0;
+ for (i = 0; i < QSEED3_LUT_REGIONS; i++) {
+ lut_addr = QSEED3_COEF_LUT + offset
+ + off_tbl[filter][i][1];
+ lut_len = off_tbl[filter][i][0] << 2;
+ for (j = 0; j < lut_len; j++) {
+ SDE_REG_WRITE(c,
+ lut_addr,
+ (lut[filter])[lut_offset++]);
+ lut_addr += 4;
+ }
+ }
+ }
+ }
+
+ if (test_bit(QSEED3_COEF_LUT_SWAP_BIT, &lut_flags))
+ SDE_REG_WRITE(c, QSEED3_COEF_LUT_CTRL + offset, BIT(0));
+
+}
+
+static void _sde_hw_setup_scaler3_de(struct sde_hw_blk_reg_map *c,
+ struct sde_hw_scaler3_de_cfg *de_cfg, u32 offset)
+{
+ u32 sharp_lvl, sharp_ctl, shape_ctl, de_thr;
+ u32 adjust_a, adjust_b, adjust_c;
+
+ if (!de_cfg->enable)
+ return;
+
+ sharp_lvl = (de_cfg->sharpen_level1 & 0x1FF) |
+ ((de_cfg->sharpen_level2 & 0x1FF) << 16);
+
+ sharp_ctl = ((de_cfg->limit & 0xF) << 9) |
+ ((de_cfg->prec_shift & 0x7) << 13) |
+ ((de_cfg->clip & 0x7) << 16);
+
+ shape_ctl = (de_cfg->thr_quiet & 0xFF) |
+ ((de_cfg->thr_dieout & 0x3FF) << 16);
+
+ de_thr = (de_cfg->thr_low & 0x3FF) |
+ ((de_cfg->thr_high & 0x3FF) << 16);
+
+ adjust_a = (de_cfg->adjust_a[0] & 0x3FF) |
+ ((de_cfg->adjust_a[1] & 0x3FF) << 10) |
+ ((de_cfg->adjust_a[2] & 0x3FF) << 20);
+
+ adjust_b = (de_cfg->adjust_b[0] & 0x3FF) |
+ ((de_cfg->adjust_b[1] & 0x3FF) << 10) |
+ ((de_cfg->adjust_b[2] & 0x3FF) << 20);
+
+ adjust_c = (de_cfg->adjust_c[0] & 0x3FF) |
+ ((de_cfg->adjust_c[1] & 0x3FF) << 10) |
+ ((de_cfg->adjust_c[2] & 0x3FF) << 20);
+
+ SDE_REG_WRITE(c, QSEED3_DE_SHARPEN + offset, sharp_lvl);
+ SDE_REG_WRITE(c, QSEED3_DE_SHARPEN_CTL + offset, sharp_ctl);
+ SDE_REG_WRITE(c, QSEED3_DE_SHAPE_CTL + offset, shape_ctl);
+ SDE_REG_WRITE(c, QSEED3_DE_THRESHOLD + offset, de_thr);
+ SDE_REG_WRITE(c, QSEED3_DE_ADJUST_DATA_0 + offset, adjust_a);
+ SDE_REG_WRITE(c, QSEED3_DE_ADJUST_DATA_1 + offset, adjust_b);
+ SDE_REG_WRITE(c, QSEED3_DE_ADJUST_DATA_2 + offset, adjust_c);
+
+}
+
+void sde_hw_setup_scaler3(struct sde_hw_blk_reg_map *c,
+ struct sde_hw_scaler3_cfg *scaler3_cfg,
+ u32 scaler_offset, u32 scaler_version,
+ const struct sde_format *format)
+{
+ u32 op_mode = 0;
+ u32 phase_init, preload, src_y_rgb, src_uv, dst;
+
+ if (!scaler3_cfg->enable)
+ goto end;
+
+ op_mode |= BIT(0);
+ op_mode |= (scaler3_cfg->y_rgb_filter_cfg & 0x3) << 16;
+
+ if (format && SDE_FORMAT_IS_YUV(format)) {
+ op_mode |= BIT(12);
+ op_mode |= (scaler3_cfg->uv_filter_cfg & 0x3) << 24;
+ }
+
+ op_mode |= (scaler3_cfg->blend_cfg & 1) << 31;
+ op_mode |= (scaler3_cfg->dir_en) ? BIT(4) : 0;
+
+ preload =
+ ((scaler3_cfg->preload_x[0] & 0x7F) << 0) |
+ ((scaler3_cfg->preload_y[0] & 0x7F) << 8) |
+ ((scaler3_cfg->preload_x[1] & 0x7F) << 16) |
+ ((scaler3_cfg->preload_y[1] & 0x7F) << 24);
+
+ src_y_rgb = (scaler3_cfg->src_width[0] & 0x1FFFF) |
+ ((scaler3_cfg->src_height[0] & 0x1FFFF) << 16);
+
+ src_uv = (scaler3_cfg->src_width[1] & 0x1FFFF) |
+ ((scaler3_cfg->src_height[1] & 0x1FFFF) << 16);
+
+ dst = (scaler3_cfg->dst_width & 0x1FFFF) |
+ ((scaler3_cfg->dst_height & 0x1FFFF) << 16);
+
+ if (scaler3_cfg->de.enable) {
+ _sde_hw_setup_scaler3_de(c, &scaler3_cfg->de, scaler_offset);
+ op_mode |= BIT(8);
+ }
+
+ if (scaler3_cfg->lut_flag)
+ _sde_hw_setup_scaler3_lut(c, scaler3_cfg,
+ scaler_offset);
+
+ if (scaler_version == 0x1002) {
+ phase_init =
+ ((scaler3_cfg->init_phase_x[0] & 0x3F) << 0) |
+ ((scaler3_cfg->init_phase_y[0] & 0x3F) << 8) |
+ ((scaler3_cfg->init_phase_x[1] & 0x3F) << 16) |
+ ((scaler3_cfg->init_phase_y[1] & 0x3F) << 24);
+ SDE_REG_WRITE(c, QSEED3_PHASE_INIT + scaler_offset, phase_init);
+ } else {
+ SDE_REG_WRITE(c, QSEED3_PHASE_INIT_Y_H + scaler_offset,
+ scaler3_cfg->init_phase_x[0] & 0x1FFFFF);
+ SDE_REG_WRITE(c, QSEED3_PHASE_INIT_Y_V + scaler_offset,
+ scaler3_cfg->init_phase_y[0] & 0x1FFFFF);
+ SDE_REG_WRITE(c, QSEED3_PHASE_INIT_UV_H + scaler_offset,
+ scaler3_cfg->init_phase_x[1] & 0x1FFFFF);
+ SDE_REG_WRITE(c, QSEED3_PHASE_INIT_UV_V + scaler_offset,
+ scaler3_cfg->init_phase_y[1] & 0x1FFFFF);
+ }
+
+ SDE_REG_WRITE(c, QSEED3_PHASE_STEP_Y_H + scaler_offset,
+ scaler3_cfg->phase_step_x[0] & 0xFFFFFF);
+
+ SDE_REG_WRITE(c, QSEED3_PHASE_STEP_Y_V + scaler_offset,
+ scaler3_cfg->phase_step_y[0] & 0xFFFFFF);
+
+ SDE_REG_WRITE(c, QSEED3_PHASE_STEP_UV_H + scaler_offset,
+ scaler3_cfg->phase_step_x[1] & 0xFFFFFF);
+
+ SDE_REG_WRITE(c, QSEED3_PHASE_STEP_UV_V + scaler_offset,
+ scaler3_cfg->phase_step_y[1] & 0xFFFFFF);
+
+ SDE_REG_WRITE(c, QSEED3_PRELOAD + scaler_offset, preload);
+
+ SDE_REG_WRITE(c, QSEED3_SRC_SIZE_Y_RGB_A + scaler_offset, src_y_rgb);
+
+ SDE_REG_WRITE(c, QSEED3_SRC_SIZE_UV + scaler_offset, src_uv);
+
+ SDE_REG_WRITE(c, QSEED3_DST_SIZE + scaler_offset, dst);
+
+end:
+ if (format && !SDE_FORMAT_IS_DX(format))
+ op_mode |= BIT(14);
+
+ if (format && format->alpha_enable) {
+ op_mode |= BIT(10);
+ if (scaler_version == 0x1002)
+ op_mode |= (scaler3_cfg->alpha_filter_cfg & 0x1) << 30;
+ else
+ op_mode |= (scaler3_cfg->alpha_filter_cfg & 0x3) << 29;
+ }
+
+ SDE_REG_WRITE(c, QSEED3_OP_MODE + scaler_offset, op_mode);
+}
+
+u32 sde_hw_get_scaler3_ver(struct sde_hw_blk_reg_map *c,
+ u32 scaler_offset)
+{
+ return SDE_REG_READ(c, QSEED3_HW_VERSION + scaler_offset);
+}
+
void sde_hw_csc_setup(struct sde_hw_blk_reg_map *c,
u32 csc_reg_off,
struct sde_csc_cfg *data, bool csc10)
diff --git a/drivers/gpu/drm/msm/sde/sde_hw_util.h b/drivers/gpu/drm/msm/sde/sde_hw_util.h
index aa3d5b9..720e113 100644
--- a/drivers/gpu/drm/msm/sde/sde_hw_util.h
+++ b/drivers/gpu/drm/msm/sde/sde_hw_util.h
@@ -39,6 +39,125 @@
u32 log_mask;
};
+/**
+ * struct sde_hw_scaler3_de_cfg : QSEEDv3 detail enhancer configuration
+ * @enable: detail enhancer enable/disable
+ * @sharpen_level1: sharpening strength for noise
+ * @sharpen_level2: sharpening strength for signal
+ * @ clip: clip shift
+ * @ limit: limit value
+ * @ thr_quiet: quiet threshold
+ * @ thr_dieout: dieout threshold
+ * @ thr_high: low threshold
+ * @ thr_high: high threshold
+ * @ prec_shift: precision shift
+ * @ adjust_a: A-coefficients for mapping curve
+ * @ adjust_b: B-coefficients for mapping curve
+ * @ adjust_c: C-coefficients for mapping curve
+ */
+struct sde_hw_scaler3_de_cfg {
+ u32 enable;
+ int16_t sharpen_level1;
+ int16_t sharpen_level2;
+ uint16_t clip;
+ uint16_t limit;
+ uint16_t thr_quiet;
+ uint16_t thr_dieout;
+ uint16_t thr_low;
+ uint16_t thr_high;
+ uint16_t prec_shift;
+ int16_t adjust_a[SDE_MAX_DE_CURVES];
+ int16_t adjust_b[SDE_MAX_DE_CURVES];
+ int16_t adjust_c[SDE_MAX_DE_CURVES];
+};
+
+
+/**
+ * struct sde_hw_scaler3_cfg : QSEEDv3 configuration
+ * @enable: scaler enable
+ * @dir_en: direction detection block enable
+ * @ init_phase_x: horizontal initial phase
+ * @ phase_step_x: horizontal phase step
+ * @ init_phase_y: vertical initial phase
+ * @ phase_step_y: vertical phase step
+ * @ preload_x: horizontal preload value
+ * @ preload_y: vertical preload value
+ * @ src_width: source width
+ * @ src_height: source height
+ * @ dst_width: destination width
+ * @ dst_height: destination height
+ * @ y_rgb_filter_cfg: y/rgb plane filter configuration
+ * @ uv_filter_cfg: uv plane filter configuration
+ * @ alpha_filter_cfg: alpha filter configuration
+ * @ blend_cfg: blend coefficients configuration
+ * @ lut_flag: scaler LUT update flags
+ * 0x1 swap LUT bank
+ * 0x2 update 2D filter LUT
+ * 0x4 update y circular filter LUT
+ * 0x8 update uv circular filter LUT
+ * 0x10 update y separable filter LUT
+ * 0x20 update uv separable filter LUT
+ * @ dir_lut_idx: 2D filter LUT index
+ * @ y_rgb_cir_lut_idx: y circular filter LUT index
+ * @ uv_cir_lut_idx: uv circular filter LUT index
+ * @ y_rgb_sep_lut_idx: y circular filter LUT index
+ * @ uv_sep_lut_idx: uv separable filter LUT index
+ * @ dir_lut: pointer to 2D LUT
+ * @ cir_lut: pointer to circular filter LUT
+ * @ sep_lut: pointer to separable filter LUT
+ * @ de: detail enhancer configuration
+ */
+struct sde_hw_scaler3_cfg {
+ u32 enable;
+ u32 dir_en;
+ int32_t init_phase_x[SDE_MAX_PLANES];
+ int32_t phase_step_x[SDE_MAX_PLANES];
+ int32_t init_phase_y[SDE_MAX_PLANES];
+ int32_t phase_step_y[SDE_MAX_PLANES];
+
+ u32 preload_x[SDE_MAX_PLANES];
+ u32 preload_y[SDE_MAX_PLANES];
+ u32 src_width[SDE_MAX_PLANES];
+ u32 src_height[SDE_MAX_PLANES];
+
+ u32 dst_width;
+ u32 dst_height;
+
+ u32 y_rgb_filter_cfg;
+ u32 uv_filter_cfg;
+ u32 alpha_filter_cfg;
+ u32 blend_cfg;
+
+ u32 lut_flag;
+ u32 dir_lut_idx;
+
+ u32 y_rgb_cir_lut_idx;
+ u32 uv_cir_lut_idx;
+ u32 y_rgb_sep_lut_idx;
+ u32 uv_sep_lut_idx;
+ u32 *dir_lut;
+ size_t dir_len;
+ u32 *cir_lut;
+ size_t cir_len;
+ u32 *sep_lut;
+ size_t sep_len;
+
+ /*
+ * Detail enhancer settings
+ */
+ struct sde_hw_scaler3_de_cfg de;
+};
+
+struct sde_hw_scaler3_lut_cfg {
+ bool is_configured;
+ u32 *dir_lut;
+ size_t dir_len;
+ u32 *cir_lut;
+ size_t cir_len;
+ u32 *sep_lut;
+ size_t sep_len;
+};
+
u32 *sde_hw_util_get_log_mask_ptr(void);
void sde_reg_write(struct sde_hw_blk_reg_map *c,
@@ -58,6 +177,17 @@
void *sde_hw_util_get_dir(void);
+void sde_set_scaler_v2(struct sde_hw_scaler3_cfg *cfg,
+ const struct sde_drm_scaler_v2 *scale_v2);
+
+void sde_hw_setup_scaler3(struct sde_hw_blk_reg_map *c,
+ struct sde_hw_scaler3_cfg *scaler3_cfg,
+ u32 scaler_offset, u32 scaler_version,
+ const struct sde_format *format);
+
+u32 sde_hw_get_scaler3_ver(struct sde_hw_blk_reg_map *c,
+ u32 scaler_offset);
+
void sde_hw_csc_setup(struct sde_hw_blk_reg_map *c,
u32 csc_reg_off,
struct sde_csc_cfg *data, bool csc10);
diff --git a/drivers/gpu/drm/msm/sde/sde_plane.c b/drivers/gpu/drm/msm/sde/sde_plane.c
index 40dad76..62a298c 100644
--- a/drivers/gpu/drm/msm/sde/sde_plane.c
+++ b/drivers/gpu/drm/msm/sde/sde_plane.c
@@ -4061,51 +4061,11 @@
&pstate->property_state, PLANE_PROP_SCALER_V2);
/* populate from user space */
+ sde_set_scaler_v2(cfg, &scale_v2);
+
pe = &pstate->pixel_ext;
memset(pe, 0, sizeof(struct sde_hw_pixel_ext));
- cfg->enable = scale_v2.enable;
- cfg->dir_en = scale_v2.dir_en;
- for (i = 0; i < SDE_MAX_PLANES; i++) {
- cfg->init_phase_x[i] = scale_v2.init_phase_x[i];
- cfg->phase_step_x[i] = scale_v2.phase_step_x[i];
- cfg->init_phase_y[i] = scale_v2.init_phase_y[i];
- cfg->phase_step_y[i] = scale_v2.phase_step_y[i];
- cfg->preload_x[i] = scale_v2.preload_x[i];
- cfg->preload_y[i] = scale_v2.preload_y[i];
- cfg->src_width[i] = scale_v2.src_width[i];
- cfg->src_height[i] = scale_v2.src_height[i];
- }
- cfg->dst_width = scale_v2.dst_width;
- cfg->dst_height = scale_v2.dst_height;
-
- cfg->y_rgb_filter_cfg = scale_v2.y_rgb_filter_cfg;
- cfg->uv_filter_cfg = scale_v2.uv_filter_cfg;
- cfg->alpha_filter_cfg = scale_v2.alpha_filter_cfg;
- cfg->blend_cfg = scale_v2.blend_cfg;
-
- cfg->lut_flag = scale_v2.lut_flag;
- cfg->dir_lut_idx = scale_v2.dir_lut_idx;
- cfg->y_rgb_cir_lut_idx = scale_v2.y_rgb_cir_lut_idx;
- cfg->uv_cir_lut_idx = scale_v2.uv_cir_lut_idx;
- cfg->y_rgb_sep_lut_idx = scale_v2.y_rgb_sep_lut_idx;
- cfg->uv_sep_lut_idx = scale_v2.uv_sep_lut_idx;
-
- cfg->de.enable = scale_v2.de.enable;
- cfg->de.sharpen_level1 = scale_v2.de.sharpen_level1;
- cfg->de.sharpen_level2 = scale_v2.de.sharpen_level2;
- cfg->de.clip = scale_v2.de.clip;
- cfg->de.limit = scale_v2.de.limit;
- cfg->de.thr_quiet = scale_v2.de.thr_quiet;
- cfg->de.thr_dieout = scale_v2.de.thr_dieout;
- cfg->de.thr_low = scale_v2.de.thr_low;
- cfg->de.thr_high = scale_v2.de.thr_high;
- cfg->de.prec_shift = scale_v2.de.prec_shift;
- for (i = 0; i < SDE_MAX_DE_CURVES; i++) {
- cfg->de.adjust_a[i] = scale_v2.de.adjust_a[i];
- cfg->de.adjust_b[i] = scale_v2.de.adjust_b[i];
- cfg->de.adjust_c[i] = scale_v2.de.adjust_c[i];
- }
for (i = 0; i < SDE_MAX_PLANES; i++) {
pe->left_ftch[i] = scale_v2.pe.left_ftch[i];
pe->right_ftch[i] = scale_v2.pe.right_ftch[i];