tree 7c183cfbdbfc59f9477b2137287b2bb4e7112341
parent 0c00f65653389a408dfbbee7578e671664eea26a
author Sebastian Andrzej Siewior <bigeasy@linutronix.de> 1331833228 +0100
committer Kumar Gala <galak@kernel.crashing.org> 1331912791 -0500

powerpc/85xx: p2020rdb & p1010rdb - lower spi flash freq to 40Mhz

This is here most likely since the FSL bsp. Back in the FSL bsp it was
set to 50Mhz and working. However the driver divided the SoC freq. only
by 2. According to the TRM the platform clock (which the manual refers
in its formula) is the system clock divided by two. So in the end it has
to divide by 4 and this is what the fsl-spi driver in tree is doing.
Since then the flash is not wokring I guess. After chaning the freq from
50Mhz to 40Mhz like others do then I can access the flash.

Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>