| commit | 56713da3ee5c6b0cf5b1881973b939250766a91b | [log] [tgz] |
|---|---|---|
| author | Dinh Nguyen <dinguyen@opensource.altera.com> | Mon Feb 22 15:52:46 2016 -0600 |
| committer | Stephen Boyd <sboyd@codeaurora.org> | Mon Feb 22 14:17:37 2016 -0800 |
| tree | f44bdc536676e9cc64934dda0076bd3197b8b4cf | |
| parent | b6f5128459a40410f9afefddc0ad688ea5b22c28 [diff] |
clk: socfpga: allow for multiple parents on Arria10 periph clocks There are some Arria10 clocks of type "altr,socfpga-a10-perip-clk" that can have multiple parents. Fix up the __socfpga_periph_init() to call of_clk_parent_fill() that will return the appropriate number of parents. Also, update __socfpga_gate_init() to call of_clk_parent_fill() helper function. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>