ARM: EXYNOS4: Add save/restore function for PLL
The PLL restore routine supports waiting pll locking. If PLL is
enabled in restoring sequence, it should wait until PLL is locked.
Signed-off-by: Jaecheol Lee <jc.lee@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
diff --git a/arch/arm/mach-exynos4/include/mach/regs-clock.h b/arch/arm/mach-exynos4/include/mach/regs-clock.h
index 6e311c1..64bdd24 100644
--- a/arch/arm/mach-exynos4/include/mach/regs-clock.h
+++ b/arch/arm/mach-exynos4/include/mach/regs-clock.h
@@ -25,6 +25,9 @@
#define S5P_CLKDIV_STAT_RIGHTBUS S5P_CLKREG(0x08600)
#define S5P_CLKGATE_IP_RIGHTBUS S5P_CLKREG(0x08800)
+#define S5P_EPLL_LOCK S5P_CLKREG(0x0C010)
+#define S5P_VPLL_LOCK S5P_CLKREG(0x0C020)
+
#define S5P_EPLL_CON0 S5P_CLKREG(0x0C110)
#define S5P_EPLL_CON1 S5P_CLKREG(0x0C114)
#define S5P_VPLL_CON0 S5P_CLKREG(0x0C120)
@@ -120,6 +123,12 @@
#define S5P_APLL_VAL_1000 ((250 << 16) | (6 << 8) | 1)
#define S5P_APLL_VAL_800 ((200 << 16) | (6 << 8) | 1)
+#define S5P_EPLLCON0_ENABLE_SHIFT (31)
+#define S5P_EPLLCON0_LOCKED_SHIFT (29)
+
+#define S5P_VPLLCON0_ENABLE_SHIFT (31)
+#define S5P_VPLLCON0_LOCKED_SHIFT (29)
+
#define S5P_CLKSRC_CPU_MUXCORE_SHIFT (16)
#define S5P_CLKMUX_STATCPU_MUXCORE_MASK (0x7 << S5P_CLKSRC_CPU_MUXCORE_SHIFT)