| commit | 56fd27b31f1a216623f285bb77b4bcb6129e84c2 | [log] [tgz] |
|---|---|---|
| author | Bill Huang <bilhuang@nvidia.com> | Thu Jun 18 17:28:22 2015 -0400 |
| committer | Thierry Reding <treding@nvidia.com> | Fri Nov 20 18:04:49 2015 +0100 |
| tree | 8bad50beb11b3a32a70a853e23c9203311b333cf | |
| parent | 204c85d124bd51c0b1c70f1d6b0d853389179d38 [diff] |
clk: tegra: pll: Change misc_reg count from 3 to 6 New SoC's may have more than 3 MISC registers, so bump up the array size and use a #define to be more informative about the value. Reviewed-by: Benson Leung <bleung@chromium.org> Signed-off-by: Bill Huang <bilhuang@nvidia.com> Signed-off-by: Rhyland Klein <rklein@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>