drm/nv04-nv40/instmem: remove use of nouveau_gpuobj_new_fake()
These type of fake objects will not be supported for much longer.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/nv40.c b/drivers/gpu/drm/nouveau/core/engine/fifo/nv40.c
index 23ae459..e42498f 100644
--- a/drivers/gpu/drm/nouveau/core/engine/fifo/nv40.c
+++ b/drivers/gpu/drm/nouveau/core/engine/fifo/nv40.c
@@ -31,6 +31,8 @@
#include "nouveau_util.h"
#include <core/ramht.h>
+#include <core/subdev/instmem/nv04.h>
+
static struct ramfc_desc {
unsigned bits:6;
unsigned ctxs:5;
@@ -66,6 +68,8 @@
struct nv40_fifo_priv {
struct nouveau_fifo_priv base;
struct ramfc_desc *ramfc_desc;
+ struct nouveau_gpuobj *ramro;
+ struct nouveau_gpuobj *ramfc;
};
struct nv40_fifo_chan {
@@ -96,7 +100,7 @@
}
/* initialise default fifo context */
- ret = nouveau_gpuobj_new_fake(dev, dev_priv->ramfc->pinst +
+ ret = nouveau_gpuobj_new_fake(dev, priv->ramfc->pinst +
chan->id * 128, ~0, 128,
NVOBJ_FLAG_ZERO_ALLOC |
NVOBJ_FLAG_ZERO_FREE, &fctx->ramfc);
@@ -146,7 +150,7 @@
nv_wr32(dev, NV03_PFIFO_RAMHT, (0x03 << 24) /* search 128 */ |
((dev_priv->ramht->bits - 9) << 16) |
(dev_priv->ramht->gpuobj->pinst >> 8));
- nv_wr32(dev, NV03_PFIFO_RAMRO, dev_priv->ramro->pinst >> 8);
+ nv_wr32(dev, NV03_PFIFO_RAMRO, priv->ramro->pinst >> 8);
switch (dev_priv->chipset) {
case 0x47:
@@ -164,7 +168,7 @@
default:
nv_wr32(dev, 0x002230, 0x00000000);
nv_wr32(dev, 0x002220, ((nvfb_vram_size(dev) - 512 * 1024 +
- dev_priv->ramfc->pinst) >> 16) |
+ priv->ramfc->pinst) >> 16) |
0x00030000);
break;
}
@@ -190,12 +194,16 @@
nv40_fifo_create(struct drm_device *dev)
{
struct drm_nouveau_private *dev_priv = dev->dev_private;
+ struct nv04_instmem_priv *imem = dev_priv->engine.instmem.priv;
struct nv40_fifo_priv *priv;
priv = kzalloc(sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
+ nouveau_gpuobj_ref(imem->ramro, &priv->ramro);
+ nouveau_gpuobj_ref(imem->ramfc, &priv->ramfc);
+
priv->base.base.destroy = nv04_fifo_destroy;
priv->base.base.init = nv40_fifo_init;
priv->base.base.fini = nv04_fifo_fini;