tree 9963b419762b3bbe9a30544c9543edb199df5cde
parent f10590c9836c9fc595d1dafff965b280029d4f16
author Kisoo Yu <ksoo.yu@samsung.com> 1335304455 -0700
committer Kukjin Kim <kgene.kim@samsung.com> 1337119421 +0900

ARM: EXYNOS: Add pre-divider and fout mux clocks for bpll and mpll

The fout clock of BPLL and MPLL have a selectable source on EXYNOS5250.
The clock options are a fixed divided by 2 clock and the output of the
PLL itself. Add support for these new clock instances.

Signed-off-by: Kisoo Yu <ksoo.yu@samsung.com>
Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
[kgene.kim@samsung.com: moved common pll stuff into s5p-clock.c]
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>