Merge "drm/msm/sde: Initialize the mmu contexts early during probe" into msm-4.9
diff --git a/drivers/gpu/drm/msm/sde/sde_hw_dspp.c b/drivers/gpu/drm/msm/sde/sde_hw_dspp.c
index 8df4de2..586d1f1 100644
--- a/drivers/gpu/drm/msm/sde/sde_hw_dspp.c
+++ b/drivers/gpu/drm/msm/sde/sde_hw_dspp.c
@@ -151,5 +151,7 @@
void sde_hw_dspp_destroy(struct sde_hw_dspp *dspp)
{
+ if (dspp)
+ reg_dmav1_deinit_dspp_ops(dspp->idx);
kfree(dspp);
}
diff --git a/drivers/gpu/drm/msm/sde/sde_hw_reg_dma_v1_color_proc.c b/drivers/gpu/drm/msm/sde/sde_hw_reg_dma_v1_color_proc.c
index 49af946..c33e520 100644
--- a/drivers/gpu/drm/msm/sde/sde_hw_reg_dma_v1_color_proc.c
+++ b/drivers/gpu/drm/msm/sde/sde_hw_reg_dma_v1_color_proc.c
@@ -553,3 +553,26 @@
BIT(0));
SDE_REG_WRITE(&ctx->hw, ctx->cap->sblk->gc.base, reg);
}
+
+int reg_dmav1_deinit_dspp_ops(enum sde_dspp idx)
+{
+ int i;
+ struct sde_hw_reg_dma_ops *dma_ops;
+
+ dma_ops = sde_reg_dma_get_ops();
+ if (IS_ERR_OR_NULL(dma_ops))
+ return -ENOTSUPP;
+
+ if (idx >= DSPP_MAX) {
+ DRM_ERROR("invalid dspp idx %x max %xd\n", idx, DSPP_MAX);
+ return -EINVAL;
+ }
+
+ for (i = 0; i < REG_DMA_FEATURES_MAX; i++) {
+ if (!dspp_buf[i][idx])
+ continue;
+ dma_ops->dealloc_reg_dma(dspp_buf[i][idx]);
+ dspp_buf[i][idx] = NULL;
+ }
+ return 0;
+}
diff --git a/drivers/gpu/drm/msm/sde/sde_hw_reg_dma_v1_color_proc.h b/drivers/gpu/drm/msm/sde/sde_hw_reg_dma_v1_color_proc.h
index e3bf142..94e1a5c 100644
--- a/drivers/gpu/drm/msm/sde/sde_hw_reg_dma_v1_color_proc.h
+++ b/drivers/gpu/drm/msm/sde/sde_hw_reg_dma_v1_color_proc.h
@@ -51,4 +51,11 @@
* @cfg: pointer to struct sde_hw_cp_cfg
*/
void reg_dmav1_setup_dspp_gcv18(struct sde_hw_dspp *ctx, void *cfg);
+
+/**
+ * reg_dmav1_deinit_dspp_ops() - deinitialize the dspp feature op for sde v4
+ * which were initialized.
+ * @idx: dspp idx
+ */
+int reg_dmav1_deinit_dspp_ops(enum sde_dspp idx);
#endif /* _SDE_HW_REG_DMA_V1_COLOR_PROC_H */
diff --git a/drivers/gpu/drm/msm/sde/sde_kms.c b/drivers/gpu/drm/msm/sde/sde_kms.c
index b68d736..8cc196a 100644
--- a/drivers/gpu/drm/msm/sde/sde_kms.c
+++ b/drivers/gpu/drm/msm/sde/sde_kms.c
@@ -1472,6 +1472,16 @@
sde_dbg_init_dbg_buses(sde_kms->core_rev);
+ /*
+ * Now we need to read the HW catalog and initialize resources such as
+ * clocks, regulators, GDSC/MMAGIC, ioremap the register ranges etc
+ */
+ rc = _sde_kms_mmu_init(sde_kms);
+ if (rc) {
+ SDE_ERROR("sde_kms_mmu_init failed: %d\n", rc);
+ goto power_error;
+ }
+
/* Initialize reg dma block which is a singleton */
rc = sde_reg_dma_init(sde_kms->reg_dma, sde_kms->catalog,
sde_kms->dev);
@@ -1521,15 +1531,6 @@
sde_kms->iclient = NULL;
}
- /*
- * Now we need to read the HW catalog and initialize resources such as
- * clocks, regulators, GDSC/MMAGIC, ioremap the register ranges etc
- */
- rc = _sde_kms_mmu_init(sde_kms);
- if (rc) {
- SDE_ERROR("sde_kms_mmu_init failed: %d\n", rc);
- goto power_error;
- }
rc = sde_core_perf_init(&sde_kms->perf, dev, sde_kms->catalog,
&priv->phandle, priv->pclient, "core_clk");