tree f1c3fc761b5e43b85d319f580f9f04991125154d
parent 89e47f62cf3eea7ad5e3d7d72ea846be37d6e352
author Nicolin Chen <Guangyu.Chen@freescale.com> 1399366560 +0800
committer Mark Brown <broonie@linaro.org> 1399932793 +0100

ASoC: fsl_esai: Only bypass sck_div for EXTAL source

ESAI can only output EXTAL clock source directly. But for FSYS clock source,
ESAI can not output it without getting through PSR PM dividers.

So this patch adds an extra check in the code.

Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
Signed-off-by: Mark Brown <broonie@linaro.org>