commit 58cc9c9a175885bbf6bae3acf18233d0a8229a84
author Eric Nelson <eric.nelson@boundarydevices.com> Fri Jan 30 14:07:55 2015 -0700
committer Mark Brown <broonie@kernel.org> Tue Feb 03 13:08:41 2015 +0000
tree 4d65ef4a48db605d32b2dc4013e6236a59b1ba5f
parent 9ee802ec5b1ae0ee468b6acf1bf489347997893b

ASoC: sgtl5000: add delay before first I2C access

To quote from section 1.3.1 of the data sheet:
	The SGTL5000 has an internal reset that is deasserted
	8 SYS_MCLK cycles after all power rails have been brought
	up. After this time, communication can start

	...
	1.0us represents 8 SYS_MCLK cycles at the minimum 8.0 MHz SYS_MCLK.

Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Cc: stable@vger.kernel.org

sound/soc/codecs/sgtl5000.c

diff --git a/sound/soc/codecs/sgtl5000.c b/sound/soc/codecs/sgtl5000.c
index 7665016..aa98be3 100644
--- a/sound/soc/codecs/sgtl5000.c
+++ b/sound/soc/codecs/sgtl5000.c
@@ -1462,6 +1462,9 @@
 	if (ret)
 		return ret;
 
+	/* Need 8 clocks before I2C accesses */
+	udelay(1);
+
 	/* read chip information */
 	ret = regmap_read(sgtl5000->regmap, SGTL5000_CHIP_ID, &reg);
 	if (ret)