| commit | c04bf559264de4f986463c639fabef2028542924 | [log] [tgz] |
|---|---|---|
| author | Thierry Reding <thierry.reding@gmail.com> | Tue Oct 29 16:51:12 2013 +0100 |
| committer | Peter De Schrijver <pdeschrijver@nvidia.com> | Tue Nov 26 18:46:57 2013 +0200 |
| tree | 30bfdeed6283bfb603cad43a5519a09c75570dc4 | |
| parent | 43e36a9646ec7d0180d638c095cca36484cc6f82 [diff] |
clk: tegra: Properly setup PWM clock on Tegra30 The clock for the PWM controller is slightly different from other peripheral clocks on Tegra30. The clock source mux field start at bit position 28 rather than 30. Signed-off-by: Thierry Reding <treding@nvidia.com>