| commit | 5abcd95d8c69008c72d54d7763e0ee2b5df84ac4 | [log] [tgz] |
|---|---|---|
| author | Boris Brezillon <boris.brezillon@free-electrons.com> | Wed Nov 11 22:30:30 2015 +0100 |
| committer | Boris Brezillon <boris.brezillon@free-electrons.com> | Tue Apr 19 22:05:38 2016 +0200 |
| tree | 5eb62927cb19084d9b14071a54c2b24e55736634 | |
| parent | 2d43457f79e48ee427666fdbfe9a53f35d3a1672 [diff] |
mtd: nand: sunxi: adapt clk_rate to tWB, tADL, tWHR and tRHW timings Adapt the NAND controller clk rate to the tWB, tADL, tWHR and tRHW timings instead of returning an error when the maximum clk divisor is not big enough to provide an appropriate timing. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>