tree 5eb62927cb19084d9b14071a54c2b24e55736634
parent 2d43457f79e48ee427666fdbfe9a53f35d3a1672
author Boris Brezillon <boris.brezillon@free-electrons.com> 1447277430 +0100
committer Boris Brezillon <boris.brezillon@free-electrons.com> 1461096338 +0200

mtd: nand: sunxi: adapt clk_rate to tWB, tADL, tWHR and tRHW timings

Adapt the NAND controller clk rate to the tWB, tADL, tWHR and tRHW
timings instead of returning an error when the maximum clk divisor is
not big enough to provide an appropriate timing.

Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>