drm/msm/sde: single kickoff to flush hardware
Existing callflow has multiple points of flush to hardware.
This complicates the callflows, and makes satisfying command mode
and writeback cases difficult since they require triggers based on
event complete irqs. It is important to avoid programming the next
frame's data into hw before the previous frame has completed. For these
reasons we need to buffer flushing of the ctl path, and trigger it
at kickoff time.
This change uses the kickoff callback from the msm layer to consolidate
simple page flip commits and enable/disable commit callflows into a
common kickoff flow.
Change-Id: I565afcf67969da3dbe6e358b5daeffc713b2027c
Signed-off-by: Lloyd Atkinson <latkinso@codeaurora.org>
diff --git a/drivers/gpu/drm/msm/sde/sde_hw_ctl.h b/drivers/gpu/drm/msm/sde/sde_hw_ctl.h
index d5d3445..b5a675e 100644
--- a/drivers/gpu/drm/msm/sde/sde_hw_ctl.h
+++ b/drivers/gpu/drm/msm/sde/sde_hw_ctl.h
@@ -17,6 +17,16 @@
#include "sde_hw_util.h"
#include "sde_hw_catalog.h"
+/**
+ * sde_ctl_mode_sel: Interface mode selection
+ * SDE_CTL_MODE_SEL_VID: Video mode interface
+ * SDE_CTL_MODE_SEL_CMD: Command mode interface
+ */
+enum sde_ctl_mode_sel {
+ SDE_CTL_MODE_SEL_VID = 0,
+ SDE_CTL_MODE_SEL_CMD
+};
+
struct sde_hw_ctl;
/**
* struct sde_hw_stage_cfg - blending stage cfg
@@ -29,16 +39,19 @@
};
/**
- * struct sde_hw_intf_cfg :Desbribes how the mdp writes data to
- * output interface
+ * struct sde_hw_intf_cfg :Describes how the SDE writes data to output interface
* @intf : Interface id
- * @wb: writeback id
+ * @wb: Writeback id
* @mode_3d: 3d mux configuration
+ * @intf_mode_sel: Interface mode, cmd / vid
+ * @stream_sel: Stream selection for multi-stream interfaces
*/
struct sde_hw_intf_cfg {
enum sde_intf intf;
enum sde_wb wb;
enum sde_3d_blend_mode mode_3d;
+ enum sde_ctl_mode_sel intf_mode_sel;
+ int stream_sel;
};
/**
@@ -51,15 +64,29 @@
* DSI cmd mode and WB interface are SW controlled
* @ctx : ctl path ctx pointer
*/
- void (*setup_start)(struct sde_hw_ctl *ctx);
+ void (*trigger_start)(struct sde_hw_ctl *ctx);
/**
- * FLUSH the modules for this control path
+ * Clear the value of the cached pending_flush_mask
+ * No effect on hardware
+ * @ctx : ctl path ctx pointer
+ */
+ void (*clear_pending_flush)(struct sde_hw_ctl *ctx);
+
+ /**
+ * OR in the given flushbits to the cached pending_flush_mask
+ * No effect on hardware
* @ctx : ctl path ctx pointer
* @flushbits : module flushmask
*/
- void (*setup_flush)(struct sde_hw_ctl *ctx,
- u32 flushbits);
+ void (*update_pending_flush)(struct sde_hw_ctl *ctx,
+ u32 flushbits);
+
+ /**
+ * Write the value of the pending_flush_mask to hardware
+ * @ctx : ctl path ctx pointer
+ */
+ void (*trigger_flush)(struct sde_hw_ctl *ctx);
/**
* Setup ctl_path interface config
@@ -98,11 +125,13 @@
/**
* struct sde_hw_ctl : CTL PATH driver object
- * @struct sde_hw_blk_reg_map *hw;
- * @idx
- * @ctl_hw_caps
- * @mixer_hw_caps
- * @ops
+ * @hw: block register map object
+ * @idx: control path index
+ * @ctl_hw_caps: control path capabilities
+ * @mixer_count: number of mixers
+ * @mixer_hw_caps: mixer hardware capabilities
+ * @pending_flush_mask: storage for pending ctl_flush managed via ops
+ * @ops: operation list
*/
struct sde_hw_ctl {
/* base */
@@ -113,6 +142,7 @@
const struct sde_ctl_cfg *caps;
int mixer_count;
const struct sde_lm_cfg *mixer_hw_caps;
+ u32 pending_flush_mask;
/* ops */
struct sde_hw_ctl_ops ops;