tree 928619c9727e20a74565398bd0181a996829f1ce
parent 2374d0af29c154d6d989987a94278caed8c13be5
author LEROY Christophe <christophe.leroy@c-s.fr> 1421747853 +0100
committer Scott Wood <scottwood@freescale.com> 1422590282 -0600

powerpc/8xx: remove tests on PGDIR entry validity

Kernel MMU handling code handles validity of entries via _PMD_PRESENT which
corresponds to V bit in MD_TWC and MI_TWC. When the V bit is not set, MPC8xx
triggers TLBError exception. So we don't have to check that and branch ourself
to TLBError. We can set TLB entries with non present entries, remove all those
tests and let the 8xx handle it. This reduce the number of cycle when the
entries are valid which is the case most of the time, and doesn't significantly
increase the time for handling invalid entries.

Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Scott Wood <scottwood@freescale.com>