[PATCH] S2io: Hardware fixes
Hi,
Below patch addresses few h/w specific issues.
1. Check for additional ownership bit on Rx path before
starting Rx processing.
2. Enable only 4 PCCs(Per Context Controller) for Xframe I
revisions less than 4.
3. Program Rx and Tx round robin registers depending on
no. of rings/FIFOs.
4. Tx continous interrupts is now a loadable parameter.
5. Reset the card if we get double-bit ECC errors.
6. A soft reset of XGXS being done to force a link state change has been
eliminated.
7. After a reset, clear "parity error detected" bit,
PCI-X ECC status register, and PCI_STATUS bit in
tx_pic_int register.
8. The error in the disabling allmulticast implementation has been
rectified.
9. Leave the PCI-X parameters MMRBC, OST etc. at their
BIOS/system defaults.
Signed-off-by: Ravinandan Arakali <ravinandan.arakali@neterion.com>
Signed-off-by: Raghavendra Koushik <raghavendra.koushik@neterion.com>
Signed-off-by: Jeff Garzik <jgarzik@pobox.com>
diff --git a/drivers/net/s2io.h b/drivers/net/s2io.h
index 4d2fc7a..92db59a 100644
--- a/drivers/net/s2io.h
+++ b/drivers/net/s2io.h
@@ -372,6 +372,10 @@
#define RXD_GET_L4_CKSUM(val) ((u16)(val) & 0xFFFF)
u64 Control_2;
+#define THE_RXD_MARK 0x3
+#define SET_RXD_MARKER vBIT(THE_RXD_MARK, 0, 2)
+#define GET_RXD_MARKER(ctrl) ((ctrl & SET_RXD_MARKER) >> 62)
+
#ifndef CONFIG_2BUFF_MODE
#define MASK_BUFFER0_SIZE vBIT(0x3FFF,2,14)
#define SET_BUFFER0_SIZE(val) vBIT(val,2,14)