tree bb03d4a5c0d9d2fb30bcb8cbd6fe13fe237b2643
parent bad50d79255a8a479ea63bea89e859bf08fd0f24
author Felix Fietkau <nbd@nbd.name> 1463421114 +0200
committer Ralf Baechle <ralf@linux-mips.org> 1463476358 +0200

MIPS: ath79: make ath79_ddr_ctrl_init() compatible for newer SoCs

AR913x, AR724x and AR933x are the only SoCs where the
ath79_ddr_wb_flush_base starts at 0x7c, all newer SoCs use 0x9c
Invert the logic to make the code compatible with AR95xx

Signed-off-by: Felix Fietkau <nbd@nbd.name>
Cc: albeu@free.fr
Cc: sergei.shtylyov@cogentembedded.com
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/13257/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>