| commit | 625c0a21700bdb90844d926a1508a17a77e369c9 | [log] [tgz] |
|---|---|---|
| author | Steven J. Hill <sjhill@mips.com> | Tue Aug 28 23:20:08 2012 -0500 |
| committer | Steven J. Hill <sjhill@mips.com> | Thu Sep 13 15:43:52 2012 -0500 |
| tree | cda27e3f4b541e91d92788fa18985bfa20a6b119 | |
| parent | 3234f4466934f08136736790e3de3c6debc71271 [diff] |
MIPS: Avoid pipeline stalls on some MIPS32R2 cores. The architecture specification says that an EHB instruction is needed to avoid a hazard when writing TLB entries. However, some cores do not have this hazard, and thus the EHB instruction causes a costly pipeline stall. Detect these cores and do not use the EHB instruction. Signed-off-by: Steven J. Hill <sjhill@mips.com>