tree 3877decc283a8c351c2c6d55621cf56ee5d6f2ea
parent df7942d17e1623d7358fe895377293637de5521b
author Marc Zyngier <marc.zyngier@arm.com> 1464186396 +0100
committer Christoffer Dall <christoffer.dall@linaro.org> 1464703936 +0200

KVM: arm/arm64: vgic-v3: Always resample level interrupts

When reading back from the list registers, we need to perform
two actions for level interrupts:
1) clear the soft-pending bit if the interrupt is not pending
   anymore *in the list register*
2) resample the line level and propagate it to the pending state

But these two actions shouldn't be linked, and we should *always*
resample the line level, no matter what state is in the list
register. Otherwise, we may end-up injecting spurious interrupts
that have been already retired.

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>