| /* |
| * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ |
| * |
| * This program is free software; you can redistribute it and/or modify |
| * it under the terms of the GNU General Public License version 2 as |
| * published by the Free Software Foundation. |
| * Based on "omap4.dtsi" |
| */ |
| |
| #include <dt-bindings/interrupt-controller/arm-gic.h> |
| #include <dt-bindings/pinctrl/dra.h> |
| |
| #include "skeleton.dtsi" |
| |
| #define MAX_SOURCES 400 |
| #define DIRECT_IRQ(irq) (MAX_SOURCES + irq) |
| |
| / { |
| #address-cells = <1>; |
| #size-cells = <1>; |
| |
| compatible = "ti,dra7xx"; |
| interrupt-parent = <&gic>; |
| |
| aliases { |
| i2c0 = &i2c1; |
| i2c1 = &i2c2; |
| i2c2 = &i2c3; |
| i2c3 = &i2c4; |
| i2c4 = &i2c5; |
| serial0 = &uart1; |
| serial1 = &uart2; |
| serial2 = &uart3; |
| serial3 = &uart4; |
| serial4 = &uart5; |
| serial5 = &uart6; |
| serial6 = &uart7; |
| serial7 = &uart8; |
| serial8 = &uart9; |
| serial9 = &uart10; |
| ethernet0 = &cpsw_emac0; |
| ethernet1 = &cpsw_emac1; |
| d_can0 = &dcan1; |
| d_can1 = &dcan2; |
| }; |
| |
| timer { |
| compatible = "arm,armv7-timer"; |
| interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, |
| <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, |
| <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, |
| <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; |
| }; |
| |
| gic: interrupt-controller@48211000 { |
| compatible = "arm,cortex-a15-gic"; |
| interrupt-controller; |
| #interrupt-cells = <3>; |
| arm,routable-irqs = <192>; |
| reg = <0x48211000 0x1000>, |
| <0x48212000 0x1000>, |
| <0x48214000 0x2000>, |
| <0x48216000 0x2000>; |
| interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; |
| }; |
| |
| /* |
| * The soc node represents the soc top level view. It is used for IPs |
| * that are not memory mapped in the MPU view or for the MPU itself. |
| */ |
| soc { |
| compatible = "ti,omap-infra"; |
| mpu { |
| compatible = "ti,omap5-mpu"; |
| ti,hwmods = "mpu"; |
| }; |
| }; |
| |
| /* |
| * XXX: Use a flat representation of the SOC interconnect. |
| * The real OMAP interconnect network is quite complex. |
| * Since it will not bring real advantage to represent that in DT for |
| * the moment, just use a fake OCP bus entry to represent the whole bus |
| * hierarchy. |
| */ |
| ocp { |
| compatible = "ti,dra7-l3-noc", "simple-bus"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges; |
| ti,hwmods = "l3_main_1", "l3_main_2"; |
| reg = <0x44000000 0x1000000>, |
| <0x45000000 0x1000>; |
| interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI DIRECT_IRQ(10) IRQ_TYPE_LEVEL_HIGH>; |
| |
| prm: prm@4ae06000 { |
| compatible = "ti,dra7-prm"; |
| reg = <0x4ae06000 0x3000>; |
| interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; |
| |
| prm_clocks: clocks { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| }; |
| |
| prm_clockdomains: clockdomains { |
| }; |
| }; |
| |
| axi@0 { |
| compatible = "simple-bus"; |
| #size-cells = <1>; |
| #address-cells = <1>; |
| ranges = <0x51000000 0x51000000 0x3000 |
| 0x0 0x20000000 0x10000000>; |
| pcie@51000000 { |
| compatible = "ti,dra7-pcie"; |
| reg = <0x51000000 0x2000>, <0x51002000 0x14c>, <0x1000 0x2000>; |
| reg-names = "rc_dbics", "ti_conf", "config"; |
| interrupts = <0 232 0x4>, <0 233 0x4>; |
| #address-cells = <3>; |
| #size-cells = <2>; |
| device_type = "pci"; |
| ranges = <0x81000000 0 0 0x03000 0 0x00010000 |
| 0x82000000 0 0x20013000 0x13000 0 0xffed000>; |
| #interrupt-cells = <1>; |
| num-lanes = <1>; |
| ti,hwmods = "pcie1"; |
| phys = <&pcie1_phy>; |
| phy-names = "pcie-phy0"; |
| interrupt-map-mask = <0 0 0 7>; |
| interrupt-map = <0 0 0 1 &pcie1_intc 1>, |
| <0 0 0 2 &pcie1_intc 2>, |
| <0 0 0 3 &pcie1_intc 3>, |
| <0 0 0 4 &pcie1_intc 4>; |
| pcie1_intc: interrupt-controller { |
| interrupt-controller; |
| #address-cells = <0>; |
| #interrupt-cells = <1>; |
| }; |
| }; |
| }; |
| |
| axi@1 { |
| compatible = "simple-bus"; |
| #size-cells = <1>; |
| #address-cells = <1>; |
| ranges = <0x51800000 0x51800000 0x3000 |
| 0x0 0x30000000 0x10000000>; |
| status = "disabled"; |
| pcie@51000000 { |
| compatible = "ti,dra7-pcie"; |
| reg = <0x51800000 0x2000>, <0x51802000 0x14c>, <0x1000 0x2000>; |
| reg-names = "rc_dbics", "ti_conf", "config"; |
| interrupts = <0 355 0x4>, <0 356 0x4>; |
| #address-cells = <3>; |
| #size-cells = <2>; |
| device_type = "pci"; |
| ranges = <0x81000000 0 0 0x03000 0 0x00010000 |
| 0x82000000 0 0x30013000 0x13000 0 0xffed000>; |
| #interrupt-cells = <1>; |
| num-lanes = <1>; |
| ti,hwmods = "pcie2"; |
| phys = <&pcie2_phy>; |
| phy-names = "pcie-phy0"; |
| interrupt-map-mask = <0 0 0 7>; |
| interrupt-map = <0 0 0 1 &pcie2_intc 1>, |
| <0 0 0 2 &pcie2_intc 2>, |
| <0 0 0 3 &pcie2_intc 3>, |
| <0 0 0 4 &pcie2_intc 4>; |
| pcie2_intc: interrupt-controller { |
| interrupt-controller; |
| #address-cells = <0>; |
| #interrupt-cells = <1>; |
| }; |
| }; |
| }; |
| |
| cm_core_aon: cm_core_aon@4a005000 { |
| compatible = "ti,dra7-cm-core-aon"; |
| reg = <0x4a005000 0x2000>; |
| |
| cm_core_aon_clocks: clocks { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| }; |
| |
| cm_core_aon_clockdomains: clockdomains { |
| }; |
| }; |
| |
| cm_core: cm_core@4a008000 { |
| compatible = "ti,dra7-cm-core"; |
| reg = <0x4a008000 0x3000>; |
| |
| cm_core_clocks: clocks { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| }; |
| |
| cm_core_clockdomains: clockdomains { |
| }; |
| }; |
| |
| counter32k: counter@4ae04000 { |
| compatible = "ti,omap-counter32k"; |
| reg = <0x4ae04000 0x40>; |
| ti,hwmods = "counter_32k"; |
| }; |
| |
| dra7_ctrl_core: ctrl_core@4a002000 { |
| compatible = "syscon"; |
| reg = <0x4a002000 0x6d0>; |
| }; |
| |
| dra7_ctrl_general: tisyscon@4a002e00 { |
| compatible = "syscon"; |
| reg = <0x4a002e00 0x7c>; |
| }; |
| |
| pbias_regulator: pbias_regulator { |
| compatible = "ti,pbias-omap"; |
| reg = <0 0x4>; |
| syscon = <&dra7_ctrl_general>; |
| pbias_mmc_reg: pbias_mmc_omap5 { |
| regulator-name = "pbias_mmc_omap5"; |
| regulator-min-microvolt = <1800000>; |
| regulator-max-microvolt = <3000000>; |
| }; |
| }; |
| |
| dra7_pmx_core: pinmux@4a003400 { |
| compatible = "ti,dra7-padconf", "pinctrl-single"; |
| reg = <0x4a003400 0x0464>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| #interrupt-cells = <1>; |
| interrupt-controller; |
| pinctrl-single,register-width = <32>; |
| pinctrl-single,function-mask = <0x3fffffff>; |
| }; |
| |
| sdma: dma-controller@4a056000 { |
| compatible = "ti,omap4430-sdma"; |
| reg = <0x4a056000 0x1000>; |
| interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; |
| #dma-cells = <1>; |
| #dma-channels = <32>; |
| #dma-requests = <127>; |
| }; |
| |
| gpio1: gpio@4ae10000 { |
| compatible = "ti,omap4-gpio"; |
| reg = <0x4ae10000 0x200>; |
| interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; |
| ti,hwmods = "gpio1"; |
| gpio-controller; |
| #gpio-cells = <2>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| }; |
| |
| gpio2: gpio@48055000 { |
| compatible = "ti,omap4-gpio"; |
| reg = <0x48055000 0x200>; |
| interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; |
| ti,hwmods = "gpio2"; |
| gpio-controller; |
| #gpio-cells = <2>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| }; |
| |
| gpio3: gpio@48057000 { |
| compatible = "ti,omap4-gpio"; |
| reg = <0x48057000 0x200>; |
| interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; |
| ti,hwmods = "gpio3"; |
| gpio-controller; |
| #gpio-cells = <2>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| }; |
| |
| gpio4: gpio@48059000 { |
| compatible = "ti,omap4-gpio"; |
| reg = <0x48059000 0x200>; |
| interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; |
| ti,hwmods = "gpio4"; |
| gpio-controller; |
| #gpio-cells = <2>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| }; |
| |
| gpio5: gpio@4805b000 { |
| compatible = "ti,omap4-gpio"; |
| reg = <0x4805b000 0x200>; |
| interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; |
| ti,hwmods = "gpio5"; |
| gpio-controller; |
| #gpio-cells = <2>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| }; |
| |
| gpio6: gpio@4805d000 { |
| compatible = "ti,omap4-gpio"; |
| reg = <0x4805d000 0x200>; |
| interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; |
| ti,hwmods = "gpio6"; |
| gpio-controller; |
| #gpio-cells = <2>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| }; |
| |
| gpio7: gpio@48051000 { |
| compatible = "ti,omap4-gpio"; |
| reg = <0x48051000 0x200>; |
| interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; |
| ti,hwmods = "gpio7"; |
| gpio-controller; |
| #gpio-cells = <2>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| }; |
| |
| gpio8: gpio@48053000 { |
| compatible = "ti,omap4-gpio"; |
| reg = <0x48053000 0x200>; |
| interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; |
| ti,hwmods = "gpio8"; |
| gpio-controller; |
| #gpio-cells = <2>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| }; |
| |
| uart1: serial@4806a000 { |
| compatible = "ti,omap4-uart"; |
| reg = <0x4806a000 0x100>; |
| interrupts-extended = <&gic GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; |
| ti,hwmods = "uart1"; |
| clock-frequency = <48000000>; |
| status = "disabled"; |
| dmas = <&sdma 49>, <&sdma 50>; |
| dma-names = "tx", "rx"; |
| }; |
| |
| uart2: serial@4806c000 { |
| compatible = "ti,omap4-uart"; |
| reg = <0x4806c000 0x100>; |
| interrupts-extended = <&gic GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; |
| ti,hwmods = "uart2"; |
| clock-frequency = <48000000>; |
| status = "disabled"; |
| dmas = <&sdma 51>, <&sdma 52>; |
| dma-names = "tx", "rx"; |
| }; |
| |
| uart3: serial@48020000 { |
| compatible = "ti,omap4-uart"; |
| reg = <0x48020000 0x100>; |
| interrupts-extended = <&gic GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; |
| ti,hwmods = "uart3"; |
| clock-frequency = <48000000>; |
| status = "disabled"; |
| dmas = <&sdma 53>, <&sdma 54>; |
| dma-names = "tx", "rx"; |
| }; |
| |
| uart4: serial@4806e000 { |
| compatible = "ti,omap4-uart"; |
| reg = <0x4806e000 0x100>; |
| interrupts-extended = <&gic GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; |
| ti,hwmods = "uart4"; |
| clock-frequency = <48000000>; |
| status = "disabled"; |
| dmas = <&sdma 55>, <&sdma 56>; |
| dma-names = "tx", "rx"; |
| }; |
| |
| uart5: serial@48066000 { |
| compatible = "ti,omap4-uart"; |
| reg = <0x48066000 0x100>; |
| interrupts-extended = <&gic GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; |
| ti,hwmods = "uart5"; |
| clock-frequency = <48000000>; |
| status = "disabled"; |
| dmas = <&sdma 63>, <&sdma 64>; |
| dma-names = "tx", "rx"; |
| }; |
| |
| uart6: serial@48068000 { |
| compatible = "ti,omap4-uart"; |
| reg = <0x48068000 0x100>; |
| interrupts-extended = <&gic GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; |
| ti,hwmods = "uart6"; |
| clock-frequency = <48000000>; |
| status = "disabled"; |
| dmas = <&sdma 79>, <&sdma 80>; |
| dma-names = "tx", "rx"; |
| }; |
| |
| uart7: serial@48420000 { |
| compatible = "ti,omap4-uart"; |
| reg = <0x48420000 0x100>; |
| interrupts-extended = <&gic GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>; |
| ti,hwmods = "uart7"; |
| clock-frequency = <48000000>; |
| status = "disabled"; |
| }; |
| |
| uart8: serial@48422000 { |
| compatible = "ti,omap4-uart"; |
| reg = <0x48422000 0x100>; |
| interrupts-extended = <&gic GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>; |
| ti,hwmods = "uart8"; |
| clock-frequency = <48000000>; |
| status = "disabled"; |
| }; |
| |
| uart9: serial@48424000 { |
| compatible = "ti,omap4-uart"; |
| reg = <0x48424000 0x100>; |
| interrupts-extended = <&gic GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>; |
| ti,hwmods = "uart9"; |
| clock-frequency = <48000000>; |
| status = "disabled"; |
| }; |
| |
| uart10: serial@4ae2b000 { |
| compatible = "ti,omap4-uart"; |
| reg = <0x4ae2b000 0x100>; |
| interrupts-extended = <&gic GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; |
| ti,hwmods = "uart10"; |
| clock-frequency = <48000000>; |
| status = "disabled"; |
| }; |
| |
| mailbox1: mailbox@4a0f4000 { |
| compatible = "ti,omap4-mailbox"; |
| reg = <0x4a0f4000 0x200>; |
| interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; |
| ti,hwmods = "mailbox1"; |
| #mbox-cells = <1>; |
| ti,mbox-num-users = <3>; |
| ti,mbox-num-fifos = <8>; |
| status = "disabled"; |
| }; |
| |
| mailbox2: mailbox@4883a000 { |
| compatible = "ti,omap4-mailbox"; |
| reg = <0x4883a000 0x200>; |
| interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; |
| ti,hwmods = "mailbox2"; |
| #mbox-cells = <1>; |
| ti,mbox-num-users = <4>; |
| ti,mbox-num-fifos = <12>; |
| status = "disabled"; |
| }; |
| |
| mailbox3: mailbox@4883c000 { |
| compatible = "ti,omap4-mailbox"; |
| reg = <0x4883c000 0x200>; |
| interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>; |
| ti,hwmods = "mailbox3"; |
| #mbox-cells = <1>; |
| ti,mbox-num-users = <4>; |
| ti,mbox-num-fifos = <12>; |
| status = "disabled"; |
| }; |
| |
| mailbox4: mailbox@4883e000 { |
| compatible = "ti,omap4-mailbox"; |
| reg = <0x4883e000 0x200>; |
| interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>; |
| ti,hwmods = "mailbox4"; |
| #mbox-cells = <1>; |
| ti,mbox-num-users = <4>; |
| ti,mbox-num-fifos = <12>; |
| status = "disabled"; |
| }; |
| |
| mailbox5: mailbox@48840000 { |
| compatible = "ti,omap4-mailbox"; |
| reg = <0x48840000 0x200>; |
| interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>; |
| ti,hwmods = "mailbox5"; |
| #mbox-cells = <1>; |
| ti,mbox-num-users = <4>; |
| ti,mbox-num-fifos = <12>; |
| status = "disabled"; |
| }; |
| |
| mailbox6: mailbox@48842000 { |
| compatible = "ti,omap4-mailbox"; |
| reg = <0x48842000 0x200>; |
| interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>; |
| ti,hwmods = "mailbox6"; |
| #mbox-cells = <1>; |
| ti,mbox-num-users = <4>; |
| ti,mbox-num-fifos = <12>; |
| status = "disabled"; |
| }; |
| |
| mailbox7: mailbox@48844000 { |
| compatible = "ti,omap4-mailbox"; |
| reg = <0x48844000 0x200>; |
| interrupts = <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>; |
| ti,hwmods = "mailbox7"; |
| #mbox-cells = <1>; |
| ti,mbox-num-users = <4>; |
| ti,mbox-num-fifos = <12>; |
| status = "disabled"; |
| }; |
| |
| mailbox8: mailbox@48846000 { |
| compatible = "ti,omap4-mailbox"; |
| reg = <0x48846000 0x200>; |
| interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>; |
| ti,hwmods = "mailbox8"; |
| #mbox-cells = <1>; |
| ti,mbox-num-users = <4>; |
| ti,mbox-num-fifos = <12>; |
| status = "disabled"; |
| }; |
| |
| mailbox9: mailbox@4885e000 { |
| compatible = "ti,omap4-mailbox"; |
| reg = <0x4885e000 0x200>; |
| interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; |
| ti,hwmods = "mailbox9"; |
| #mbox-cells = <1>; |
| ti,mbox-num-users = <4>; |
| ti,mbox-num-fifos = <12>; |
| status = "disabled"; |
| }; |
| |
| mailbox10: mailbox@48860000 { |
| compatible = "ti,omap4-mailbox"; |
| reg = <0x48860000 0x200>; |
| interrupts = <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; |
| ti,hwmods = "mailbox10"; |
| #mbox-cells = <1>; |
| ti,mbox-num-users = <4>; |
| ti,mbox-num-fifos = <12>; |
| status = "disabled"; |
| }; |
| |
| mailbox11: mailbox@48862000 { |
| compatible = "ti,omap4-mailbox"; |
| reg = <0x48862000 0x200>; |
| interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>; |
| ti,hwmods = "mailbox11"; |
| #mbox-cells = <1>; |
| ti,mbox-num-users = <4>; |
| ti,mbox-num-fifos = <12>; |
| status = "disabled"; |
| }; |
| |
| mailbox12: mailbox@48864000 { |
| compatible = "ti,omap4-mailbox"; |
| reg = <0x48864000 0x200>; |
| interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>; |
| ti,hwmods = "mailbox12"; |
| #mbox-cells = <1>; |
| ti,mbox-num-users = <4>; |
| ti,mbox-num-fifos = <12>; |
| status = "disabled"; |
| }; |
| |
| mailbox13: mailbox@48802000 { |
| compatible = "ti,omap4-mailbox"; |
| reg = <0x48802000 0x200>; |
| interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>; |
| ti,hwmods = "mailbox13"; |
| #mbox-cells = <1>; |
| ti,mbox-num-users = <4>; |
| ti,mbox-num-fifos = <12>; |
| status = "disabled"; |
| }; |
| |
| timer1: timer@4ae18000 { |
| compatible = "ti,omap5430-timer"; |
| reg = <0x4ae18000 0x80>; |
| interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; |
| ti,hwmods = "timer1"; |
| ti,timer-alwon; |
| }; |
| |
| timer2: timer@48032000 { |
| compatible = "ti,omap5430-timer"; |
| reg = <0x48032000 0x80>; |
| interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; |
| ti,hwmods = "timer2"; |
| }; |
| |
| timer3: timer@48034000 { |
| compatible = "ti,omap5430-timer"; |
| reg = <0x48034000 0x80>; |
| interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; |
| ti,hwmods = "timer3"; |
| }; |
| |
| timer4: timer@48036000 { |
| compatible = "ti,omap5430-timer"; |
| reg = <0x48036000 0x80>; |
| interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; |
| ti,hwmods = "timer4"; |
| }; |
| |
| timer5: timer@48820000 { |
| compatible = "ti,omap5430-timer"; |
| reg = <0x48820000 0x80>; |
| interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; |
| ti,hwmods = "timer5"; |
| ti,timer-dsp; |
| }; |
| |
| timer6: timer@48822000 { |
| compatible = "ti,omap5430-timer"; |
| reg = <0x48822000 0x80>; |
| interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; |
| ti,hwmods = "timer6"; |
| ti,timer-dsp; |
| ti,timer-pwm; |
| }; |
| |
| timer7: timer@48824000 { |
| compatible = "ti,omap5430-timer"; |
| reg = <0x48824000 0x80>; |
| interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; |
| ti,hwmods = "timer7"; |
| ti,timer-dsp; |
| }; |
| |
| timer8: timer@48826000 { |
| compatible = "ti,omap5430-timer"; |
| reg = <0x48826000 0x80>; |
| interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; |
| ti,hwmods = "timer8"; |
| ti,timer-dsp; |
| ti,timer-pwm; |
| }; |
| |
| timer9: timer@4803e000 { |
| compatible = "ti,omap5430-timer"; |
| reg = <0x4803e000 0x80>; |
| interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; |
| ti,hwmods = "timer9"; |
| }; |
| |
| timer10: timer@48086000 { |
| compatible = "ti,omap5430-timer"; |
| reg = <0x48086000 0x80>; |
| interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; |
| ti,hwmods = "timer10"; |
| }; |
| |
| timer11: timer@48088000 { |
| compatible = "ti,omap5430-timer"; |
| reg = <0x48088000 0x80>; |
| interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; |
| ti,hwmods = "timer11"; |
| ti,timer-pwm; |
| }; |
| |
| timer13: timer@48828000 { |
| compatible = "ti,omap5430-timer"; |
| reg = <0x48828000 0x80>; |
| interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>; |
| ti,hwmods = "timer13"; |
| status = "disabled"; |
| }; |
| |
| timer14: timer@4882a000 { |
| compatible = "ti,omap5430-timer"; |
| reg = <0x4882a000 0x80>; |
| interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>; |
| ti,hwmods = "timer14"; |
| status = "disabled"; |
| }; |
| |
| timer15: timer@4882c000 { |
| compatible = "ti,omap5430-timer"; |
| reg = <0x4882c000 0x80>; |
| interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>; |
| ti,hwmods = "timer15"; |
| status = "disabled"; |
| }; |
| |
| timer16: timer@4882e000 { |
| compatible = "ti,omap5430-timer"; |
| reg = <0x4882e000 0x80>; |
| interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>; |
| ti,hwmods = "timer16"; |
| status = "disabled"; |
| }; |
| |
| wdt2: wdt@4ae14000 { |
| compatible = "ti,omap3-wdt"; |
| reg = <0x4ae14000 0x80>; |
| interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; |
| ti,hwmods = "wd_timer2"; |
| }; |
| |
| hwspinlock: spinlock@4a0f6000 { |
| compatible = "ti,omap4-hwspinlock"; |
| reg = <0x4a0f6000 0x1000>; |
| ti,hwmods = "spinlock"; |
| #hwlock-cells = <1>; |
| }; |
| |
| dmm@4e000000 { |
| compatible = "ti,omap5-dmm"; |
| reg = <0x4e000000 0x800>; |
| interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; |
| ti,hwmods = "dmm"; |
| }; |
| |
| i2c1: i2c@48070000 { |
| compatible = "ti,omap4-i2c"; |
| reg = <0x48070000 0x100>; |
| interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| ti,hwmods = "i2c1"; |
| status = "disabled"; |
| }; |
| |
| i2c2: i2c@48072000 { |
| compatible = "ti,omap4-i2c"; |
| reg = <0x48072000 0x100>; |
| interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| ti,hwmods = "i2c2"; |
| status = "disabled"; |
| }; |
| |
| i2c3: i2c@48060000 { |
| compatible = "ti,omap4-i2c"; |
| reg = <0x48060000 0x100>; |
| interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| ti,hwmods = "i2c3"; |
| status = "disabled"; |
| }; |
| |
| i2c4: i2c@4807a000 { |
| compatible = "ti,omap4-i2c"; |
| reg = <0x4807a000 0x100>; |
| interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| ti,hwmods = "i2c4"; |
| status = "disabled"; |
| }; |
| |
| i2c5: i2c@4807c000 { |
| compatible = "ti,omap4-i2c"; |
| reg = <0x4807c000 0x100>; |
| interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| ti,hwmods = "i2c5"; |
| status = "disabled"; |
| }; |
| |
| mmc1: mmc@4809c000 { |
| compatible = "ti,omap4-hsmmc"; |
| reg = <0x4809c000 0x400>; |
| interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; |
| ti,hwmods = "mmc1"; |
| ti,dual-volt; |
| ti,needs-special-reset; |
| dmas = <&sdma 61>, <&sdma 62>; |
| dma-names = "tx", "rx"; |
| status = "disabled"; |
| pbias-supply = <&pbias_mmc_reg>; |
| }; |
| |
| mmc2: mmc@480b4000 { |
| compatible = "ti,omap4-hsmmc"; |
| reg = <0x480b4000 0x400>; |
| interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; |
| ti,hwmods = "mmc2"; |
| ti,needs-special-reset; |
| dmas = <&sdma 47>, <&sdma 48>; |
| dma-names = "tx", "rx"; |
| status = "disabled"; |
| }; |
| |
| mmc3: mmc@480ad000 { |
| compatible = "ti,omap4-hsmmc"; |
| reg = <0x480ad000 0x400>; |
| interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; |
| ti,hwmods = "mmc3"; |
| ti,needs-special-reset; |
| dmas = <&sdma 77>, <&sdma 78>; |
| dma-names = "tx", "rx"; |
| status = "disabled"; |
| }; |
| |
| mmc4: mmc@480d1000 { |
| compatible = "ti,omap4-hsmmc"; |
| reg = <0x480d1000 0x400>; |
| interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; |
| ti,hwmods = "mmc4"; |
| ti,needs-special-reset; |
| dmas = <&sdma 57>, <&sdma 58>; |
| dma-names = "tx", "rx"; |
| status = "disabled"; |
| }; |
| |
| abb_mpu: regulator-abb-mpu { |
| compatible = "ti,abb-v3"; |
| regulator-name = "abb_mpu"; |
| #address-cells = <0>; |
| #size-cells = <0>; |
| clocks = <&sys_clkin1>; |
| ti,settling-time = <50>; |
| ti,clock-cycles = <16>; |
| |
| reg = <0x4ae07ddc 0x4>, <0x4ae07de0 0x4>, |
| <0x4ae06014 0x4>, <0x4a003b20 0x8>, |
| <0x4ae0c158 0x4>; |
| reg-names = "setup-address", "control-address", |
| "int-address", "efuse-address", |
| "ldo-address"; |
| ti,tranxdone-status-mask = <0x80>; |
| /* LDOVBBMPU_FBB_MUX_CTRL */ |
| ti,ldovbb-override-mask = <0x400>; |
| /* LDOVBBMPU_FBB_VSET_OUT */ |
| ti,ldovbb-vset-mask = <0x1F>; |
| |
| /* |
| * NOTE: only FBB mode used but actual vset will |
| * determine final biasing |
| */ |
| ti,abb_info = < |
| /*uV ABB efuse rbb_m fbb_m vset_m*/ |
| 1060000 0 0x0 0 0x02000000 0x01F00000 |
| 1160000 0 0x4 0 0x02000000 0x01F00000 |
| 1210000 0 0x8 0 0x02000000 0x01F00000 |
| >; |
| }; |
| |
| abb_ivahd: regulator-abb-ivahd { |
| compatible = "ti,abb-v3"; |
| regulator-name = "abb_ivahd"; |
| #address-cells = <0>; |
| #size-cells = <0>; |
| clocks = <&sys_clkin1>; |
| ti,settling-time = <50>; |
| ti,clock-cycles = <16>; |
| |
| reg = <0x4ae07e34 0x4>, <0x4ae07e24 0x4>, |
| <0x4ae06010 0x4>, <0x4a0025cc 0x8>, |
| <0x4a002470 0x4>; |
| reg-names = "setup-address", "control-address", |
| "int-address", "efuse-address", |
| "ldo-address"; |
| ti,tranxdone-status-mask = <0x40000000>; |
| /* LDOVBBIVA_FBB_MUX_CTRL */ |
| ti,ldovbb-override-mask = <0x400>; |
| /* LDOVBBIVA_FBB_VSET_OUT */ |
| ti,ldovbb-vset-mask = <0x1F>; |
| |
| /* |
| * NOTE: only FBB mode used but actual vset will |
| * determine final biasing |
| */ |
| ti,abb_info = < |
| /*uV ABB efuse rbb_m fbb_m vset_m*/ |
| 1055000 0 0x0 0 0x02000000 0x01F00000 |
| 1150000 0 0x4 0 0x02000000 0x01F00000 |
| 1250000 0 0x8 0 0x02000000 0x01F00000 |
| >; |
| }; |
| |
| abb_dspeve: regulator-abb-dspeve { |
| compatible = "ti,abb-v3"; |
| regulator-name = "abb_dspeve"; |
| #address-cells = <0>; |
| #size-cells = <0>; |
| clocks = <&sys_clkin1>; |
| ti,settling-time = <50>; |
| ti,clock-cycles = <16>; |
| |
| reg = <0x4ae07e30 0x4>, <0x4ae07e20 0x4>, |
| <0x4ae06010 0x4>, <0x4a0025e0 0x8>, |
| <0x4a00246c 0x4>; |
| reg-names = "setup-address", "control-address", |
| "int-address", "efuse-address", |
| "ldo-address"; |
| ti,tranxdone-status-mask = <0x20000000>; |
| /* LDOVBBDSPEVE_FBB_MUX_CTRL */ |
| ti,ldovbb-override-mask = <0x400>; |
| /* LDOVBBDSPEVE_FBB_VSET_OUT */ |
| ti,ldovbb-vset-mask = <0x1F>; |
| |
| /* |
| * NOTE: only FBB mode used but actual vset will |
| * determine final biasing |
| */ |
| ti,abb_info = < |
| /*uV ABB efuse rbb_m fbb_m vset_m*/ |
| 1055000 0 0x0 0 0x02000000 0x01F00000 |
| 1150000 0 0x4 0 0x02000000 0x01F00000 |
| 1250000 0 0x8 0 0x02000000 0x01F00000 |
| >; |
| }; |
| |
| abb_gpu: regulator-abb-gpu { |
| compatible = "ti,abb-v3"; |
| regulator-name = "abb_gpu"; |
| #address-cells = <0>; |
| #size-cells = <0>; |
| clocks = <&sys_clkin1>; |
| ti,settling-time = <50>; |
| ti,clock-cycles = <16>; |
| |
| reg = <0x4ae07de4 0x4>, <0x4ae07de8 0x4>, |
| <0x4ae06010 0x4>, <0x4a003b08 0x8>, |
| <0x4ae0c154 0x4>; |
| reg-names = "setup-address", "control-address", |
| "int-address", "efuse-address", |
| "ldo-address"; |
| ti,tranxdone-status-mask = <0x10000000>; |
| /* LDOVBBGPU_FBB_MUX_CTRL */ |
| ti,ldovbb-override-mask = <0x400>; |
| /* LDOVBBGPU_FBB_VSET_OUT */ |
| ti,ldovbb-vset-mask = <0x1F>; |
| |
| /* |
| * NOTE: only FBB mode used but actual vset will |
| * determine final biasing |
| */ |
| ti,abb_info = < |
| /*uV ABB efuse rbb_m fbb_m vset_m*/ |
| 1090000 0 0x0 0 0x02000000 0x01F00000 |
| 1210000 0 0x4 0 0x02000000 0x01F00000 |
| 1280000 0 0x8 0 0x02000000 0x01F00000 |
| >; |
| }; |
| |
| mcspi1: spi@48098000 { |
| compatible = "ti,omap4-mcspi"; |
| reg = <0x48098000 0x200>; |
| interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| ti,hwmods = "mcspi1"; |
| ti,spi-num-cs = <4>; |
| dmas = <&sdma 35>, |
| <&sdma 36>, |
| <&sdma 37>, |
| <&sdma 38>, |
| <&sdma 39>, |
| <&sdma 40>, |
| <&sdma 41>, |
| <&sdma 42>; |
| dma-names = "tx0", "rx0", "tx1", "rx1", |
| "tx2", "rx2", "tx3", "rx3"; |
| status = "disabled"; |
| }; |
| |
| mcspi2: spi@4809a000 { |
| compatible = "ti,omap4-mcspi"; |
| reg = <0x4809a000 0x200>; |
| interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| ti,hwmods = "mcspi2"; |
| ti,spi-num-cs = <2>; |
| dmas = <&sdma 43>, |
| <&sdma 44>, |
| <&sdma 45>, |
| <&sdma 46>; |
| dma-names = "tx0", "rx0", "tx1", "rx1"; |
| status = "disabled"; |
| }; |
| |
| mcspi3: spi@480b8000 { |
| compatible = "ti,omap4-mcspi"; |
| reg = <0x480b8000 0x200>; |
| interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| ti,hwmods = "mcspi3"; |
| ti,spi-num-cs = <2>; |
| dmas = <&sdma 15>, <&sdma 16>; |
| dma-names = "tx0", "rx0"; |
| status = "disabled"; |
| }; |
| |
| mcspi4: spi@480ba000 { |
| compatible = "ti,omap4-mcspi"; |
| reg = <0x480ba000 0x200>; |
| interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| ti,hwmods = "mcspi4"; |
| ti,spi-num-cs = <1>; |
| dmas = <&sdma 70>, <&sdma 71>; |
| dma-names = "tx0", "rx0"; |
| status = "disabled"; |
| }; |
| |
| qspi: qspi@4b300000 { |
| compatible = "ti,dra7xxx-qspi"; |
| reg = <0x4b300000 0x100>; |
| reg-names = "qspi_base"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| ti,hwmods = "qspi"; |
| clocks = <&qspi_gfclk_div>; |
| clock-names = "fck"; |
| num-cs = <4>; |
| interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>; |
| status = "disabled"; |
| }; |
| |
| omap_control_sata: control-phy@4a002374 { |
| compatible = "ti,control-phy-pipe3"; |
| reg = <0x4a002374 0x4>; |
| reg-names = "power"; |
| clocks = <&sys_clkin1>; |
| clock-names = "sysclk"; |
| }; |
| |
| /* OCP2SCP3 */ |
| ocp2scp@4a090000 { |
| compatible = "ti,omap-ocp2scp"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges; |
| reg = <0x4a090000 0x20>; |
| ti,hwmods = "ocp2scp3"; |
| sata_phy: phy@4A096000 { |
| compatible = "ti,phy-pipe3-sata"; |
| reg = <0x4A096000 0x80>, /* phy_rx */ |
| <0x4A096400 0x64>, /* phy_tx */ |
| <0x4A096800 0x40>; /* pll_ctrl */ |
| reg-names = "phy_rx", "phy_tx", "pll_ctrl"; |
| ctrl-module = <&omap_control_sata>; |
| clocks = <&sys_clkin1>; |
| clock-names = "sysclk"; |
| #phy-cells = <0>; |
| }; |
| |
| pcie1_phy: pciephy@4a094000 { |
| compatible = "ti,phy-pipe3-pcie"; |
| reg = <0x4a094000 0x80>, /* phy_rx */ |
| <0x4a094400 0x64>; /* phy_tx */ |
| reg-names = "phy_rx", "phy_tx"; |
| ctrl-module = <&omap_control_pcie1phy>; |
| clocks = <&dpll_pcie_ref_ck>, |
| <&dpll_pcie_ref_m2ldo_ck>, |
| <&optfclk_pciephy1_32khz>, |
| <&optfclk_pciephy1_clk>, |
| <&optfclk_pciephy1_div_clk>, |
| <&optfclk_pciephy_div>; |
| clock-names = "dpll_ref", "dpll_ref_m2", |
| "wkupclk", "refclk", |
| "div-clk", "phy-div"; |
| #phy-cells = <0>; |
| id = <1>; |
| ti,hwmods = "pcie1-phy"; |
| }; |
| |
| pcie2_phy: pciephy@4a095000 { |
| compatible = "ti,phy-pipe3-pcie"; |
| reg = <0x4a095000 0x80>, /* phy_rx */ |
| <0x4a095400 0x64>; /* phy_tx */ |
| reg-names = "phy_rx", "phy_tx"; |
| ctrl-module = <&omap_control_pcie2phy>; |
| clocks = <&dpll_pcie_ref_ck>, |
| <&dpll_pcie_ref_m2ldo_ck>, |
| <&optfclk_pciephy2_32khz>, |
| <&optfclk_pciephy2_clk>, |
| <&optfclk_pciephy2_div_clk>, |
| <&optfclk_pciephy_div>; |
| clock-names = "dpll_ref", "dpll_ref_m2", |
| "wkupclk", "refclk", |
| "div-clk", "phy-div"; |
| #phy-cells = <0>; |
| ti,hwmods = "pcie2-phy"; |
| id = <2>; |
| status = "disabled"; |
| }; |
| }; |
| |
| sata: sata@4a141100 { |
| compatible = "snps,dwc-ahci"; |
| reg = <0x4a140000 0x1100>, <0x4a141100 0x7>; |
| interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; |
| phys = <&sata_phy>; |
| phy-names = "sata-phy"; |
| clocks = <&sata_ref_clk>; |
| ti,hwmods = "sata"; |
| }; |
| |
| omap_control_pcie1phy: control-phy@0x4a003c40 { |
| compatible = "ti,control-phy-pcie"; |
| reg = <0x4a003c40 0x4>, <0x4a003c14 0x4>, <0x4a003c34 0x4>; |
| reg-names = "power", "control_sma", "pcie_pcs"; |
| clocks = <&sys_clkin1>; |
| clock-names = "sysclk"; |
| }; |
| |
| omap_control_pcie2phy: control-pcie@0x4a003c44 { |
| compatible = "ti,control-phy-pcie"; |
| reg = <0x4a003c44 0x4>, <0x4a003c14 0x4>, <0x4a003c34 0x4>; |
| reg-names = "power", "control_sma", "pcie_pcs"; |
| clocks = <&sys_clkin1>; |
| clock-names = "sysclk"; |
| status = "disabled"; |
| }; |
| |
| rtc@48838000 { |
| compatible = "ti,am3352-rtc"; |
| reg = <0x48838000 0x100>; |
| interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>; |
| ti,hwmods = "rtcss"; |
| clocks = <&sys_32k_ck>; |
| }; |
| |
| omap_control_usb2phy1: control-phy@4a002300 { |
| compatible = "ti,control-phy-usb2"; |
| reg = <0x4a002300 0x4>; |
| reg-names = "power"; |
| }; |
| |
| omap_control_usb3phy1: control-phy@4a002370 { |
| compatible = "ti,control-phy-pipe3"; |
| reg = <0x4a002370 0x4>; |
| reg-names = "power"; |
| }; |
| |
| omap_control_usb2phy2: control-phy@0x4a002e74 { |
| compatible = "ti,control-phy-usb2-dra7"; |
| reg = <0x4a002e74 0x4>; |
| reg-names = "power"; |
| }; |
| |
| /* OCP2SCP1 */ |
| ocp2scp@4a080000 { |
| compatible = "ti,omap-ocp2scp"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges; |
| reg = <0x4a080000 0x20>; |
| ti,hwmods = "ocp2scp1"; |
| |
| usb2_phy1: phy@4a084000 { |
| compatible = "ti,omap-usb2"; |
| reg = <0x4a084000 0x400>; |
| ctrl-module = <&omap_control_usb2phy1>; |
| clocks = <&usb_phy1_always_on_clk32k>, |
| <&usb_otg_ss1_refclk960m>; |
| clock-names = "wkupclk", |
| "refclk"; |
| #phy-cells = <0>; |
| }; |
| |
| usb2_phy2: phy@4a085000 { |
| compatible = "ti,omap-usb2"; |
| reg = <0x4a085000 0x400>; |
| ctrl-module = <&omap_control_usb2phy2>; |
| clocks = <&usb_phy2_always_on_clk32k>, |
| <&usb_otg_ss2_refclk960m>; |
| clock-names = "wkupclk", |
| "refclk"; |
| #phy-cells = <0>; |
| }; |
| |
| usb3_phy1: phy@4a084400 { |
| compatible = "ti,omap-usb3"; |
| reg = <0x4a084400 0x80>, |
| <0x4a084800 0x64>, |
| <0x4a084c00 0x40>; |
| reg-names = "phy_rx", "phy_tx", "pll_ctrl"; |
| ctrl-module = <&omap_control_usb3phy1>; |
| clocks = <&usb_phy3_always_on_clk32k>, |
| <&sys_clkin1>, |
| <&usb_otg_ss1_refclk960m>; |
| clock-names = "wkupclk", |
| "sysclk", |
| "refclk"; |
| #phy-cells = <0>; |
| }; |
| }; |
| |
| omap_dwc3_1: omap_dwc3_1@48880000 { |
| compatible = "ti,dwc3"; |
| ti,hwmods = "usb_otg_ss1"; |
| reg = <0x48880000 0x10000>; |
| interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| utmi-mode = <2>; |
| ranges; |
| usb1: usb@48890000 { |
| compatible = "snps,dwc3"; |
| reg = <0x48890000 0x17000>; |
| interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; |
| phys = <&usb2_phy1>, <&usb3_phy1>; |
| phy-names = "usb2-phy", "usb3-phy"; |
| tx-fifo-resize; |
| maximum-speed = "super-speed"; |
| dr_mode = "otg"; |
| }; |
| }; |
| |
| omap_dwc3_2: omap_dwc3_2@488c0000 { |
| compatible = "ti,dwc3"; |
| ti,hwmods = "usb_otg_ss2"; |
| reg = <0x488c0000 0x10000>; |
| interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| utmi-mode = <2>; |
| ranges; |
| usb2: usb@488d0000 { |
| compatible = "snps,dwc3"; |
| reg = <0x488d0000 0x17000>; |
| interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; |
| phys = <&usb2_phy2>; |
| phy-names = "usb2-phy"; |
| tx-fifo-resize; |
| maximum-speed = "high-speed"; |
| dr_mode = "otg"; |
| }; |
| }; |
| |
| /* IRQ for DWC3_3 and DWC3_4 need IRQ crossbar */ |
| omap_dwc3_3: omap_dwc3_3@48900000 { |
| compatible = "ti,dwc3"; |
| ti,hwmods = "usb_otg_ss3"; |
| reg = <0x48900000 0x10000>; |
| interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| utmi-mode = <2>; |
| ranges; |
| status = "disabled"; |
| usb3: usb@48910000 { |
| compatible = "snps,dwc3"; |
| reg = <0x48910000 0x17000>; |
| interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; |
| tx-fifo-resize; |
| maximum-speed = "high-speed"; |
| dr_mode = "otg"; |
| }; |
| }; |
| |
| elm: elm@48078000 { |
| compatible = "ti,am3352-elm"; |
| reg = <0x48078000 0xfc0>; /* device IO registers */ |
| interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; |
| ti,hwmods = "elm"; |
| status = "disabled"; |
| }; |
| |
| gpmc: gpmc@50000000 { |
| compatible = "ti,am3352-gpmc"; |
| ti,hwmods = "gpmc"; |
| reg = <0x50000000 0x37c>; /* device IO registers */ |
| interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; |
| gpmc,num-cs = <8>; |
| gpmc,num-waitpins = <2>; |
| #address-cells = <2>; |
| #size-cells = <1>; |
| status = "disabled"; |
| }; |
| |
| atl: atl@4843c000 { |
| compatible = "ti,dra7-atl"; |
| reg = <0x4843c000 0x3ff>; |
| ti,hwmods = "atl"; |
| ti,provided-clocks = <&atl_clkin0_ck>, <&atl_clkin1_ck>, |
| <&atl_clkin2_ck>, <&atl_clkin3_ck>; |
| clocks = <&atl_gfclk_mux>; |
| clock-names = "fck"; |
| status = "disabled"; |
| }; |
| |
| crossbar_mpu: crossbar@4a020000 { |
| compatible = "ti,irq-crossbar"; |
| reg = <0x4a002a48 0x130>; |
| ti,max-irqs = <160>; |
| ti,max-crossbar-sources = <MAX_SOURCES>; |
| ti,reg-size = <2>; |
| ti,irqs-reserved = <0 1 2 3 5 6 131 132>; |
| ti,irqs-skip = <10 133 139 140>; |
| ti,irqs-safe-map = <0>; |
| }; |
| |
| mac: ethernet@4a100000 { |
| compatible = "ti,cpsw"; |
| ti,hwmods = "gmac"; |
| clocks = <&dpll_gmac_ck>, <&gmac_gmii_ref_clk_div>; |
| clock-names = "fck", "cpts"; |
| cpdma_channels = <8>; |
| ale_entries = <1024>; |
| bd_ram_size = <0x2000>; |
| no_bd_ram = <0>; |
| rx_descs = <64>; |
| mac_control = <0x20>; |
| slaves = <2>; |
| active_slave = <0>; |
| cpts_clock_mult = <0x80000000>; |
| cpts_clock_shift = <29>; |
| reg = <0x48484000 0x1000 |
| 0x48485200 0x2E00>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| /* |
| * rx_thresh_pend |
| * rx_pend |
| * tx_pend |
| * misc_pend |
| */ |
| interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>; |
| ranges; |
| status = "disabled"; |
| |
| davinci_mdio: mdio@48485000 { |
| compatible = "ti,davinci_mdio"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| ti,hwmods = "davinci_mdio"; |
| bus_freq = <1000000>; |
| reg = <0x48485000 0x100>; |
| }; |
| |
| cpsw_emac0: slave@48480200 { |
| /* Filled in by U-Boot */ |
| mac-address = [ 00 00 00 00 00 00 ]; |
| }; |
| |
| cpsw_emac1: slave@48480300 { |
| /* Filled in by U-Boot */ |
| mac-address = [ 00 00 00 00 00 00 ]; |
| }; |
| |
| phy_sel: cpsw-phy-sel@4a002554 { |
| compatible = "ti,dra7xx-cpsw-phy-sel"; |
| reg= <0x4a002554 0x4>; |
| reg-names = "gmii-sel"; |
| }; |
| }; |
| |
| dcan1: can@481cc000 { |
| compatible = "ti,dra7-d_can"; |
| ti,hwmods = "dcan1"; |
| reg = <0x4ae3c000 0x2000>; |
| syscon-raminit = <&dra7_ctrl_core 0x558 0>; |
| interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&dcan1_sys_clk_mux>; |
| status = "disabled"; |
| }; |
| |
| dcan2: can@481d0000 { |
| compatible = "ti,dra7-d_can"; |
| ti,hwmods = "dcan2"; |
| reg = <0x48480000 0x2000>; |
| syscon-raminit = <&dra7_ctrl_core 0x558 1>; |
| interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&sys_clkin1>; |
| status = "disabled"; |
| }; |
| }; |
| }; |
| |
| /include/ "dra7xx-clocks.dtsi" |