| /****************************************************************************** |
| * emulate.c |
| * |
| * Generic x86 (32-bit and 64-bit) instruction decoder and emulator. |
| * |
| * Copyright (c) 2005 Keir Fraser |
| * |
| * Linux coding style, mod r/m decoder, segment base fixes, real-mode |
| * privileged instructions: |
| * |
| * Copyright (C) 2006 Qumranet |
| * Copyright 2010 Red Hat, Inc. and/or its affiliates. |
| * |
| * Avi Kivity <avi@qumranet.com> |
| * Yaniv Kamay <yaniv@qumranet.com> |
| * |
| * This work is licensed under the terms of the GNU GPL, version 2. See |
| * the COPYING file in the top-level directory. |
| * |
| * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4 |
| */ |
| |
| #include <linux/kvm_host.h> |
| #include "kvm_cache_regs.h" |
| #include <linux/module.h> |
| #include <asm/kvm_emulate.h> |
| #include <linux/stringify.h> |
| |
| #include "x86.h" |
| #include "tss.h" |
| |
| /* |
| * Operand types |
| */ |
| #define OpNone 0ull |
| #define OpImplicit 1ull /* No generic decode */ |
| #define OpReg 2ull /* Register */ |
| #define OpMem 3ull /* Memory */ |
| #define OpAcc 4ull /* Accumulator: AL/AX/EAX/RAX */ |
| #define OpDI 5ull /* ES:DI/EDI/RDI */ |
| #define OpMem64 6ull /* Memory, 64-bit */ |
| #define OpImmUByte 7ull /* Zero-extended 8-bit immediate */ |
| #define OpDX 8ull /* DX register */ |
| #define OpCL 9ull /* CL register (for shifts) */ |
| #define OpImmByte 10ull /* 8-bit sign extended immediate */ |
| #define OpOne 11ull /* Implied 1 */ |
| #define OpImm 12ull /* Sign extended up to 32-bit immediate */ |
| #define OpMem16 13ull /* Memory operand (16-bit). */ |
| #define OpMem32 14ull /* Memory operand (32-bit). */ |
| #define OpImmU 15ull /* Immediate operand, zero extended */ |
| #define OpSI 16ull /* SI/ESI/RSI */ |
| #define OpImmFAddr 17ull /* Immediate far address */ |
| #define OpMemFAddr 18ull /* Far address in memory */ |
| #define OpImmU16 19ull /* Immediate operand, 16 bits, zero extended */ |
| #define OpES 20ull /* ES */ |
| #define OpCS 21ull /* CS */ |
| #define OpSS 22ull /* SS */ |
| #define OpDS 23ull /* DS */ |
| #define OpFS 24ull /* FS */ |
| #define OpGS 25ull /* GS */ |
| #define OpMem8 26ull /* 8-bit zero extended memory operand */ |
| #define OpImm64 27ull /* Sign extended 16/32/64-bit immediate */ |
| #define OpXLat 28ull /* memory at BX/EBX/RBX + zero-extended AL */ |
| #define OpAccLo 29ull /* Low part of extended acc (AX/AX/EAX/RAX) */ |
| #define OpAccHi 30ull /* High part of extended acc (-/DX/EDX/RDX) */ |
| |
| #define OpBits 5 /* Width of operand field */ |
| #define OpMask ((1ull << OpBits) - 1) |
| |
| /* |
| * Opcode effective-address decode tables. |
| * Note that we only emulate instructions that have at least one memory |
| * operand (excluding implicit stack references). We assume that stack |
| * references and instruction fetches will never occur in special memory |
| * areas that require emulation. So, for example, 'mov <imm>,<reg>' need |
| * not be handled. |
| */ |
| |
| /* Operand sizes: 8-bit operands or specified/overridden size. */ |
| #define ByteOp (1<<0) /* 8-bit operands. */ |
| /* Destination operand type. */ |
| #define DstShift 1 |
| #define ImplicitOps (OpImplicit << DstShift) |
| #define DstReg (OpReg << DstShift) |
| #define DstMem (OpMem << DstShift) |
| #define DstAcc (OpAcc << DstShift) |
| #define DstDI (OpDI << DstShift) |
| #define DstMem64 (OpMem64 << DstShift) |
| #define DstImmUByte (OpImmUByte << DstShift) |
| #define DstDX (OpDX << DstShift) |
| #define DstAccLo (OpAccLo << DstShift) |
| #define DstMask (OpMask << DstShift) |
| /* Source operand type. */ |
| #define SrcShift 6 |
| #define SrcNone (OpNone << SrcShift) |
| #define SrcReg (OpReg << SrcShift) |
| #define SrcMem (OpMem << SrcShift) |
| #define SrcMem16 (OpMem16 << SrcShift) |
| #define SrcMem32 (OpMem32 << SrcShift) |
| #define SrcImm (OpImm << SrcShift) |
| #define SrcImmByte (OpImmByte << SrcShift) |
| #define SrcOne (OpOne << SrcShift) |
| #define SrcImmUByte (OpImmUByte << SrcShift) |
| #define SrcImmU (OpImmU << SrcShift) |
| #define SrcSI (OpSI << SrcShift) |
| #define SrcXLat (OpXLat << SrcShift) |
| #define SrcImmFAddr (OpImmFAddr << SrcShift) |
| #define SrcMemFAddr (OpMemFAddr << SrcShift) |
| #define SrcAcc (OpAcc << SrcShift) |
| #define SrcImmU16 (OpImmU16 << SrcShift) |
| #define SrcImm64 (OpImm64 << SrcShift) |
| #define SrcDX (OpDX << SrcShift) |
| #define SrcMem8 (OpMem8 << SrcShift) |
| #define SrcAccHi (OpAccHi << SrcShift) |
| #define SrcMask (OpMask << SrcShift) |
| #define BitOp (1<<11) |
| #define MemAbs (1<<12) /* Memory operand is absolute displacement */ |
| #define String (1<<13) /* String instruction (rep capable) */ |
| #define Stack (1<<14) /* Stack instruction (push/pop) */ |
| #define GroupMask (7<<15) /* Opcode uses one of the group mechanisms */ |
| #define Group (1<<15) /* Bits 3:5 of modrm byte extend opcode */ |
| #define GroupDual (2<<15) /* Alternate decoding of mod == 3 */ |
| #define Prefix (3<<15) /* Instruction varies with 66/f2/f3 prefix */ |
| #define RMExt (4<<15) /* Opcode extension in ModRM r/m if mod == 3 */ |
| #define Escape (5<<15) /* Escape to coprocessor instruction */ |
| #define InstrDual (6<<15) /* Alternate instruction decoding of mod == 3 */ |
| #define Sse (1<<18) /* SSE Vector instruction */ |
| /* Generic ModRM decode. */ |
| #define ModRM (1<<19) |
| /* Destination is only written; never read. */ |
| #define Mov (1<<20) |
| /* Misc flags */ |
| #define Prot (1<<21) /* instruction generates #UD if not in prot-mode */ |
| #define EmulateOnUD (1<<22) /* Emulate if unsupported by the host */ |
| #define NoAccess (1<<23) /* Don't access memory (lea/invlpg/verr etc) */ |
| #define Op3264 (1<<24) /* Operand is 64b in long mode, 32b otherwise */ |
| #define Undefined (1<<25) /* No Such Instruction */ |
| #define Lock (1<<26) /* lock prefix is allowed for the instruction */ |
| #define Priv (1<<27) /* instruction generates #GP if current CPL != 0 */ |
| #define No64 (1<<28) |
| #define PageTable (1 << 29) /* instruction used to write page table */ |
| #define NotImpl (1 << 30) /* instruction is not implemented */ |
| /* Source 2 operand type */ |
| #define Src2Shift (31) |
| #define Src2None (OpNone << Src2Shift) |
| #define Src2Mem (OpMem << Src2Shift) |
| #define Src2CL (OpCL << Src2Shift) |
| #define Src2ImmByte (OpImmByte << Src2Shift) |
| #define Src2One (OpOne << Src2Shift) |
| #define Src2Imm (OpImm << Src2Shift) |
| #define Src2ES (OpES << Src2Shift) |
| #define Src2CS (OpCS << Src2Shift) |
| #define Src2SS (OpSS << Src2Shift) |
| #define Src2DS (OpDS << Src2Shift) |
| #define Src2FS (OpFS << Src2Shift) |
| #define Src2GS (OpGS << Src2Shift) |
| #define Src2Mask (OpMask << Src2Shift) |
| #define Mmx ((u64)1 << 40) /* MMX Vector instruction */ |
| #define Aligned ((u64)1 << 41) /* Explicitly aligned (e.g. MOVDQA) */ |
| #define Unaligned ((u64)1 << 42) /* Explicitly unaligned (e.g. MOVDQU) */ |
| #define Avx ((u64)1 << 43) /* Advanced Vector Extensions */ |
| #define Fastop ((u64)1 << 44) /* Use opcode::u.fastop */ |
| #define NoWrite ((u64)1 << 45) /* No writeback */ |
| #define SrcWrite ((u64)1 << 46) /* Write back src operand */ |
| #define NoMod ((u64)1 << 47) /* Mod field is ignored */ |
| #define Intercept ((u64)1 << 48) /* Has valid intercept field */ |
| #define CheckPerm ((u64)1 << 49) /* Has valid check_perm field */ |
| #define NoBigReal ((u64)1 << 50) /* No big real mode */ |
| #define PrivUD ((u64)1 << 51) /* #UD instead of #GP on CPL > 0 */ |
| #define NearBranch ((u64)1 << 52) /* Near branches */ |
| #define No16 ((u64)1 << 53) /* No 16 bit operand */ |
| |
| #define DstXacc (DstAccLo | SrcAccHi | SrcWrite) |
| |
| #define X2(x...) x, x |
| #define X3(x...) X2(x), x |
| #define X4(x...) X2(x), X2(x) |
| #define X5(x...) X4(x), x |
| #define X6(x...) X4(x), X2(x) |
| #define X7(x...) X4(x), X3(x) |
| #define X8(x...) X4(x), X4(x) |
| #define X16(x...) X8(x), X8(x) |
| |
| #define NR_FASTOP (ilog2(sizeof(ulong)) + 1) |
| #define FASTOP_SIZE 8 |
| |
| /* |
| * fastop functions have a special calling convention: |
| * |
| * dst: rax (in/out) |
| * src: rdx (in/out) |
| * src2: rcx (in) |
| * flags: rflags (in/out) |
| * ex: rsi (in:fastop pointer, out:zero if exception) |
| * |
| * Moreover, they are all exactly FASTOP_SIZE bytes long, so functions for |
| * different operand sizes can be reached by calculation, rather than a jump |
| * table (which would be bigger than the code). |
| * |
| * fastop functions are declared as taking a never-defined fastop parameter, |
| * so they can't be called from C directly. |
| */ |
| |
| struct fastop; |
| |
| struct opcode { |
| u64 flags : 56; |
| u64 intercept : 8; |
| union { |
| int (*execute)(struct x86_emulate_ctxt *ctxt); |
| const struct opcode *group; |
| const struct group_dual *gdual; |
| const struct gprefix *gprefix; |
| const struct escape *esc; |
| const struct instr_dual *idual; |
| void (*fastop)(struct fastop *fake); |
| } u; |
| int (*check_perm)(struct x86_emulate_ctxt *ctxt); |
| }; |
| |
| struct group_dual { |
| struct opcode mod012[8]; |
| struct opcode mod3[8]; |
| }; |
| |
| struct gprefix { |
| struct opcode pfx_no; |
| struct opcode pfx_66; |
| struct opcode pfx_f2; |
| struct opcode pfx_f3; |
| }; |
| |
| struct escape { |
| struct opcode op[8]; |
| struct opcode high[64]; |
| }; |
| |
| struct instr_dual { |
| struct opcode mod012; |
| struct opcode mod3; |
| }; |
| |
| /* EFLAGS bit definitions. */ |
| #define EFLG_ID (1<<21) |
| #define EFLG_VIP (1<<20) |
| #define EFLG_VIF (1<<19) |
| #define EFLG_AC (1<<18) |
| #define EFLG_VM (1<<17) |
| #define EFLG_RF (1<<16) |
| #define EFLG_IOPL (3<<12) |
| #define EFLG_NT (1<<14) |
| #define EFLG_OF (1<<11) |
| #define EFLG_DF (1<<10) |
| #define EFLG_IF (1<<9) |
| #define EFLG_TF (1<<8) |
| #define EFLG_SF (1<<7) |
| #define EFLG_ZF (1<<6) |
| #define EFLG_AF (1<<4) |
| #define EFLG_PF (1<<2) |
| #define EFLG_CF (1<<0) |
| |
| #define EFLG_RESERVED_ZEROS_MASK 0xffc0802a |
| #define EFLG_RESERVED_ONE_MASK 2 |
| |
| static ulong reg_read(struct x86_emulate_ctxt *ctxt, unsigned nr) |
| { |
| if (!(ctxt->regs_valid & (1 << nr))) { |
| ctxt->regs_valid |= 1 << nr; |
| ctxt->_regs[nr] = ctxt->ops->read_gpr(ctxt, nr); |
| } |
| return ctxt->_regs[nr]; |
| } |
| |
| static ulong *reg_write(struct x86_emulate_ctxt *ctxt, unsigned nr) |
| { |
| ctxt->regs_valid |= 1 << nr; |
| ctxt->regs_dirty |= 1 << nr; |
| return &ctxt->_regs[nr]; |
| } |
| |
| static ulong *reg_rmw(struct x86_emulate_ctxt *ctxt, unsigned nr) |
| { |
| reg_read(ctxt, nr); |
| return reg_write(ctxt, nr); |
| } |
| |
| static void writeback_registers(struct x86_emulate_ctxt *ctxt) |
| { |
| unsigned reg; |
| |
| for_each_set_bit(reg, (ulong *)&ctxt->regs_dirty, 16) |
| ctxt->ops->write_gpr(ctxt, reg, ctxt->_regs[reg]); |
| } |
| |
| static void invalidate_registers(struct x86_emulate_ctxt *ctxt) |
| { |
| ctxt->regs_dirty = 0; |
| ctxt->regs_valid = 0; |
| } |
| |
| /* |
| * These EFLAGS bits are restored from saved value during emulation, and |
| * any changes are written back to the saved value after emulation. |
| */ |
| #define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF) |
| |
| #ifdef CONFIG_X86_64 |
| #define ON64(x) x |
| #else |
| #define ON64(x) |
| #endif |
| |
| static int fastop(struct x86_emulate_ctxt *ctxt, void (*fop)(struct fastop *)); |
| |
| #define FOP_ALIGN ".align " __stringify(FASTOP_SIZE) " \n\t" |
| #define FOP_RET "ret \n\t" |
| |
| #define FOP_START(op) \ |
| extern void em_##op(struct fastop *fake); \ |
| asm(".pushsection .text, \"ax\" \n\t" \ |
| ".global em_" #op " \n\t" \ |
| FOP_ALIGN \ |
| "em_" #op ": \n\t" |
| |
| #define FOP_END \ |
| ".popsection") |
| |
| #define FOPNOP() FOP_ALIGN FOP_RET |
| |
| #define FOP1E(op, dst) \ |
| FOP_ALIGN "10: " #op " %" #dst " \n\t" FOP_RET |
| |
| #define FOP1EEX(op, dst) \ |
| FOP1E(op, dst) _ASM_EXTABLE(10b, kvm_fastop_exception) |
| |
| #define FASTOP1(op) \ |
| FOP_START(op) \ |
| FOP1E(op##b, al) \ |
| FOP1E(op##w, ax) \ |
| FOP1E(op##l, eax) \ |
| ON64(FOP1E(op##q, rax)) \ |
| FOP_END |
| |
| /* 1-operand, using src2 (for MUL/DIV r/m) */ |
| #define FASTOP1SRC2(op, name) \ |
| FOP_START(name) \ |
| FOP1E(op, cl) \ |
| FOP1E(op, cx) \ |
| FOP1E(op, ecx) \ |
| ON64(FOP1E(op, rcx)) \ |
| FOP_END |
| |
| /* 1-operand, using src2 (for MUL/DIV r/m), with exceptions */ |
| #define FASTOP1SRC2EX(op, name) \ |
| FOP_START(name) \ |
| FOP1EEX(op, cl) \ |
| FOP1EEX(op, cx) \ |
| FOP1EEX(op, ecx) \ |
| ON64(FOP1EEX(op, rcx)) \ |
| FOP_END |
| |
| #define FOP2E(op, dst, src) \ |
| FOP_ALIGN #op " %" #src ", %" #dst " \n\t" FOP_RET |
| |
| #define FASTOP2(op) \ |
| FOP_START(op) \ |
| FOP2E(op##b, al, dl) \ |
| FOP2E(op##w, ax, dx) \ |
| FOP2E(op##l, eax, edx) \ |
| ON64(FOP2E(op##q, rax, rdx)) \ |
| FOP_END |
| |
| /* 2 operand, word only */ |
| #define FASTOP2W(op) \ |
| FOP_START(op) \ |
| FOPNOP() \ |
| FOP2E(op##w, ax, dx) \ |
| FOP2E(op##l, eax, edx) \ |
| ON64(FOP2E(op##q, rax, rdx)) \ |
| FOP_END |
| |
| /* 2 operand, src is CL */ |
| #define FASTOP2CL(op) \ |
| FOP_START(op) \ |
| FOP2E(op##b, al, cl) \ |
| FOP2E(op##w, ax, cl) \ |
| FOP2E(op##l, eax, cl) \ |
| ON64(FOP2E(op##q, rax, cl)) \ |
| FOP_END |
| |
| /* 2 operand, src and dest are reversed */ |
| #define FASTOP2R(op, name) \ |
| FOP_START(name) \ |
| FOP2E(op##b, dl, al) \ |
| FOP2E(op##w, dx, ax) \ |
| FOP2E(op##l, edx, eax) \ |
| ON64(FOP2E(op##q, rdx, rax)) \ |
| FOP_END |
| |
| #define FOP3E(op, dst, src, src2) \ |
| FOP_ALIGN #op " %" #src2 ", %" #src ", %" #dst " \n\t" FOP_RET |
| |
| /* 3-operand, word-only, src2=cl */ |
| #define FASTOP3WCL(op) \ |
| FOP_START(op) \ |
| FOPNOP() \ |
| FOP3E(op##w, ax, dx, cl) \ |
| FOP3E(op##l, eax, edx, cl) \ |
| ON64(FOP3E(op##q, rax, rdx, cl)) \ |
| FOP_END |
| |
| /* Special case for SETcc - 1 instruction per cc */ |
| #define FOP_SETCC(op) ".align 4; " #op " %al; ret \n\t" |
| |
| asm(".global kvm_fastop_exception \n" |
| "kvm_fastop_exception: xor %esi, %esi; ret"); |
| |
| FOP_START(setcc) |
| FOP_SETCC(seto) |
| FOP_SETCC(setno) |
| FOP_SETCC(setc) |
| FOP_SETCC(setnc) |
| FOP_SETCC(setz) |
| FOP_SETCC(setnz) |
| FOP_SETCC(setbe) |
| FOP_SETCC(setnbe) |
| FOP_SETCC(sets) |
| FOP_SETCC(setns) |
| FOP_SETCC(setp) |
| FOP_SETCC(setnp) |
| FOP_SETCC(setl) |
| FOP_SETCC(setnl) |
| FOP_SETCC(setle) |
| FOP_SETCC(setnle) |
| FOP_END; |
| |
| FOP_START(salc) "pushf; sbb %al, %al; popf \n\t" FOP_RET |
| FOP_END; |
| |
| static int emulator_check_intercept(struct x86_emulate_ctxt *ctxt, |
| enum x86_intercept intercept, |
| enum x86_intercept_stage stage) |
| { |
| struct x86_instruction_info info = { |
| .intercept = intercept, |
| .rep_prefix = ctxt->rep_prefix, |
| .modrm_mod = ctxt->modrm_mod, |
| .modrm_reg = ctxt->modrm_reg, |
| .modrm_rm = ctxt->modrm_rm, |
| .src_val = ctxt->src.val64, |
| .dst_val = ctxt->dst.val64, |
| .src_bytes = ctxt->src.bytes, |
| .dst_bytes = ctxt->dst.bytes, |
| .ad_bytes = ctxt->ad_bytes, |
| .next_rip = ctxt->eip, |
| }; |
| |
| return ctxt->ops->intercept(ctxt, &info, stage); |
| } |
| |
| static void assign_masked(ulong *dest, ulong src, ulong mask) |
| { |
| *dest = (*dest & ~mask) | (src & mask); |
| } |
| |
| static inline unsigned long ad_mask(struct x86_emulate_ctxt *ctxt) |
| { |
| return (1UL << (ctxt->ad_bytes << 3)) - 1; |
| } |
| |
| static ulong stack_mask(struct x86_emulate_ctxt *ctxt) |
| { |
| u16 sel; |
| struct desc_struct ss; |
| |
| if (ctxt->mode == X86EMUL_MODE_PROT64) |
| return ~0UL; |
| ctxt->ops->get_segment(ctxt, &sel, &ss, NULL, VCPU_SREG_SS); |
| return ~0U >> ((ss.d ^ 1) * 16); /* d=0: 0xffff; d=1: 0xffffffff */ |
| } |
| |
| static int stack_size(struct x86_emulate_ctxt *ctxt) |
| { |
| return (__fls(stack_mask(ctxt)) + 1) >> 3; |
| } |
| |
| /* Access/update address held in a register, based on addressing mode. */ |
| static inline unsigned long |
| address_mask(struct x86_emulate_ctxt *ctxt, unsigned long reg) |
| { |
| if (ctxt->ad_bytes == sizeof(unsigned long)) |
| return reg; |
| else |
| return reg & ad_mask(ctxt); |
| } |
| |
| static inline unsigned long |
| register_address(struct x86_emulate_ctxt *ctxt, int reg) |
| { |
| return address_mask(ctxt, reg_read(ctxt, reg)); |
| } |
| |
| static void masked_increment(ulong *reg, ulong mask, int inc) |
| { |
| assign_masked(reg, *reg + inc, mask); |
| } |
| |
| static inline void |
| register_address_increment(struct x86_emulate_ctxt *ctxt, int reg, int inc) |
| { |
| ulong mask; |
| |
| if (ctxt->ad_bytes == sizeof(unsigned long)) |
| mask = ~0UL; |
| else |
| mask = ad_mask(ctxt); |
| masked_increment(reg_rmw(ctxt, reg), mask, inc); |
| } |
| |
| static void rsp_increment(struct x86_emulate_ctxt *ctxt, int inc) |
| { |
| masked_increment(reg_rmw(ctxt, VCPU_REGS_RSP), stack_mask(ctxt), inc); |
| } |
| |
| static u32 desc_limit_scaled(struct desc_struct *desc) |
| { |
| u32 limit = get_desc_limit(desc); |
| |
| return desc->g ? (limit << 12) | 0xfff : limit; |
| } |
| |
| static unsigned long seg_base(struct x86_emulate_ctxt *ctxt, int seg) |
| { |
| if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS) |
| return 0; |
| |
| return ctxt->ops->get_cached_segment_base(ctxt, seg); |
| } |
| |
| static int emulate_exception(struct x86_emulate_ctxt *ctxt, int vec, |
| u32 error, bool valid) |
| { |
| WARN_ON(vec > 0x1f); |
| ctxt->exception.vector = vec; |
| ctxt->exception.error_code = error; |
| ctxt->exception.error_code_valid = valid; |
| return X86EMUL_PROPAGATE_FAULT; |
| } |
| |
| static int emulate_db(struct x86_emulate_ctxt *ctxt) |
| { |
| return emulate_exception(ctxt, DB_VECTOR, 0, false); |
| } |
| |
| static int emulate_gp(struct x86_emulate_ctxt *ctxt, int err) |
| { |
| return emulate_exception(ctxt, GP_VECTOR, err, true); |
| } |
| |
| static int emulate_ss(struct x86_emulate_ctxt *ctxt, int err) |
| { |
| return emulate_exception(ctxt, SS_VECTOR, err, true); |
| } |
| |
| static int emulate_ud(struct x86_emulate_ctxt *ctxt) |
| { |
| return emulate_exception(ctxt, UD_VECTOR, 0, false); |
| } |
| |
| static int emulate_ts(struct x86_emulate_ctxt *ctxt, int err) |
| { |
| return emulate_exception(ctxt, TS_VECTOR, err, true); |
| } |
| |
| static int emulate_de(struct x86_emulate_ctxt *ctxt) |
| { |
| return emulate_exception(ctxt, DE_VECTOR, 0, false); |
| } |
| |
| static int emulate_nm(struct x86_emulate_ctxt *ctxt) |
| { |
| return emulate_exception(ctxt, NM_VECTOR, 0, false); |
| } |
| |
| static u16 get_segment_selector(struct x86_emulate_ctxt *ctxt, unsigned seg) |
| { |
| u16 selector; |
| struct desc_struct desc; |
| |
| ctxt->ops->get_segment(ctxt, &selector, &desc, NULL, seg); |
| return selector; |
| } |
| |
| static void set_segment_selector(struct x86_emulate_ctxt *ctxt, u16 selector, |
| unsigned seg) |
| { |
| u16 dummy; |
| u32 base3; |
| struct desc_struct desc; |
| |
| ctxt->ops->get_segment(ctxt, &dummy, &desc, &base3, seg); |
| ctxt->ops->set_segment(ctxt, selector, &desc, base3, seg); |
| } |
| |
| /* |
| * x86 defines three classes of vector instructions: explicitly |
| * aligned, explicitly unaligned, and the rest, which change behaviour |
| * depending on whether they're AVX encoded or not. |
| * |
| * Also included is CMPXCHG16B which is not a vector instruction, yet it is |
| * subject to the same check. |
| */ |
| static bool insn_aligned(struct x86_emulate_ctxt *ctxt, unsigned size) |
| { |
| if (likely(size < 16)) |
| return false; |
| |
| if (ctxt->d & Aligned) |
| return true; |
| else if (ctxt->d & Unaligned) |
| return false; |
| else if (ctxt->d & Avx) |
| return false; |
| else |
| return true; |
| } |
| |
| static __always_inline int __linearize(struct x86_emulate_ctxt *ctxt, |
| struct segmented_address addr, |
| unsigned *max_size, unsigned size, |
| bool write, bool fetch, |
| enum x86emul_mode mode, ulong *linear) |
| { |
| struct desc_struct desc; |
| bool usable; |
| ulong la; |
| u32 lim; |
| u16 sel; |
| |
| la = seg_base(ctxt, addr.seg) + addr.ea; |
| *max_size = 0; |
| switch (mode) { |
| case X86EMUL_MODE_PROT64: |
| if (is_noncanonical_address(la)) |
| goto bad; |
| |
| *max_size = min_t(u64, ~0u, (1ull << 48) - la); |
| if (size > *max_size) |
| goto bad; |
| break; |
| default: |
| usable = ctxt->ops->get_segment(ctxt, &sel, &desc, NULL, |
| addr.seg); |
| if (!usable) |
| goto bad; |
| /* code segment in protected mode or read-only data segment */ |
| if ((((ctxt->mode != X86EMUL_MODE_REAL) && (desc.type & 8)) |
| || !(desc.type & 2)) && write) |
| goto bad; |
| /* unreadable code segment */ |
| if (!fetch && (desc.type & 8) && !(desc.type & 2)) |
| goto bad; |
| lim = desc_limit_scaled(&desc); |
| if (!(desc.type & 8) && (desc.type & 4)) { |
| /* expand-down segment */ |
| if (addr.ea <= lim) |
| goto bad; |
| lim = desc.d ? 0xffffffff : 0xffff; |
| } |
| if (addr.ea > lim) |
| goto bad; |
| *max_size = min_t(u64, ~0u, (u64)lim + 1 - addr.ea); |
| if (size > *max_size) |
| goto bad; |
| la &= (u32)-1; |
| break; |
| } |
| if (insn_aligned(ctxt, size) && ((la & (size - 1)) != 0)) |
| return emulate_gp(ctxt, 0); |
| *linear = la; |
| return X86EMUL_CONTINUE; |
| bad: |
| if (addr.seg == VCPU_SREG_SS) |
| return emulate_ss(ctxt, 0); |
| else |
| return emulate_gp(ctxt, 0); |
| } |
| |
| static int linearize(struct x86_emulate_ctxt *ctxt, |
| struct segmented_address addr, |
| unsigned size, bool write, |
| ulong *linear) |
| { |
| unsigned max_size; |
| return __linearize(ctxt, addr, &max_size, size, write, false, |
| ctxt->mode, linear); |
| } |
| |
| static inline int assign_eip(struct x86_emulate_ctxt *ctxt, ulong dst, |
| enum x86emul_mode mode) |
| { |
| ulong linear; |
| int rc; |
| unsigned max_size; |
| struct segmented_address addr = { .seg = VCPU_SREG_CS, |
| .ea = dst }; |
| |
| if (ctxt->op_bytes != sizeof(unsigned long)) |
| addr.ea = dst & ((1UL << (ctxt->op_bytes << 3)) - 1); |
| rc = __linearize(ctxt, addr, &max_size, 1, false, true, mode, &linear); |
| if (rc == X86EMUL_CONTINUE) |
| ctxt->_eip = addr.ea; |
| return rc; |
| } |
| |
| static inline int assign_eip_near(struct x86_emulate_ctxt *ctxt, ulong dst) |
| { |
| return assign_eip(ctxt, dst, ctxt->mode); |
| } |
| |
| static int assign_eip_far(struct x86_emulate_ctxt *ctxt, ulong dst, |
| const struct desc_struct *cs_desc) |
| { |
| enum x86emul_mode mode = ctxt->mode; |
| |
| #ifdef CONFIG_X86_64 |
| if (ctxt->mode >= X86EMUL_MODE_PROT32 && cs_desc->l) { |
| u64 efer = 0; |
| |
| ctxt->ops->get_msr(ctxt, MSR_EFER, &efer); |
| if (efer & EFER_LMA) |
| mode = X86EMUL_MODE_PROT64; |
| } |
| #endif |
| if (mode == X86EMUL_MODE_PROT16 || mode == X86EMUL_MODE_PROT32) |
| mode = cs_desc->d ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16; |
| return assign_eip(ctxt, dst, mode); |
| } |
| |
| static inline int jmp_rel(struct x86_emulate_ctxt *ctxt, int rel) |
| { |
| return assign_eip_near(ctxt, ctxt->_eip + rel); |
| } |
| |
| static int segmented_read_std(struct x86_emulate_ctxt *ctxt, |
| struct segmented_address addr, |
| void *data, |
| unsigned size) |
| { |
| int rc; |
| ulong linear; |
| |
| rc = linearize(ctxt, addr, size, false, &linear); |
| if (rc != X86EMUL_CONTINUE) |
| return rc; |
| return ctxt->ops->read_std(ctxt, linear, data, size, &ctxt->exception); |
| } |
| |
| /* |
| * Prefetch the remaining bytes of the instruction without crossing page |
| * boundary if they are not in fetch_cache yet. |
| */ |
| static int __do_insn_fetch_bytes(struct x86_emulate_ctxt *ctxt, int op_size) |
| { |
| int rc; |
| unsigned size, max_size; |
| unsigned long linear; |
| int cur_size = ctxt->fetch.end - ctxt->fetch.data; |
| struct segmented_address addr = { .seg = VCPU_SREG_CS, |
| .ea = ctxt->eip + cur_size }; |
| |
| /* |
| * We do not know exactly how many bytes will be needed, and |
| * __linearize is expensive, so fetch as much as possible. We |
| * just have to avoid going beyond the 15 byte limit, the end |
| * of the segment, or the end of the page. |
| * |
| * __linearize is called with size 0 so that it does not do any |
| * boundary check itself. Instead, we use max_size to check |
| * against op_size. |
| */ |
| rc = __linearize(ctxt, addr, &max_size, 0, false, true, ctxt->mode, |
| &linear); |
| if (unlikely(rc != X86EMUL_CONTINUE)) |
| return rc; |
| |
| size = min_t(unsigned, 15UL ^ cur_size, max_size); |
| size = min_t(unsigned, size, PAGE_SIZE - offset_in_page(linear)); |
| |
| /* |
| * One instruction can only straddle two pages, |
| * and one has been loaded at the beginning of |
| * x86_decode_insn. So, if not enough bytes |
| * still, we must have hit the 15-byte boundary. |
| */ |
| if (unlikely(size < op_size)) |
| return emulate_gp(ctxt, 0); |
| |
| rc = ctxt->ops->fetch(ctxt, linear, ctxt->fetch.end, |
| size, &ctxt->exception); |
| if (unlikely(rc != X86EMUL_CONTINUE)) |
| return rc; |
| ctxt->fetch.end += size; |
| return X86EMUL_CONTINUE; |
| } |
| |
| static __always_inline int do_insn_fetch_bytes(struct x86_emulate_ctxt *ctxt, |
| unsigned size) |
| { |
| unsigned done_size = ctxt->fetch.end - ctxt->fetch.ptr; |
| |
| if (unlikely(done_size < size)) |
| return __do_insn_fetch_bytes(ctxt, size - done_size); |
| else |
| return X86EMUL_CONTINUE; |
| } |
| |
| /* Fetch next part of the instruction being emulated. */ |
| #define insn_fetch(_type, _ctxt) \ |
| ({ _type _x; \ |
| \ |
| rc = do_insn_fetch_bytes(_ctxt, sizeof(_type)); \ |
| if (rc != X86EMUL_CONTINUE) \ |
| goto done; \ |
| ctxt->_eip += sizeof(_type); \ |
| _x = *(_type __aligned(1) *) ctxt->fetch.ptr; \ |
| ctxt->fetch.ptr += sizeof(_type); \ |
| _x; \ |
| }) |
| |
| #define insn_fetch_arr(_arr, _size, _ctxt) \ |
| ({ \ |
| rc = do_insn_fetch_bytes(_ctxt, _size); \ |
| if (rc != X86EMUL_CONTINUE) \ |
| goto done; \ |
| ctxt->_eip += (_size); \ |
| memcpy(_arr, ctxt->fetch.ptr, _size); \ |
| ctxt->fetch.ptr += (_size); \ |
| }) |
| |
| /* |
| * Given the 'reg' portion of a ModRM byte, and a register block, return a |
| * pointer into the block that addresses the relevant register. |
| * @highbyte_regs specifies whether to decode AH,CH,DH,BH. |
| */ |
| static void *decode_register(struct x86_emulate_ctxt *ctxt, u8 modrm_reg, |
| int byteop) |
| { |
| void *p; |
| int highbyte_regs = (ctxt->rex_prefix == 0) && byteop; |
| |
| if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8) |
| p = (unsigned char *)reg_rmw(ctxt, modrm_reg & 3) + 1; |
| else |
| p = reg_rmw(ctxt, modrm_reg); |
| return p; |
| } |
| |
| static int read_descriptor(struct x86_emulate_ctxt *ctxt, |
| struct segmented_address addr, |
| u16 *size, unsigned long *address, int op_bytes) |
| { |
| int rc; |
| |
| if (op_bytes == 2) |
| op_bytes = 3; |
| *address = 0; |
| rc = segmented_read_std(ctxt, addr, size, 2); |
| if (rc != X86EMUL_CONTINUE) |
| return rc; |
| addr.ea += 2; |
| rc = segmented_read_std(ctxt, addr, address, op_bytes); |
| return rc; |
| } |
| |
| FASTOP2(add); |
| FASTOP2(or); |
| FASTOP2(adc); |
| FASTOP2(sbb); |
| FASTOP2(and); |
| FASTOP2(sub); |
| FASTOP2(xor); |
| FASTOP2(cmp); |
| FASTOP2(test); |
| |
| FASTOP1SRC2(mul, mul_ex); |
| FASTOP1SRC2(imul, imul_ex); |
| FASTOP1SRC2EX(div, div_ex); |
| FASTOP1SRC2EX(idiv, idiv_ex); |
| |
| FASTOP3WCL(shld); |
| FASTOP3WCL(shrd); |
| |
| FASTOP2W(imul); |
| |
| FASTOP1(not); |
| FASTOP1(neg); |
| FASTOP1(inc); |
| FASTOP1(dec); |
| |
| FASTOP2CL(rol); |
| FASTOP2CL(ror); |
| FASTOP2CL(rcl); |
| FASTOP2CL(rcr); |
| FASTOP2CL(shl); |
| FASTOP2CL(shr); |
| FASTOP2CL(sar); |
| |
| FASTOP2W(bsf); |
| FASTOP2W(bsr); |
| FASTOP2W(bt); |
| FASTOP2W(bts); |
| FASTOP2W(btr); |
| FASTOP2W(btc); |
| |
| FASTOP2(xadd); |
| |
| FASTOP2R(cmp, cmp_r); |
| |
| static u8 test_cc(unsigned int condition, unsigned long flags) |
| { |
| u8 rc; |
| void (*fop)(void) = (void *)em_setcc + 4 * (condition & 0xf); |
| |
| flags = (flags & EFLAGS_MASK) | X86_EFLAGS_IF; |
| asm("push %[flags]; popf; call *%[fastop]" |
| : "=a"(rc) : [fastop]"r"(fop), [flags]"r"(flags)); |
| return rc; |
| } |
| |
| static void fetch_register_operand(struct operand *op) |
| { |
| switch (op->bytes) { |
| case 1: |
| op->val = *(u8 *)op->addr.reg; |
| break; |
| case 2: |
| op->val = *(u16 *)op->addr.reg; |
| break; |
| case 4: |
| op->val = *(u32 *)op->addr.reg; |
| break; |
| case 8: |
| op->val = *(u64 *)op->addr.reg; |
| break; |
| } |
| } |
| |
| static void read_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data, int reg) |
| { |
| ctxt->ops->get_fpu(ctxt); |
| switch (reg) { |
| case 0: asm("movdqa %%xmm0, %0" : "=m"(*data)); break; |
| case 1: asm("movdqa %%xmm1, %0" : "=m"(*data)); break; |
| case 2: asm("movdqa %%xmm2, %0" : "=m"(*data)); break; |
| case 3: asm("movdqa %%xmm3, %0" : "=m"(*data)); break; |
| case 4: asm("movdqa %%xmm4, %0" : "=m"(*data)); break; |
| case 5: asm("movdqa %%xmm5, %0" : "=m"(*data)); break; |
| case 6: asm("movdqa %%xmm6, %0" : "=m"(*data)); break; |
| case 7: asm("movdqa %%xmm7, %0" : "=m"(*data)); break; |
| #ifdef CONFIG_X86_64 |
| case 8: asm("movdqa %%xmm8, %0" : "=m"(*data)); break; |
| case 9: asm("movdqa %%xmm9, %0" : "=m"(*data)); break; |
| case 10: asm("movdqa %%xmm10, %0" : "=m"(*data)); break; |
| case 11: asm("movdqa %%xmm11, %0" : "=m"(*data)); break; |
| case 12: asm("movdqa %%xmm12, %0" : "=m"(*data)); break; |
| case 13: asm("movdqa %%xmm13, %0" : "=m"(*data)); break; |
| case 14: asm("movdqa %%xmm14, %0" : "=m"(*data)); break; |
| case 15: asm("movdqa %%xmm15, %0" : "=m"(*data)); break; |
| #endif |
| default: BUG(); |
| } |
| ctxt->ops->put_fpu(ctxt); |
| } |
| |
| static void write_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data, |
| int reg) |
| { |
| ctxt->ops->get_fpu(ctxt); |
| switch (reg) { |
| case 0: asm("movdqa %0, %%xmm0" : : "m"(*data)); break; |
| case 1: asm("movdqa %0, %%xmm1" : : "m"(*data)); break; |
| case 2: asm("movdqa %0, %%xmm2" : : "m"(*data)); break; |
| case 3: asm("movdqa %0, %%xmm3" : : "m"(*data)); break; |
| case 4: asm("movdqa %0, %%xmm4" : : "m"(*data)); break; |
| case 5: asm("movdqa %0, %%xmm5" : : "m"(*data)); break; |
| case 6: asm("movdqa %0, %%xmm6" : : "m"(*data)); break; |
| case 7: asm("movdqa %0, %%xmm7" : : "m"(*data)); break; |
| #ifdef CONFIG_X86_64 |
| case 8: asm("movdqa %0, %%xmm8" : : "m"(*data)); break; |
| case 9: asm("movdqa %0, %%xmm9" : : "m"(*data)); break; |
| case 10: asm("movdqa %0, %%xmm10" : : "m"(*data)); break; |
| case 11: asm("movdqa %0, %%xmm11" : : "m"(*data)); break; |
| case 12: asm("movdqa %0, %%xmm12" : : "m"(*data)); break; |
| case 13: asm("movdqa %0, %%xmm13" : : "m"(*data)); break; |
| case 14: asm("movdqa %0, %%xmm14" : : "m"(*data)); break; |
| case 15: asm("movdqa %0, %%xmm15" : : "m"(*data)); break; |
| #endif |
| default: BUG(); |
| } |
| ctxt->ops->put_fpu(ctxt); |
| } |
| |
| static void read_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg) |
| { |
| ctxt->ops->get_fpu(ctxt); |
| switch (reg) { |
| case 0: asm("movq %%mm0, %0" : "=m"(*data)); break; |
| case 1: asm("movq %%mm1, %0" : "=m"(*data)); break; |
| case 2: asm("movq %%mm2, %0" : "=m"(*data)); break; |
| case 3: asm("movq %%mm3, %0" : "=m"(*data)); break; |
| case 4: asm("movq %%mm4, %0" : "=m"(*data)); break; |
| case 5: asm("movq %%mm5, %0" : "=m"(*data)); break; |
| case 6: asm("movq %%mm6, %0" : "=m"(*data)); break; |
| case 7: asm("movq %%mm7, %0" : "=m"(*data)); break; |
| default: BUG(); |
| } |
| ctxt->ops->put_fpu(ctxt); |
| } |
| |
| static void write_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg) |
| { |
| ctxt->ops->get_fpu(ctxt); |
| switch (reg) { |
| case 0: asm("movq %0, %%mm0" : : "m"(*data)); break; |
| case 1: asm("movq %0, %%mm1" : : "m"(*data)); break; |
| case 2: asm("movq %0, %%mm2" : : "m"(*data)); break; |
| case 3: asm("movq %0, %%mm3" : : "m"(*data)); break; |
| case 4: asm("movq %0, %%mm4" : : "m"(*data)); break; |
| case 5: asm("movq %0, %%mm5" : : "m"(*data)); break; |
| case 6: asm("movq %0, %%mm6" : : "m"(*data)); break; |
| case 7: asm("movq %0, %%mm7" : : "m"(*data)); break; |
| default: BUG(); |
| } |
| ctxt->ops->put_fpu(ctxt); |
| } |
| |
| static int em_fninit(struct x86_emulate_ctxt *ctxt) |
| { |
| if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM)) |
| return emulate_nm(ctxt); |
| |
| ctxt->ops->get_fpu(ctxt); |
| asm volatile("fninit"); |
| ctxt->ops->put_fpu(ctxt); |
| return X86EMUL_CONTINUE; |
| } |
| |
| static int em_fnstcw(struct x86_emulate_ctxt *ctxt) |
| { |
| u16 fcw; |
| |
| if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM)) |
| return emulate_nm(ctxt); |
| |
| ctxt->ops->get_fpu(ctxt); |
| asm volatile("fnstcw %0": "+m"(fcw)); |
| ctxt->ops->put_fpu(ctxt); |
| |
| /* force 2 byte destination */ |
| ctxt->dst.bytes = 2; |
| ctxt->dst.val = fcw; |
| |
| return X86EMUL_CONTINUE; |
| } |
| |
| static int em_fnstsw(struct x86_emulate_ctxt *ctxt) |
| { |
| u16 fsw; |
| |
| if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM)) |
| return emulate_nm(ctxt); |
| |
| ctxt->ops->get_fpu(ctxt); |
| asm volatile("fnstsw %0": "+m"(fsw)); |
| ctxt->ops->put_fpu(ctxt); |
| |
| /* force 2 byte destination */ |
| ctxt->dst.bytes = 2; |
| ctxt->dst.val = fsw; |
| |
| return X86EMUL_CONTINUE; |
| } |
| |
| static void decode_register_operand(struct x86_emulate_ctxt *ctxt, |
| struct operand *op) |
| { |
| unsigned reg = ctxt->modrm_reg; |
| |
| if (!(ctxt->d & ModRM)) |
| reg = (ctxt->b & 7) | ((ctxt->rex_prefix & 1) << 3); |
| |
| if (ctxt->d & Sse) { |
| op->type = OP_XMM; |
| op->bytes = 16; |
| op->addr.xmm = reg; |
| read_sse_reg(ctxt, &op->vec_val, reg); |
| return; |
| } |
| if (ctxt->d & Mmx) { |
| reg &= 7; |
| op->type = OP_MM; |
| op->bytes = 8; |
| op->addr.mm = reg; |
| return; |
| } |
| |
| op->type = OP_REG; |
| op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes; |
| op->addr.reg = decode_register(ctxt, reg, ctxt->d & ByteOp); |
| |
| fetch_register_operand(op); |
| op->orig_val = op->val; |
| } |
| |
| static void adjust_modrm_seg(struct x86_emulate_ctxt *ctxt, int base_reg) |
| { |
| if (base_reg == VCPU_REGS_RSP || base_reg == VCPU_REGS_RBP) |
| ctxt->modrm_seg = VCPU_SREG_SS; |
| } |
| |
| static int decode_modrm(struct x86_emulate_ctxt *ctxt, |
| struct operand *op) |
| { |
| u8 sib; |
| int index_reg, base_reg, scale; |
| int rc = X86EMUL_CONTINUE; |
| ulong modrm_ea = 0; |
| |
| ctxt->modrm_reg = ((ctxt->rex_prefix << 1) & 8); /* REX.R */ |
| index_reg = (ctxt->rex_prefix << 2) & 8; /* REX.X */ |
| base_reg = (ctxt->rex_prefix << 3) & 8; /* REX.B */ |
| |
| ctxt->modrm_mod = (ctxt->modrm & 0xc0) >> 6; |
| ctxt->modrm_reg |= (ctxt->modrm & 0x38) >> 3; |
| ctxt->modrm_rm = base_reg | (ctxt->modrm & 0x07); |
| ctxt->modrm_seg = VCPU_SREG_DS; |
| |
| if (ctxt->modrm_mod == 3 || (ctxt->d & NoMod)) { |
| op->type = OP_REG; |
| op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes; |
| op->addr.reg = decode_register(ctxt, ctxt->modrm_rm, |
| ctxt->d & ByteOp); |
| if (ctxt->d & Sse) { |
| op->type = OP_XMM; |
| op->bytes = 16; |
| op->addr.xmm = ctxt->modrm_rm; |
| read_sse_reg(ctxt, &op->vec_val, ctxt->modrm_rm); |
| return rc; |
| } |
| if (ctxt->d & Mmx) { |
| op->type = OP_MM; |
| op->bytes = 8; |
| op->addr.mm = ctxt->modrm_rm & 7; |
| return rc; |
| } |
| fetch_register_operand(op); |
| return rc; |
| } |
| |
| op->type = OP_MEM; |
| |
| if (ctxt->ad_bytes == 2) { |
| unsigned bx = reg_read(ctxt, VCPU_REGS_RBX); |
| unsigned bp = reg_read(ctxt, VCPU_REGS_RBP); |
| unsigned si = reg_read(ctxt, VCPU_REGS_RSI); |
| unsigned di = reg_read(ctxt, VCPU_REGS_RDI); |
| |
| /* 16-bit ModR/M decode. */ |
| switch (ctxt->modrm_mod) { |
| case 0: |
| if (ctxt->modrm_rm == 6) |
| modrm_ea += insn_fetch(u16, ctxt); |
| break; |
| case 1: |
| modrm_ea += insn_fetch(s8, ctxt); |
| break; |
| case 2: |
| modrm_ea += insn_fetch(u16, ctxt); |
| break; |
| } |
| switch (ctxt->modrm_rm) { |
| case 0: |
| modrm_ea += bx + si; |
| break; |
| case 1: |
| modrm_ea += bx + di; |
| break; |
| case 2: |
| modrm_ea += bp + si; |
| break; |
| case 3: |
| modrm_ea += bp + di; |
| break; |
| case 4: |
| modrm_ea += si; |
| break; |
| case 5: |
| modrm_ea += di; |
| break; |
| case 6: |
| if (ctxt->modrm_mod != 0) |
| modrm_ea += bp; |
| break; |
| case 7: |
| modrm_ea += bx; |
| break; |
| } |
| if (ctxt->modrm_rm == 2 || ctxt->modrm_rm == 3 || |
| (ctxt->modrm_rm == 6 && ctxt->modrm_mod != 0)) |
| ctxt->modrm_seg = VCPU_SREG_SS; |
| modrm_ea = (u16)modrm_ea; |
| } else { |
| /* 32/64-bit ModR/M decode. */ |
| if ((ctxt->modrm_rm & 7) == 4) { |
| sib = insn_fetch(u8, ctxt); |
| index_reg |= (sib >> 3) & 7; |
| base_reg |= sib & 7; |
| scale = sib >> 6; |
| |
| if ((base_reg & 7) == 5 && ctxt->modrm_mod == 0) |
| modrm_ea += insn_fetch(s32, ctxt); |
| else { |
| modrm_ea += reg_read(ctxt, base_reg); |
| adjust_modrm_seg(ctxt, base_reg); |
| } |
| if (index_reg != 4) |
| modrm_ea += reg_read(ctxt, index_reg) << scale; |
| } else if ((ctxt->modrm_rm & 7) == 5 && ctxt->modrm_mod == 0) { |
| modrm_ea += insn_fetch(s32, ctxt); |
| if (ctxt->mode == X86EMUL_MODE_PROT64) |
| ctxt->rip_relative = 1; |
| } else { |
| base_reg = ctxt->modrm_rm; |
| modrm_ea += reg_read(ctxt, base_reg); |
| adjust_modrm_seg(ctxt, base_reg); |
| } |
| switch (ctxt->modrm_mod) { |
| case 1: |
| modrm_ea += insn_fetch(s8, ctxt); |
| break; |
| case 2: |
| modrm_ea += insn_fetch(s32, ctxt); |
| break; |
| } |
| } |
| op->addr.mem.ea = modrm_ea; |
| if (ctxt->ad_bytes != 8) |
| ctxt->memop.addr.mem.ea = (u32)ctxt->memop.addr.mem.ea; |
| |
| done: |
| return rc; |
| } |
| |
| static int decode_abs(struct x86_emulate_ctxt *ctxt, |
| struct operand *op) |
| { |
| int rc = X86EMUL_CONTINUE; |
| |
| op->type = OP_MEM; |
| switch (ctxt->ad_bytes) { |
| case 2: |
| op->addr.mem.ea = insn_fetch(u16, ctxt); |
| break; |
| case 4: |
| op->addr.mem.ea = insn_fetch(u32, ctxt); |
| break; |
| case 8: |
| op->addr.mem.ea = insn_fetch(u64, ctxt); |
| break; |
| } |
| done: |
| return rc; |
| } |
| |
| static void fetch_bit_operand(struct x86_emulate_ctxt *ctxt) |
| { |
| long sv = 0, mask; |
| |
| if (ctxt->dst.type == OP_MEM && ctxt->src.type == OP_REG) { |
| mask = ~((long)ctxt->dst.bytes * 8 - 1); |
| |
| if (ctxt->src.bytes == 2) |
| sv = (s16)ctxt->src.val & (s16)mask; |
| else if (ctxt->src.bytes == 4) |
| sv = (s32)ctxt->src.val & (s32)mask; |
| else |
| sv = (s64)ctxt->src.val & (s64)mask; |
| |
| ctxt->dst.addr.mem.ea = address_mask(ctxt, |
| ctxt->dst.addr.mem.ea + (sv >> 3)); |
| } |
| |
| /* only subword offset */ |
| ctxt->src.val &= (ctxt->dst.bytes << 3) - 1; |
| } |
| |
| static int read_emulated(struct x86_emulate_ctxt *ctxt, |
| unsigned long addr, void *dest, unsigned size) |
| { |
| int rc; |
| struct read_cache *mc = &ctxt->mem_read; |
| |
| if (mc->pos < mc->end) |
| goto read_cached; |
| |
| WARN_ON((mc->end + size) >= sizeof(mc->data)); |
| |
| rc = ctxt->ops->read_emulated(ctxt, addr, mc->data + mc->end, size, |
| &ctxt->exception); |
| if (rc != X86EMUL_CONTINUE) |
| return rc; |
| |
| mc->end += size; |
| |
| read_cached: |
| memcpy(dest, mc->data + mc->pos, size); |
| mc->pos += size; |
| return X86EMUL_CONTINUE; |
| } |
| |
| static int segmented_read(struct x86_emulate_ctxt *ctxt, |
| struct segmented_address addr, |
| void *data, |
| unsigned size) |
| { |
| int rc; |
| ulong linear; |
| |
| rc = linearize(ctxt, addr, size, false, &linear); |
| if (rc != X86EMUL_CONTINUE) |
| return rc; |
| return read_emulated(ctxt, linear, data, size); |
| } |
| |
| static int segmented_write(struct x86_emulate_ctxt *ctxt, |
| struct segmented_address addr, |
| const void *data, |
| unsigned size) |
| { |
| int rc; |
| ulong linear; |
| |
| rc = linearize(ctxt, addr, size, true, &linear); |
| if (rc != X86EMUL_CONTINUE) |
| return rc; |
| return ctxt->ops->write_emulated(ctxt, linear, data, size, |
| &ctxt->exception); |
| } |
| |
| static int segmented_cmpxchg(struct x86_emulate_ctxt *ctxt, |
| struct segmented_address addr, |
| const void *orig_data, const void *data, |
| unsigned size) |
| { |
| int rc; |
| ulong linear; |
| |
| rc = linearize(ctxt, addr, size, true, &linear); |
| if (rc != X86EMUL_CONTINUE) |
| return rc; |
| return ctxt->ops->cmpxchg_emulated(ctxt, linear, orig_data, data, |
| size, &ctxt->exception); |
| } |
| |
| static int pio_in_emulated(struct x86_emulate_ctxt *ctxt, |
| unsigned int size, unsigned short port, |
| void *dest) |
| { |
| struct read_cache *rc = &ctxt->io_read; |
| |
| if (rc->pos == rc->end) { /* refill pio read ahead */ |
| unsigned int in_page, n; |
| unsigned int count = ctxt->rep_prefix ? |
| address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) : 1; |
| in_page = (ctxt->eflags & EFLG_DF) ? |
| offset_in_page(reg_read(ctxt, VCPU_REGS_RDI)) : |
| PAGE_SIZE - offset_in_page(reg_read(ctxt, VCPU_REGS_RDI)); |
| n = min3(in_page, (unsigned int)sizeof(rc->data) / size, count); |
| if (n == 0) |
| n = 1; |
| rc->pos = rc->end = 0; |
| if (!ctxt->ops->pio_in_emulated(ctxt, size, port, rc->data, n)) |
| return 0; |
| rc->end = n * size; |
| } |
| |
| if (ctxt->rep_prefix && (ctxt->d & String) && |
| !(ctxt->eflags & EFLG_DF)) { |
| ctxt->dst.data = rc->data + rc->pos; |
| ctxt->dst.type = OP_MEM_STR; |
| ctxt->dst.count = (rc->end - rc->pos) / size; |
| rc->pos = rc->end; |
| } else { |
| memcpy(dest, rc->data + rc->pos, size); |
| rc->pos += size; |
| } |
| return 1; |
| } |
| |
| static int read_interrupt_descriptor(struct x86_emulate_ctxt *ctxt, |
| u16 index, struct desc_struct *desc) |
| { |
| struct desc_ptr dt; |
| ulong addr; |
| |
| ctxt->ops->get_idt(ctxt, &dt); |
| |
| if (dt.size < index * 8 + 7) |
| return emulate_gp(ctxt, index << 3 | 0x2); |
| |
| addr = dt.address + index * 8; |
| return ctxt->ops->read_std(ctxt, addr, desc, sizeof *desc, |
| &ctxt->exception); |
| } |
| |
| static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt, |
| u16 selector, struct desc_ptr *dt) |
| { |
| const struct x86_emulate_ops *ops = ctxt->ops; |
| u32 base3 = 0; |
| |
| if (selector & 1 << 2) { |
| struct desc_struct desc; |
| u16 sel; |
| |
| memset (dt, 0, sizeof *dt); |
| if (!ops->get_segment(ctxt, &sel, &desc, &base3, |
| VCPU_SREG_LDTR)) |
| return; |
| |
| dt->size = desc_limit_scaled(&desc); /* what if limit > 65535? */ |
| dt->address = get_desc_base(&desc) | ((u64)base3 << 32); |
| } else |
| ops->get_gdt(ctxt, dt); |
| } |
| |
| /* allowed just for 8 bytes segments */ |
| static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt, |
| u16 selector, struct desc_struct *desc, |
| ulong *desc_addr_p) |
| { |
| struct desc_ptr dt; |
| u16 index = selector >> 3; |
| ulong addr; |
| |
| get_descriptor_table_ptr(ctxt, selector, &dt); |
| |
| if (dt.size < index * 8 + 7) |
| return emulate_gp(ctxt, selector & 0xfffc); |
| |
| *desc_addr_p = addr = dt.address + index * 8; |
| return ctxt->ops->read_std(ctxt, addr, desc, sizeof *desc, |
| &ctxt->exception); |
| } |
| |
| /* allowed just for 8 bytes segments */ |
| static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt, |
| u16 selector, struct desc_struct *desc) |
| { |
| struct desc_ptr dt; |
| u16 index = selector >> 3; |
| ulong addr; |
| |
| get_descriptor_table_ptr(ctxt, selector, &dt); |
| |
| if (dt.size < index * 8 + 7) |
| return emulate_gp(ctxt, selector & 0xfffc); |
| |
| addr = dt.address + index * 8; |
| return ctxt->ops->write_std(ctxt, addr, desc, sizeof *desc, |
| &ctxt->exception); |
| } |
| |
| /* Does not support long mode */ |
| static int __load_segment_descriptor(struct x86_emulate_ctxt *ctxt, |
| u16 selector, int seg, u8 cpl, |
| bool in_task_switch, |
| struct desc_struct *desc) |
| { |
| struct desc_struct seg_desc, old_desc; |
| u8 dpl, rpl; |
| unsigned err_vec = GP_VECTOR; |
| u32 err_code = 0; |
| bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */ |
| ulong desc_addr; |
| int ret; |
| u16 dummy; |
| u32 base3 = 0; |
| |
| memset(&seg_desc, 0, sizeof seg_desc); |
| |
| if (ctxt->mode == X86EMUL_MODE_REAL) { |
| /* set real mode segment descriptor (keep limit etc. for |
| * unreal mode) */ |
| ctxt->ops->get_segment(ctxt, &dummy, &seg_desc, NULL, seg); |
| set_desc_base(&seg_desc, selector << 4); |
| goto load; |
| } else if (seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86) { |
| /* VM86 needs a clean new segment descriptor */ |
| set_desc_base(&seg_desc, selector << 4); |
| set_desc_limit(&seg_desc, 0xffff); |
| seg_desc.type = 3; |
| seg_desc.p = 1; |
| seg_desc.s = 1; |
| seg_desc.dpl = 3; |
| goto load; |
| } |
| |
| rpl = selector & 3; |
| |
| /* NULL selector is not valid for TR, CS and SS (except for long mode) */ |
| if ((seg == VCPU_SREG_CS |
| || (seg == VCPU_SREG_SS |
| && (ctxt->mode != X86EMUL_MODE_PROT64 || rpl != cpl)) |
| || seg == VCPU_SREG_TR) |
| && null_selector) |
| goto exception; |
| |
| /* TR should be in GDT only */ |
| if (seg == VCPU_SREG_TR && (selector & (1 << 2))) |
| goto exception; |
| |
| if (null_selector) /* for NULL selector skip all following checks */ |
| goto load; |
| |
| ret = read_segment_descriptor(ctxt, selector, &seg_desc, &desc_addr); |
| if (ret != X86EMUL_CONTINUE) |
| return ret; |
| |
| err_code = selector & 0xfffc; |
| err_vec = in_task_switch ? TS_VECTOR : GP_VECTOR; |
| |
| /* can't load system descriptor into segment selector */ |
| if (seg <= VCPU_SREG_GS && !seg_desc.s) |
| goto exception; |
| |
| if (!seg_desc.p) { |
| err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR; |
| goto exception; |
| } |
| |
| dpl = seg_desc.dpl; |
| |
| switch (seg) { |
| case VCPU_SREG_SS: |
| /* |
| * segment is not a writable data segment or segment |
| * selector's RPL != CPL or segment selector's RPL != CPL |
| */ |
| if (rpl != cpl || (seg_desc.type & 0xa) != 0x2 || dpl != cpl) |
| goto exception; |
| break; |
| case VCPU_SREG_CS: |
| if (!(seg_desc.type & 8)) |
| goto exception; |
| |
| if (seg_desc.type & 4) { |
| /* conforming */ |
| if (dpl > cpl) |
| goto exception; |
| } else { |
| /* nonconforming */ |
| if (rpl > cpl || dpl != cpl) |
| goto exception; |
| } |
| /* in long-mode d/b must be clear if l is set */ |
| if (seg_desc.d && seg_desc.l) { |
| u64 efer = 0; |
| |
| ctxt->ops->get_msr(ctxt, MSR_EFER, &efer); |
| if (efer & EFER_LMA) |
| goto exception; |
| } |
| |
| /* CS(RPL) <- CPL */ |
| selector = (selector & 0xfffc) | cpl; |
| break; |
| case VCPU_SREG_TR: |
| if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9)) |
| goto exception; |
| old_desc = seg_desc; |
| seg_desc.type |= 2; /* busy */ |
| ret = ctxt->ops->cmpxchg_emulated(ctxt, desc_addr, &old_desc, &seg_desc, |
| sizeof(seg_desc), &ctxt->exception); |
| if (ret != X86EMUL_CONTINUE) |
| return ret; |
| break; |
| case VCPU_SREG_LDTR: |
| if (seg_desc.s || seg_desc.type != 2) |
| goto exception; |
| break; |
| default: /* DS, ES, FS, or GS */ |
| /* |
| * segment is not a data or readable code segment or |
| * ((segment is a data or nonconforming code segment) |
| * and (both RPL and CPL > DPL)) |
| */ |
| if ((seg_desc.type & 0xa) == 0x8 || |
| (((seg_desc.type & 0xc) != 0xc) && |
| (rpl > dpl && cpl > dpl))) |
| goto exception; |
| break; |
| } |
| |
| if (seg_desc.s) { |
| /* mark segment as accessed */ |
| seg_desc.type |= 1; |
| ret = write_segment_descriptor(ctxt, selector, &seg_desc); |
| if (ret != X86EMUL_CONTINUE) |
| return ret; |
| } else if (ctxt->mode == X86EMUL_MODE_PROT64) { |
| ret = ctxt->ops->read_std(ctxt, desc_addr+8, &base3, |
| sizeof(base3), &ctxt->exception); |
| if (ret != X86EMUL_CONTINUE) |
| return ret; |
| if (is_noncanonical_address(get_desc_base(&seg_desc) | |
| ((u64)base3 << 32))) |
| return emulate_gp(ctxt, 0); |
| } |
| load: |
| ctxt->ops->set_segment(ctxt, selector, &seg_desc, base3, seg); |
| if (desc) |
| *desc = seg_desc; |
| return X86EMUL_CONTINUE; |
| exception: |
| return emulate_exception(ctxt, err_vec, err_code, true); |
| } |
| |
| static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt, |
| u16 selector, int seg) |
| { |
| u8 cpl = ctxt->ops->cpl(ctxt); |
| return __load_segment_descriptor(ctxt, selector, seg, cpl, false, NULL); |
| } |
| |
| static void write_register_operand(struct operand *op) |
| { |
| /* The 4-byte case *is* correct: in 64-bit mode we zero-extend. */ |
| switch (op->bytes) { |
| case 1: |
| *(u8 *)op->addr.reg = (u8)op->val; |
| break; |
| case 2: |
| *(u16 *)op->addr.reg = (u16)op->val; |
| break; |
| case 4: |
| *op->addr.reg = (u32)op->val; |
| break; /* 64b: zero-extend */ |
| case 8: |
| *op->addr.reg = op->val; |
| break; |
| } |
| } |
| |
| static int writeback(struct x86_emulate_ctxt *ctxt, struct operand *op) |
| { |
| switch (op->type) { |
| case OP_REG: |
| write_register_operand(op); |
| break; |
| case OP_MEM: |
| if (ctxt->lock_prefix) |
| return segmented_cmpxchg(ctxt, |
| op->addr.mem, |
| &op->orig_val, |
| &op->val, |
| op->bytes); |
| else |
| return segmented_write(ctxt, |
| op->addr.mem, |
| &op->val, |
| op->bytes); |
| break; |
| case OP_MEM_STR: |
| return segmented_write(ctxt, |
| op->addr.mem, |
| op->data, |
| op->bytes * op->count); |
| break; |
| case OP_XMM: |
| write_sse_reg(ctxt, &op->vec_val, op->addr.xmm); |
| break; |
| case OP_MM: |
| write_mmx_reg(ctxt, &op->mm_val, op->addr.mm); |
| break; |
| case OP_NONE: |
| /* no writeback */ |
| break; |
| default: |
| break; |
| } |
| return X86EMUL_CONTINUE; |
| } |
| |
| static int push(struct x86_emulate_ctxt *ctxt, void *data, int bytes) |
| { |
| struct segmented_address addr; |
| |
| rsp_increment(ctxt, -bytes); |
| addr.ea = reg_read(ctxt, VCPU_REGS_RSP) & stack_mask(ctxt); |
| addr.seg = VCPU_SREG_SS; |
| |
| return segmented_write(ctxt, addr, data, bytes); |
| } |
| |
| static int em_push(struct x86_emulate_ctxt *ctxt) |
| { |
| /* Disable writeback. */ |
| ctxt->dst.type = OP_NONE; |
| return push(ctxt, &ctxt->src.val, ctxt->op_bytes); |
| } |
| |
| static int emulate_pop(struct x86_emulate_ctxt *ctxt, |
| void *dest, int len) |
| { |
| int rc; |
| struct segmented_address addr; |
| |
| addr.ea = reg_read(ctxt, VCPU_REGS_RSP) & stack_mask(ctxt); |
| addr.seg = VCPU_SREG_SS; |
| rc = segmented_read(ctxt, addr, dest, len); |
| if (rc != X86EMUL_CONTINUE) |
| return rc; |
| |
| rsp_increment(ctxt, len); |
| return rc; |
| } |
| |
| static int em_pop(struct x86_emulate_ctxt *ctxt) |
| { |
| return emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes); |
| } |
| |
| static int emulate_popf(struct x86_emulate_ctxt *ctxt, |
| void *dest, int len) |
| { |
| int rc; |
| unsigned long val, change_mask; |
| int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT; |
| int cpl = ctxt->ops->cpl(ctxt); |
| |
| rc = emulate_pop(ctxt, &val, len); |
| if (rc != X86EMUL_CONTINUE) |
| return rc; |
| |
| change_mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_OF |
| | EFLG_TF | EFLG_DF | EFLG_NT | EFLG_AC | EFLG_ID; |
| |
| switch(ctxt->mode) { |
| case X86EMUL_MODE_PROT64: |
| case X86EMUL_MODE_PROT32: |
| case X86EMUL_MODE_PROT16: |
| if (cpl == 0) |
| change_mask |= EFLG_IOPL; |
| if (cpl <= iopl) |
| change_mask |= EFLG_IF; |
| break; |
| case X86EMUL_MODE_VM86: |
| if (iopl < 3) |
| return emulate_gp(ctxt, 0); |
| change_mask |= EFLG_IF; |
| break; |
| default: /* real mode */ |
| change_mask |= (EFLG_IOPL | EFLG_IF); |
| break; |
| } |
| |
| *(unsigned long *)dest = |
| (ctxt->eflags & ~change_mask) | (val & change_mask); |
| |
| return rc; |
| } |
| |
| static int em_popf(struct x86_emulate_ctxt *ctxt) |
| { |
| ctxt->dst.type = OP_REG; |
| ctxt->dst.addr.reg = &ctxt->eflags; |
| ctxt->dst.bytes = ctxt->op_bytes; |
| return emulate_popf(ctxt, &ctxt->dst.val, ctxt->op_bytes); |
| } |
| |
| static int em_enter(struct x86_emulate_ctxt *ctxt) |
| { |
| int rc; |
| unsigned frame_size = ctxt->src.val; |
| unsigned nesting_level = ctxt->src2.val & 31; |
| ulong rbp; |
| |
| if (nesting_level) |
| return X86EMUL_UNHANDLEABLE; |
| |
| rbp = reg_read(ctxt, VCPU_REGS_RBP); |
| rc = push(ctxt, &rbp, stack_size(ctxt)); |
| if (rc != X86EMUL_CONTINUE) |
| return rc; |
| assign_masked(reg_rmw(ctxt, VCPU_REGS_RBP), reg_read(ctxt, VCPU_REGS_RSP), |
| stack_mask(ctxt)); |
| assign_masked(reg_rmw(ctxt, VCPU_REGS_RSP), |
| reg_read(ctxt, VCPU_REGS_RSP) - frame_size, |
| stack_mask(ctxt)); |
| return X86EMUL_CONTINUE; |
| } |
| |
| static int em_leave(struct x86_emulate_ctxt *ctxt) |
| { |
| assign_masked(reg_rmw(ctxt, VCPU_REGS_RSP), reg_read(ctxt, VCPU_REGS_RBP), |
| stack_mask(ctxt)); |
| return emulate_pop(ctxt, reg_rmw(ctxt, VCPU_REGS_RBP), ctxt->op_bytes); |
| } |
| |
| static int em_push_sreg(struct x86_emulate_ctxt *ctxt) |
| { |
| int seg = ctxt->src2.val; |
| |
| ctxt->src.val = get_segment_selector(ctxt, seg); |
| if (ctxt->op_bytes == 4) { |
| rsp_increment(ctxt, -2); |
| ctxt->op_bytes = 2; |
| } |
| |
| return em_push(ctxt); |
| } |
| |
| static int em_pop_sreg(struct x86_emulate_ctxt *ctxt) |
| { |
| int seg = ctxt->src2.val; |
| unsigned long selector; |
| int rc; |
| |
| rc = emulate_pop(ctxt, &selector, ctxt->op_bytes); |
| if (rc != X86EMUL_CONTINUE) |
| return rc; |
| |
| if (ctxt->modrm_reg == VCPU_SREG_SS) |
| ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS; |
| |
| rc = load_segment_descriptor(ctxt, (u16)selector, seg); |
| return rc; |
| } |
| |
| static int em_pusha(struct x86_emulate_ctxt *ctxt) |
| { |
| unsigned long old_esp = reg_read(ctxt, VCPU_REGS_RSP); |
| int rc = X86EMUL_CONTINUE; |
| int reg = VCPU_REGS_RAX; |
| |
| while (reg <= VCPU_REGS_RDI) { |
| (reg == VCPU_REGS_RSP) ? |
| (ctxt->src.val = old_esp) : (ctxt->src.val = reg_read(ctxt, reg)); |
| |
| rc = em_push(ctxt); |
| if (rc != X86EMUL_CONTINUE) |
| return rc; |
| |
| ++reg; |
| } |
| |
| return rc; |
| } |
| |
| static int em_pushf(struct x86_emulate_ctxt *ctxt) |
| { |
| ctxt->src.val = (unsigned long)ctxt->eflags & ~EFLG_VM; |
| return em_push(ctxt); |
| } |
| |
| static int em_popa(struct x86_emulate_ctxt *ctxt) |
| { |
| int rc = X86EMUL_CONTINUE; |
| int reg = VCPU_REGS_RDI; |
| |
| while (reg >= VCPU_REGS_RAX) { |
| if (reg == VCPU_REGS_RSP) { |
| rsp_increment(ctxt, ctxt->op_bytes); |
| --reg; |
| } |
| |
| rc = emulate_pop(ctxt, reg_rmw(ctxt, reg), ctxt->op_bytes); |
| if (rc != X86EMUL_CONTINUE) |
| break; |
| --reg; |
| } |
| return rc; |
| } |
| |
| static int __emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq) |
| { |
| const struct x86_emulate_ops *ops = ctxt->ops; |
| int rc; |
| struct desc_ptr dt; |
| gva_t cs_addr; |
| gva_t eip_addr; |
| u16 cs, eip; |
| |
| /* TODO: Add limit checks */ |
| ctxt->src.val = ctxt->eflags; |
| rc = em_push(ctxt); |
| if (rc != X86EMUL_CONTINUE) |
| return rc; |
| |
| ctxt->eflags &= ~(EFLG_IF | EFLG_TF | EFLG_AC); |
| |
| ctxt->src.val = get_segment_selector(ctxt, VCPU_SREG_CS); |
| rc = em_push(ctxt); |
| if (rc != X86EMUL_CONTINUE) |
| return rc; |
| |
| ctxt->src.val = ctxt->_eip; |
| rc = em_push(ctxt); |
| if (rc != X86EMUL_CONTINUE) |
| return rc; |
| |
| ops->get_idt(ctxt, &dt); |
| |
| eip_addr = dt.address + (irq << 2); |
| cs_addr = dt.address + (irq << 2) + 2; |
| |
| rc = ops->read_std(ctxt, cs_addr, &cs, 2, &ctxt->exception); |
| if (rc != X86EMUL_CONTINUE) |
| return rc; |
| |
| rc = ops->read_std(ctxt, eip_addr, &eip, 2, &ctxt->exception); |
| if (rc != X86EMUL_CONTINUE) |
| return rc; |
| |
| rc = load_segment_descriptor(ctxt, cs, VCPU_SREG_CS); |
| if (rc != X86EMUL_CONTINUE) |
| return rc; |
| |
| ctxt->_eip = eip; |
| |
| return rc; |
| } |
| |
| int emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq) |
| { |
| int rc; |
| |
| invalidate_registers(ctxt); |
| rc = __emulate_int_real(ctxt, irq); |
| if (rc == X86EMUL_CONTINUE) |
| writeback_registers(ctxt); |
| return rc; |
| } |
| |
| static int emulate_int(struct x86_emulate_ctxt *ctxt, int irq) |
| { |
| switch(ctxt->mode) { |
| case X86EMUL_MODE_REAL: |
| return __emulate_int_real(ctxt, irq); |
| case X86EMUL_MODE_VM86: |
| case X86EMUL_MODE_PROT16: |
| case X86EMUL_MODE_PROT32: |
| case X86EMUL_MODE_PROT64: |
| default: |
| /* Protected mode interrupts unimplemented yet */ |
| return X86EMUL_UNHANDLEABLE; |
| } |
| } |
| |
| static int emulate_iret_real(struct x86_emulate_ctxt *ctxt) |
| { |
| int rc = X86EMUL_CONTINUE; |
| unsigned long temp_eip = 0; |
| unsigned long temp_eflags = 0; |
| unsigned long cs = 0; |
| unsigned long mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_TF | |
| EFLG_IF | EFLG_DF | EFLG_OF | EFLG_IOPL | EFLG_NT | EFLG_RF | |
| EFLG_AC | EFLG_ID | (1 << 1); /* Last one is the reserved bit */ |
| unsigned long vm86_mask = EFLG_VM | EFLG_VIF | EFLG_VIP; |
| |
| /* TODO: Add stack limit check */ |
| |
| rc = emulate_pop(ctxt, &temp_eip, ctxt->op_bytes); |
| |
| if (rc != X86EMUL_CONTINUE) |
| return rc; |
| |
| if (temp_eip & ~0xffff) |
| return emulate_gp(ctxt, 0); |
| |
| rc = emulate_pop(ctxt, &cs, ctxt->op_bytes); |
| |
| if (rc != X86EMUL_CONTINUE) |
| return rc; |
| |
| rc = emulate_pop(ctxt, &temp_eflags, ctxt->op_bytes); |
| |
| if (rc != X86EMUL_CONTINUE) |
| return rc; |
| |
| rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS); |
| |
| if (rc != X86EMUL_CONTINUE) |
| return rc; |
| |
| ctxt->_eip = temp_eip; |
| |
| |
| if (ctxt->op_bytes == 4) |
| ctxt->eflags = ((temp_eflags & mask) | (ctxt->eflags & vm86_mask)); |
| else if (ctxt->op_bytes == 2) { |
| ctxt->eflags &= ~0xffff; |
| ctxt->eflags |= temp_eflags; |
| } |
| |
| ctxt->eflags &= ~EFLG_RESERVED_ZEROS_MASK; /* Clear reserved zeros */ |
| ctxt->eflags |= EFLG_RESERVED_ONE_MASK; |
| |
| return rc; |
| } |
| |
| static int em_iret(struct x86_emulate_ctxt *ctxt) |
| { |
| switch(ctxt->mode) { |
| case X86EMUL_MODE_REAL: |
| return emulate_iret_real(ctxt); |
| case X86EMUL_MODE_VM86: |
| case X86EMUL_MODE_PROT16: |
| case X86EMUL_MODE_PROT32: |
| case X86EMUL_MODE_PROT64: |
| default: |
| /* iret from protected mode unimplemented yet */ |
| return X86EMUL_UNHANDLEABLE; |
| } |
| } |
| |
| static int em_jmp_far(struct x86_emulate_ctxt *ctxt) |
| { |
| int rc; |
| unsigned short sel, old_sel; |
| struct desc_struct old_desc, new_desc; |
| const struct x86_emulate_ops *ops = ctxt->ops; |
| u8 cpl = ctxt->ops->cpl(ctxt); |
| |
| /* Assignment of RIP may only fail in 64-bit mode */ |
| if (ctxt->mode == X86EMUL_MODE_PROT64) |
| ops->get_segment(ctxt, &old_sel, &old_desc, NULL, |
| VCPU_SREG_CS); |
| |
| memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2); |
| |
| rc = __load_segment_descriptor(ctxt, sel, VCPU_SREG_CS, cpl, false, |
| &new_desc); |
| if (rc != X86EMUL_CONTINUE) |
| return rc; |
| |
| rc = assign_eip_far(ctxt, ctxt->src.val, &new_desc); |
| if (rc != X86EMUL_CONTINUE) { |
| WARN_ON(ctxt->mode != X86EMUL_MODE_PROT64); |
| /* assigning eip failed; restore the old cs */ |
| ops->set_segment(ctxt, old_sel, &old_desc, 0, VCPU_SREG_CS); |
| return rc; |
| } |
| return rc; |
| } |
| |
| static int em_jmp_abs(struct x86_emulate_ctxt *ctxt) |
| { |
| return assign_eip_near(ctxt, ctxt->src.val); |
| } |
| |
| static int em_call_near_abs(struct x86_emulate_ctxt *ctxt) |
| { |
| int rc; |
| long int old_eip; |
| |
| old_eip = ctxt->_eip; |
| rc = assign_eip_near(ctxt, ctxt->src.val); |
| if (rc != X86EMUL_CONTINUE) |
| return rc; |
| ctxt->src.val = old_eip; |
| rc = em_push(ctxt); |
| return rc; |
| } |
| |
| static int em_cmpxchg8b(struct x86_emulate_ctxt *ctxt) |
| { |
| u64 old = ctxt->dst.orig_val64; |
| |
| if (ctxt->dst.bytes == 16) |
| return X86EMUL_UNHANDLEABLE; |
| |
| if (((u32) (old >> 0) != (u32) reg_read(ctxt, VCPU_REGS_RAX)) || |
| ((u32) (old >> 32) != (u32) reg_read(ctxt, VCPU_REGS_RDX))) { |
| *reg_write(ctxt, VCPU_REGS_RAX) = (u32) (old >> 0); |
| *reg_write(ctxt, VCPU_REGS_RDX) = (u32) (old >> 32); |
| ctxt->eflags &= ~EFLG_ZF; |
| } else { |
| ctxt->dst.val64 = ((u64)reg_read(ctxt, VCPU_REGS_RCX) << 32) | |
| (u32) reg_read(ctxt, VCPU_REGS_RBX); |
| |
| ctxt->eflags |= EFLG_ZF; |
| } |
| return X86EMUL_CONTINUE; |
| } |
| |
| static int em_ret(struct x86_emulate_ctxt *ctxt) |
| { |
| int rc; |
| unsigned long eip; |
| |
| rc = emulate_pop(ctxt, &eip, ctxt->op_bytes); |
| if (rc != X86EMUL_CONTINUE) |
| return rc; |
| |
| return assign_eip_near(ctxt, eip); |
| } |
| |
| static int em_ret_far(struct x86_emulate_ctxt *ctxt) |
| { |
| int rc; |
| unsigned long eip, cs; |
| u16 old_cs; |
| int cpl = ctxt->ops->cpl(ctxt); |
| struct desc_struct old_desc, new_desc; |
| const struct x86_emulate_ops *ops = ctxt->ops; |
| |
| if (ctxt->mode == X86EMUL_MODE_PROT64) |
| ops->get_segment(ctxt, &old_cs, &old_desc, NULL, |
| VCPU_SREG_CS); |
| |
| rc = emulate_pop(ctxt, &eip, ctxt->op_bytes); |
| if (rc != X86EMUL_CONTINUE) |
| return rc; |
| rc = emulate_pop(ctxt, &cs, ctxt->op_bytes); |
| if (rc != X86EMUL_CONTINUE) |
| return rc; |
| /* Outer-privilege level return is not implemented */ |
| if (ctxt->mode >= X86EMUL_MODE_PROT16 && (cs & 3) > cpl) |
| return X86EMUL_UNHANDLEABLE; |
| rc = __load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS, 0, false, |
| &new_desc); |
| if (rc != X86EMUL_CONTINUE) |
| return rc; |
| rc = assign_eip_far(ctxt, eip, &new_desc); |
| if (rc != X86EMUL_CONTINUE) { |
| WARN_ON(ctxt->mode != X86EMUL_MODE_PROT64); |
| ops->set_segment(ctxt, old_cs, &old_desc, 0, VCPU_SREG_CS); |
| } |
| return rc; |
| } |
| |
| static int em_ret_far_imm(struct x86_emulate_ctxt *ctxt) |
| { |
| int rc; |
| |
| rc = em_ret_far(ctxt); |
| if (rc != X86EMUL_CONTINUE) |
| return rc; |
| rsp_increment(ctxt, ctxt->src.val); |
| return X86EMUL_CONTINUE; |
| } |
| |
| static int em_cmpxchg(struct x86_emulate_ctxt *ctxt) |
| { |
| /* Save real source value, then compare EAX against destination. */ |
| ctxt->dst.orig_val = ctxt->dst.val; |
| ctxt->dst.val = reg_read(ctxt, VCPU_REGS_RAX); |
| ctxt->src.orig_val = ctxt->src.val; |
| ctxt->src.val = ctxt->dst.orig_val; |
| fastop(ctxt, em_cmp); |
| |
| if (ctxt->eflags & EFLG_ZF) { |
| /* Success: write back to memory. */ |
| ctxt->dst.val = ctxt->src.orig_val; |
| } else { |
| /* Failure: write the value we saw to EAX. */ |
| ctxt->dst.type = OP_REG; |
| ctxt->dst.addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX); |
| ctxt->dst.val = ctxt->dst.orig_val; |
| } |
| return X86EMUL_CONTINUE; |
| } |
| |
| static int em_lseg(struct x86_emulate_ctxt *ctxt) |
| { |
| int seg = ctxt->src2.val; |
| unsigned short sel; |
| int rc; |
| |
| memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2); |
| |
| rc = load_segment_descriptor(ctxt, sel, seg); |
| if (rc != X86EMUL_CONTINUE) |
| return rc; |
| |
| ctxt->dst.val = ctxt->src.val; |
| return rc; |
| } |
| |
| static void |
| setup_syscalls_segments(struct x86_emulate_ctxt *ctxt, |
| struct desc_struct *cs, struct desc_struct *ss) |
| { |
| cs->l = 0; /* will be adjusted later */ |
| set_desc_base(cs, 0); /* flat segment */ |
| cs->g = 1; /* 4kb granularity */ |
| set_desc_limit(cs, 0xfffff); /* 4GB limit */ |
| cs->type = 0x0b; /* Read, Execute, Accessed */ |
| cs->s = 1; |
| cs->dpl = 0; /* will be adjusted later */ |
| cs->p = 1; |
| cs->d = 1; |
| cs->avl = 0; |
| |
| set_desc_base(ss, 0); /* flat segment */ |
| set_desc_limit(ss, 0xfffff); /* 4GB limit */ |
| ss->g = 1; /* 4kb granularity */ |
| ss->s = 1; |
| ss->type = 0x03; /* Read/Write, Accessed */ |
| ss->d = 1; /* 32bit stack segment */ |
| ss->dpl = 0; |
| ss->p = 1; |
| ss->l = 0; |
| ss->avl = 0; |
| } |
| |
| static bool vendor_intel(struct x86_emulate_ctxt *ctxt) |
| { |
| u32 eax, ebx, ecx, edx; |
| |
| eax = ecx = 0; |
| ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx); |
| return ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx |
| && ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx |
| && edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx; |
| } |
| |
| static bool em_syscall_is_enabled(struct x86_emulate_ctxt *ctxt) |
| { |
| const struct x86_emulate_ops *ops = ctxt->ops; |
| u32 eax, ebx, ecx, edx; |
| |
| /* |
| * syscall should always be enabled in longmode - so only become |
| * vendor specific (cpuid) if other modes are active... |
| */ |
| if (ctxt->mode == X86EMUL_MODE_PROT64) |
| return true; |
| |
| eax = 0x00000000; |
| ecx = 0x00000000; |
| ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx); |
| /* |
| * Intel ("GenuineIntel") |
| * remark: Intel CPUs only support "syscall" in 64bit |
| * longmode. Also an 64bit guest with a |
| * 32bit compat-app running will #UD !! While this |
| * behaviour can be fixed (by emulating) into AMD |
| * response - CPUs of AMD can't behave like Intel. |
| */ |
| if (ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx && |
| ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx && |
| edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx) |
| return false; |
| |
| /* AMD ("AuthenticAMD") */ |
| if (ebx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ebx && |
| ecx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ecx && |
| edx == X86EMUL_CPUID_VENDOR_AuthenticAMD_edx) |
| return true; |
| |
| /* AMD ("AMDisbetter!") */ |
| if (ebx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ebx && |
| ecx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ecx && |
| edx == X86EMUL_CPUID_VENDOR_AMDisbetterI_edx) |
| return true; |
| |
| /* default: (not Intel, not AMD), apply Intel's stricter rules... */ |
| return false; |
| } |
| |
| static int em_syscall(struct x86_emulate_ctxt *ctxt) |
| { |
| const struct x86_emulate_ops *ops = ctxt->ops; |
| struct desc_struct cs, ss; |
| u64 msr_data; |
| u16 cs_sel, ss_sel; |
| u64 efer = 0; |
| |
| /* syscall is not available in real mode */ |
| if (ctxt->mode == X86EMUL_MODE_REAL || |
| ctxt->mode == X86EMUL_MODE_VM86) |
| return emulate_ud(ctxt); |
| |
| if (!(em_syscall_is_enabled(ctxt))) |
| return emulate_ud(ctxt); |
| |
| ops->get_msr(ctxt, MSR_EFER, &efer); |
| setup_syscalls_segments(ctxt, &cs, &ss); |
| |
| if (!(efer & EFER_SCE)) |
| return emulate_ud(ctxt); |
| |
| ops->get_msr(ctxt, MSR_STAR, &msr_data); |
| msr_data >>= 32; |
| cs_sel = (u16)(msr_data & 0xfffc); |
| ss_sel = (u16)(msr_data + 8); |
| |
| if (efer & EFER_LMA) { |
| cs.d = 0; |
| cs.l = 1; |
| } |
| ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS); |
| ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS); |
| |
| *reg_write(ctxt, VCPU_REGS_RCX) = ctxt->_eip; |
| if (efer & EFER_LMA) { |
| #ifdef CONFIG_X86_64 |
| *reg_write(ctxt, VCPU_REGS_R11) = ctxt->eflags; |
| |
| ops->get_msr(ctxt, |
| ctxt->mode == X86EMUL_MODE_PROT64 ? |
| MSR_LSTAR : MSR_CSTAR, &msr_data); |
| ctxt->_eip = msr_data; |
| |
| ops->get_msr(ctxt, MSR_SYSCALL_MASK, &msr_data); |
| ctxt->eflags &= ~msr_data; |
| ctxt->eflags |= EFLG_RESERVED_ONE_MASK; |
| #endif |
| } else { |
| /* legacy mode */ |
| ops->get_msr(ctxt, MSR_STAR, &msr_data); |
| ctxt->_eip = (u32)msr_data; |
| |
| ctxt->eflags &= ~(EFLG_VM | EFLG_IF); |
| } |
| |
| return X86EMUL_CONTINUE; |
| } |
| |
| static int em_sysenter(struct x86_emulate_ctxt *ctxt) |
| { |
| const struct x86_emulate_ops *ops = ctxt->ops; |
| struct desc_struct cs, ss; |
| u64 msr_data; |
| u16 cs_sel, ss_sel; |
| u64 efer = 0; |
| |
| ops->get_msr(ctxt, MSR_EFER, &efer); |
| /* inject #GP if in real mode */ |
| if (ctxt->mode == X86EMUL_MODE_REAL) |
| return emulate_gp(ctxt, 0); |
| |
| /* |
| * Not recognized on AMD in compat mode (but is recognized in legacy |
| * mode). |
| */ |
| if ((ctxt->mode == X86EMUL_MODE_PROT32) && (efer & EFER_LMA) |
| && !vendor_intel(ctxt)) |
| return emulate_ud(ctxt); |
| |
| /* sysenter/sysexit have not been tested in 64bit mode. */ |
| if (ctxt->mode == X86EMUL_MODE_PROT64) |
| return X86EMUL_UNHANDLEABLE; |
| |
| setup_syscalls_segments(ctxt, &cs, &ss); |
| |
| ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data); |
| switch (ctxt->mode) { |
| case X86EMUL_MODE_PROT32: |
| if ((msr_data & 0xfffc) == 0x0) |
| return emulate_gp(ctxt, 0); |
| break; |
| case X86EMUL_MODE_PROT64: |
| if (msr_data == 0x0) |
| return emulate_gp(ctxt, 0); |
| break; |
| default: |
| break; |
| } |
| |
| ctxt->eflags &= ~(EFLG_VM | EFLG_IF); |
| cs_sel = (u16)msr_data; |
| cs_sel &= ~SELECTOR_RPL_MASK; |
| ss_sel = cs_sel + 8; |
| ss_sel &= ~SELECTOR_RPL_MASK; |
| if (ctxt->mode == X86EMUL_MODE_PROT64 || (efer & EFER_LMA)) { |
| cs.d = 0; |
| cs.l = 1; |
| } |
| |
| ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS); |
| ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS); |
| |
| ops->get_msr(ctxt, MSR_IA32_SYSENTER_EIP, &msr_data); |
| ctxt->_eip = msr_data; |
| |
| ops->get_msr(ctxt, MSR_IA32_SYSENTER_ESP, &msr_data); |
| *reg_write(ctxt, VCPU_REGS_RSP) = msr_data; |
| |
| return X86EMUL_CONTINUE; |
| } |
| |
| static int em_sysexit(struct x86_emulate_ctxt *ctxt) |
| { |
| const struct x86_emulate_ops *ops = ctxt->ops; |
| struct desc_struct cs, ss; |
| u64 msr_data, rcx, rdx; |
| int usermode; |
| u16 cs_sel = 0, ss_sel = 0; |
| |
| /* inject #GP if in real mode or Virtual 8086 mode */ |
| if (ctxt->mode == X86EMUL_MODE_REAL || |
| ctxt->mode == X86EMUL_MODE_VM86) |
| return emulate_gp(ctxt, 0); |
| |
| setup_syscalls_segments(ctxt, &cs, &ss); |
| |
| if ((ctxt->rex_prefix & 0x8) != 0x0) |
| usermode = X86EMUL_MODE_PROT64; |
| else |
| usermode = X86EMUL_MODE_PROT32; |
| |
| rcx = reg_read(ctxt, VCPU_REGS_RCX); |
| rdx = reg_read(ctxt, VCPU_REGS_RDX); |
| |
| cs.dpl = 3; |
| ss.dpl = 3; |
| ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data); |
| switch (usermode) { |
| case X86EMUL_MODE_PROT32: |
| cs_sel = (u16)(msr_data + 16); |
| if ((msr_data & 0xfffc) == 0x0) |
| return emulate_gp(ctxt, 0); |
| ss_sel = (u16)(msr_data + 24); |
| rcx = (u32)rcx; |
| rdx = (u32)rdx; |
| break; |
| case X86EMUL_MODE_PROT64: |
| cs_sel = (u16)(msr_data + 32); |
| if (msr_data == 0x0) |
| return emulate_gp(ctxt, 0); |
| ss_sel = cs_sel + 8; |
| cs.d = 0; |
| cs.l = 1; |
| if (is_noncanonical_address(rcx) || |
| is_noncanonical_address(rdx)) |
| return emulate_gp(ctxt, 0); |
| break; |
| } |
| cs_sel |= SELECTOR_RPL_MASK; |
| ss_sel |= SELECTOR_RPL_MASK; |
| |
| ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS); |
| ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS); |
| |
| ctxt->_eip = rdx; |
| *reg_write(ctxt, VCPU_REGS_RSP) = rcx; |
| |
| return X86EMUL_CONTINUE; |
| } |
| |
| static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt) |
| { |
| int iopl; |
| if (ctxt->mode == X86EMUL_MODE_REAL) |
| return false; |
| if (ctxt->mode == X86EMUL_MODE_VM86) |
| return true; |
| iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT; |
| return ctxt->ops->cpl(ctxt) > iopl; |
| } |
| |
| static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt, |
| u16 port, u16 len) |
| { |
| const struct x86_emulate_ops *ops = ctxt->ops; |
| struct desc_struct tr_seg; |
| u32 base3; |
| int r; |
| u16 tr, io_bitmap_ptr, perm, bit_idx = port & 0x7; |
| unsigned mask = (1 << len) - 1; |
| unsigned long base; |
| |
| ops->get_segment(ctxt, &tr, &tr_seg, &base3, VCPU_SREG_TR); |
| if (!tr_seg.p) |
| return false; |
| if (desc_limit_scaled(&tr_seg) < 103) |
| return false; |
| base = get_desc_base(&tr_seg); |
| #ifdef CONFIG_X86_64 |
| base |= ((u64)base3) << 32; |
| #endif |
| r = ops->read_std(ctxt, base + 102, &io_bitmap_ptr, 2, NULL); |
| if (r != X86EMUL_CONTINUE) |
| return false; |
| if (io_bitmap_ptr + port/8 > desc_limit_scaled(&tr_seg)) |
| return false; |
| r = ops->read_std(ctxt, base + io_bitmap_ptr + port/8, &perm, 2, NULL); |
| if (r != X86EMUL_CONTINUE) |
| return false; |
| if ((perm >> bit_idx) & mask) |
| return false; |
| return true; |
| } |
| |
| static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt, |
| u16 port, u16 len) |
| { |
| if (ctxt->perm_ok) |
| return true; |
| |
| if (emulator_bad_iopl(ctxt)) |
| if (!emulator_io_port_access_allowed(ctxt, port, len)) |
| return false; |
| |
| ctxt->perm_ok = true; |
| |
| return true; |
| } |
| |
| static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt, |
| struct tss_segment_16 *tss) |
| { |
| tss->ip = ctxt->_eip; |
| tss->flag = ctxt->eflags; |
| tss->ax = reg_read(ctxt, VCPU_REGS_RAX); |
| tss->cx = reg_read(ctxt, VCPU_REGS_RCX); |
| tss->dx = reg_read(ctxt, VCPU_REGS_RDX); |
| tss->bx = reg_read(ctxt, VCPU_REGS_RBX); |
| tss->sp = reg_read(ctxt, VCPU_REGS_RSP); |
| tss->bp = reg_read(ctxt, VCPU_REGS_RBP); |
| tss->si = reg_read(ctxt, VCPU_REGS_RSI); |
| tss->di = reg_read(ctxt, VCPU_REGS_RDI); |
| |
| tss->es = get_segment_selector(ctxt, VCPU_SREG_ES); |
| tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS); |
| tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS); |
| tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS); |
| tss->ldt = get_segment_selector(ctxt, VCPU_SREG_LDTR); |
| } |
| |
| static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt, |
| struct tss_segment_16 *tss) |
| { |
| int ret; |
| u8 cpl; |
| |
| ctxt->_eip = tss->ip; |
| ctxt->eflags = tss->flag | 2; |
| *reg_write(ctxt, VCPU_REGS_RAX) = tss->ax; |
| *reg_write(ctxt, VCPU_REGS_RCX) = tss->cx; |
| *reg_write(ctxt, VCPU_REGS_RDX) = tss->dx; |
| *reg_write(ctxt, VCPU_REGS_RBX) = tss->bx; |
| *reg_write(ctxt, VCPU_REGS_RSP) = tss->sp; |
| *reg_write(ctxt, VCPU_REGS_RBP) = tss->bp; |
| *reg_write(ctxt, VCPU_REGS_RSI) = tss->si; |
| *reg_write(ctxt, VCPU_REGS_RDI) = tss->di; |
| |
| /* |
| * SDM says that segment selectors are loaded before segment |
| * descriptors |
| */ |
| set_segment_selector(ctxt, tss->ldt, VCPU_SREG_LDTR); |
| set_segment_selector(ctxt, tss->es, VCPU_SREG_ES); |
| set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS); |
| set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS); |
| set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS); |
| |
| cpl = tss->cs & 3; |
| |
| /* |
| * Now load segment descriptors. If fault happens at this stage |
| * it is handled in a context of new task |
| */ |
| ret = __load_segment_descriptor(ctxt, tss->ldt, VCPU_SREG_LDTR, cpl, |
| true, NULL); |
| if (ret != X86EMUL_CONTINUE) |
| return ret; |
| ret = __load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES, cpl, |
| true, NULL); |
| if (ret != X86EMUL_CONTINUE) |
| return ret; |
| ret = __load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS, cpl, |
| true, NULL); |
| if (ret != X86EMUL_CONTINUE) |
| return ret; |
| ret = __load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS, cpl, |
| true, NULL); |
| if (ret != X86EMUL_CONTINUE) |
| return ret; |
| ret = __load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS, cpl, |
| true, NULL); |
| if (ret != X86EMUL_CONTINUE) |
| return ret; |
| |
| return X86EMUL_CONTINUE; |
| } |
| |
| static int task_switch_16(struct x86_emulate_ctxt *ctxt, |
| u16 tss_selector, u16 old_tss_sel, |
| ulong old_tss_base, struct desc_struct *new_desc) |
| { |
| const struct x86_emulate_ops *ops = ctxt->ops; |
| struct tss_segment_16 tss_seg; |
| int ret; |
| u32 new_tss_base = get_desc_base(new_desc); |
| |
| ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg, |
| &ctxt->exception); |
| if (ret != X86EMUL_CONTINUE) |
| return ret; |
| |
| save_state_to_tss16(ctxt, &tss_seg); |
| |
| ret = ops->write_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg, |
| &ctxt->exception); |
| if (ret != X86EMUL_CONTINUE) |
| return ret; |
| |
| ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg, |
| &ctxt->exception); |
| if (ret != X86EMUL_CONTINUE) |
| return ret; |
| |
| if (old_tss_sel != 0xffff) { |
| tss_seg.prev_task_link = old_tss_sel; |
| |
| ret = ops->write_std(ctxt, new_tss_base, |
| &tss_seg.prev_task_link, |
| sizeof tss_seg.prev_task_link, |
| &ctxt->exception); |
| if (ret != X86EMUL_CONTINUE) |
| return ret; |
| } |
| |
| return load_state_from_tss16(ctxt, &tss_seg); |
| } |
| |
| static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt, |
| struct tss_segment_32 *tss) |
| { |
| /* CR3 and ldt selector are not saved intentionally */ |
| tss->eip = ctxt->_eip; |
| tss->eflags = ctxt->eflags; |
| tss->eax = reg_read(ctxt, VCPU_REGS_RAX); |
| tss->ecx = reg_read(ctxt, VCPU_REGS_RCX); |
| tss->edx = reg_read(ctxt, VCPU_REGS_RDX); |
| tss->ebx = reg_read(ctxt, VCPU_REGS_RBX); |
| tss->esp = reg_read(ctxt, VCPU_REGS_RSP); |
| tss->ebp = reg_read(ctxt, VCPU_REGS_RBP); |
| tss->esi = reg_read(ctxt, VCPU_REGS_RSI); |
| tss->edi = reg_read(ctxt, VCPU_REGS_RDI); |
| |
| tss->es = get_segment_selector(ctxt, VCPU_SREG_ES); |
| tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS); |
| tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS); |
| tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS); |
| tss->fs = get_segment_selector(ctxt, VCPU_SREG_FS); |
| tss->gs = get_segment_selector(ctxt, VCPU_SREG_GS); |
| } |
| |
| static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt, |
| struct tss_segment_32 *tss) |
| { |
| int ret; |
| u8 cpl; |
| |
| if (ctxt->ops->set_cr(ctxt, 3, tss->cr3)) |
| return emulate_gp(ctxt, 0); |
| ctxt->_eip = tss->eip; |
| ctxt->eflags = tss->eflags | 2; |
| |
| /* General purpose registers */ |
| *reg_write(ctxt, VCPU_REGS_RAX) = tss->eax; |
| *reg_write(ctxt, VCPU_REGS_RCX) = tss->ecx; |
| *reg_write(ctxt, VCPU_REGS_RDX) = tss->edx; |
| *reg_write(ctxt, VCPU_REGS_RBX) = tss->ebx; |
| *reg_write(ctxt, VCPU_REGS_RSP) = tss->esp; |
| *reg_write(ctxt, VCPU_REGS_RBP) = tss->ebp; |
| *reg_write(ctxt, VCPU_REGS_RSI) = tss->esi; |
| *reg_write(ctxt, VCPU_REGS_RDI) = tss->edi; |
| |
| /* |
| * SDM says that segment selectors are loaded before segment |
| * descriptors. This is important because CPL checks will |
| * use CS.RPL. |
| */ |
| set_segment_selector(ctxt, tss->ldt_selector, VCPU_SREG_LDTR); |
| set_segment_selector(ctxt, tss->es, VCPU_SREG_ES); |
| set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS); |
| set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS); |
| set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS); |
| set_segment_selector(ctxt, tss->fs, VCPU_SREG_FS); |
| set_segment_selector(ctxt, tss->gs, VCPU_SREG_GS); |
| |
| /* |
| * If we're switching between Protected Mode and VM86, we need to make |
| * sure to update the mode before loading the segment descriptors so |
| * that the selectors are interpreted correctly. |
| */ |
| if (ctxt->eflags & X86_EFLAGS_VM) { |
| ctxt->mode = X86EMUL_MODE_VM86; |
| cpl = 3; |
| } else { |
| ctxt->mode = X86EMUL_MODE_PROT32; |
| cpl = tss->cs & 3; |
| } |
| |
| /* |
| * Now load segment descriptors. If fault happenes at this stage |
| * it is handled in a context of new task |
| */ |
| ret = __load_segment_descriptor(ctxt, tss->ldt_selector, VCPU_SREG_LDTR, |
| cpl, true, NULL); |
| if (ret != X86EMUL_CONTINUE) |
| return ret; |
| ret = __load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES, cpl, |
| true, NULL); |
| if (ret != X86EMUL_CONTINUE) |
| return ret; |
| ret = __load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS, cpl, |
| true, NULL); |
| if (ret != X86EMUL_CONTINUE) |
| return ret; |
| ret = __load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS, cpl, |
| true, NULL); |
| if (ret != X86EMUL_CONTINUE) |
| return ret; |
| ret = __load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS, cpl, |
| true, NULL); |
| if (ret != X86EMUL_CONTINUE) |
| return ret; |
| ret = __load_segment_descriptor(ctxt, tss->fs, VCPU_SREG_FS, cpl, |
| true, NULL); |
| if (ret != X86EMUL_CONTINUE) |
| return ret; |
| ret = __load_segment_descriptor(ctxt, tss->gs, VCPU_SREG_GS, cpl, |
| true, NULL); |
| if (ret != X86EMUL_CONTINUE) |
| return ret; |
| |
| return X86EMUL_CONTINUE; |
| } |
| |
| static int task_switch_32(struct x86_emulate_ctxt *ctxt, |
| u16 tss_selector, u16 old_tss_sel, |
| ulong old_tss_base, struct desc_struct *new_desc) |
| { |
| const struct x86_emulate_ops *ops = ctxt->ops; |
| struct tss_segment_32 tss_seg; |
| int ret; |
| u32 new_tss_base = get_desc_base(new_desc); |
| u32 eip_offset = offsetof(struct tss_segment_32, eip); |
| u32 ldt_sel_offset = offsetof(struct tss_segment_32, ldt_selector); |
| |
| ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg, |
| &ctxt->exception); |
| if (ret != X86EMUL_CONTINUE) |
| /* FIXME: need to provide precise fault address */ |
| return ret; |
| |
| save_state_to_tss32(ctxt, &tss_seg); |
| |
| /* Only GP registers and segment selectors are saved */ |
| ret = ops->write_std(ctxt, old_tss_base + eip_offset, &tss_seg.eip, |
| ldt_sel_offset - eip_offset, &ctxt->exception); |
| if (ret != X86EMUL_CONTINUE) |
| /* FIXME: need to provide precise fault address */ |
| return ret; |
| |
| ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg, |
| &ctxt->exception); |
| if (ret != X86EMUL_CONTINUE) |
| /* FIXME: need to provide precise fault address */ |
| return ret; |
| |
| if (old_tss_sel != 0xffff) { |
| tss_seg.prev_task_link = old_tss_sel; |
| |
| ret = ops->write_std(ctxt, new_tss_base, |
| &tss_seg.prev_task_link, |
| sizeof tss_seg.prev_task_link, |
| &ctxt->exception); |
| if (ret != X86EMUL_CONTINUE) |
| /* FIXME: need to provide precise fault address */ |
| return ret; |
| } |
| |
| return load_state_from_tss32(ctxt, &tss_seg); |
| } |
| |
| static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt, |
| u16 tss_selector, int idt_index, int reason, |
| bool has_error_code, u32 error_code) |
| { |
| const struct x86_emulate_ops *ops = ctxt->ops; |
| struct desc_struct curr_tss_desc, next_tss_desc; |
| int ret; |
| u16 old_tss_sel = get_segment_selector(ctxt, VCPU_SREG_TR); |
| ulong old_tss_base = |
| ops->get_cached_segment_base(ctxt, VCPU_SREG_TR); |
| u32 desc_limit; |
| ulong desc_addr; |
| |
| /* FIXME: old_tss_base == ~0 ? */ |
| |
| ret = read_segment_descriptor(ctxt, tss_selector, &next_tss_desc, &desc_addr); |
| if (ret != X86EMUL_CONTINUE) |
| return ret; |
| ret = read_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc, &desc_addr); |
| if (ret != X86EMUL_CONTINUE) |
| return ret; |
| |
| /* FIXME: check that next_tss_desc is tss */ |
| |
| /* |
| * Check privileges. The three cases are task switch caused by... |
| * |
| * 1. jmp/call/int to task gate: Check against DPL of the task gate |
| * 2. Exception/IRQ/iret: No check is performed |
| * 3. jmp/call to TSS/task-gate: No check is performed since the |
| * hardware checks it before exiting. |
| */ |
| if (reason == TASK_SWITCH_GATE) { |
| if (idt_index != -1) { |
| /* Software interrupts */ |
| struct desc_struct task_gate_desc; |
| int dpl; |
| |
| ret = read_interrupt_descriptor(ctxt, idt_index, |
| &task_gate_desc); |
| if (ret != X86EMUL_CONTINUE) |
| return ret; |
| |
| dpl = task_gate_desc.dpl; |
| if ((tss_selector & 3) > dpl || ops->cpl(ctxt) > dpl) |
| return emulate_gp(ctxt, (idt_index << 3) | 0x2); |
| } |
| } |
| |
| desc_limit = desc_limit_scaled(&next_tss_desc); |
| if (!next_tss_desc.p || |
| ((desc_limit < 0x67 && (next_tss_desc.type & 8)) || |
| desc_limit < 0x2b)) { |
| return emulate_ts(ctxt, tss_selector & 0xfffc); |
| } |
| |
| if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) { |
| curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */ |
| write_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc); |
| } |
| |
| if (reason == TASK_SWITCH_IRET) |
| ctxt->eflags = ctxt->eflags & ~X86_EFLAGS_NT; |
| |
| /* set back link to prev task only if NT bit is set in eflags |
| note that old_tss_sel is not used after this point */ |
| if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE) |
| old_tss_sel = 0xffff; |
| |
| if (next_tss_desc.type & 8) |
| ret = task_switch_32(ctxt, tss_selector, old_tss_sel, |
| old_tss_base, &next_tss_desc); |
| else |
| ret = task_switch_16(ctxt, tss_selector, old_tss_sel, |
| old_tss_base, &next_tss_desc); |
| if (ret != X86EMUL_CONTINUE) |
| return ret; |
| |
| if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE) |
| ctxt->eflags = ctxt->eflags | X86_EFLAGS_NT; |
| |
| if (reason != TASK_SWITCH_IRET) { |
| next_tss_desc.type |= (1 << 1); /* set busy flag */ |
| write_segment_descriptor(ctxt, tss_selector, &next_tss_desc); |
| } |
| |
| ops->set_cr(ctxt, 0, ops->get_cr(ctxt, 0) | X86_CR0_TS); |
| ops->set_segment(ctxt, tss_selector, &next_tss_desc, 0, VCPU_SREG_TR); |
| |
| if (has_error_code) { |
| ctxt->op_bytes = ctxt->ad_bytes = (next_tss_desc.type & 8) ? 4 : 2; |
| ctxt->lock_prefix = 0; |
| ctxt->src.val = (unsigned long) error_code; |
| ret = em_push(ctxt); |
| } |
| |
| return ret; |
| } |
| |
| int emulator_task_switch(struct x86_emulate_ctxt *ctxt, |
| u16 tss_selector, int idt_index, int reason, |
| bool has_error_code, u32 error_code) |
| { |
| int rc; |
| |
| invalidate_registers(ctxt); |
| ctxt->_eip = ctxt->eip; |
| ctxt->dst.type = OP_NONE; |
| |
| rc = emulator_do_task_switch(ctxt, tss_selector, idt_index, reason, |
| has_error_code, error_code); |
| |
| if (rc == X86EMUL_CONTINUE) { |
| ctxt->eip = ctxt->_eip; |
| writeback_registers(ctxt); |
| } |
| |
| return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK; |
| } |
| |
| static void string_addr_inc(struct x86_emulate_ctxt *ctxt, int reg, |
| struct operand *op) |
| { |
| int df = (ctxt->eflags & EFLG_DF) ? -op->count : op->count; |
| |
| register_address_increment(ctxt, reg, df * op->bytes); |
| op->addr.mem.ea = register_address(ctxt, reg); |
| } |
| |
| static int em_das(struct x86_emulate_ctxt *ctxt) |
| { |
| u8 al, old_al; |
| bool af, cf, old_cf; |
| |
| cf = ctxt->eflags & X86_EFLAGS_CF; |
| al = ctxt->dst.val; |
| |
| old_al = al; |
| old_cf = cf; |
| cf = false; |
| af = ctxt->eflags & X86_EFLAGS_AF; |
| if ((al & 0x0f) > 9 || af) { |
| al -= 6; |
| cf = old_cf | (al >= 250); |
| af = true; |
| } else { |
| af = false; |
| } |
| if (old_al > 0x99 || old_cf) { |
| al -= 0x60; |
| cf = true; |
| } |
| |
| ctxt->dst.val = al; |
| /* Set PF, ZF, SF */ |
| ctxt->src.type = OP_IMM; |
| ctxt->src.val = 0; |
| ctxt->src.bytes = 1; |
| fastop(ctxt, em_or); |
| ctxt->eflags &= ~(X86_EFLAGS_AF | X86_EFLAGS_CF); |
| if (cf) |
| ctxt->eflags |= X86_EFLAGS_CF; |
| if (af) |
| ctxt->eflags |= X86_EFLAGS_AF; |
| return X86EMUL_CONTINUE; |
| } |
| |
| static int em_aam(struct x86_emulate_ctxt *ctxt) |
| { |
| u8 al, ah; |
| |
| if (ctxt->src.val == 0) |
| return emulate_de(ctxt); |
| |
| al = ctxt->dst.val & 0xff; |
| ah = al / ctxt->src.val; |
| al %= ctxt->src.val; |
| |
| ctxt->dst.val = (ctxt->dst.val & 0xffff0000) | al | (ah << 8); |
| |
| /* Set PF, ZF, SF */ |
| ctxt->src.type = OP_IMM; |
| ctxt->src.val = 0; |
| ctxt->src.bytes = 1; |
| fastop(ctxt, em_or); |
| |
| return X86EMUL_CONTINUE; |
| } |
| |
| static int em_aad(struct x86_emulate_ctxt *ctxt) |
| { |
| u8 al = ctxt->dst.val & 0xff; |
| u8 ah = (ctxt->dst.val >> 8) & 0xff; |
| |
| al = (al + (ah * ctxt->src.val)) & 0xff; |
| |
| ctxt->dst.val = (ctxt->dst.val & 0xffff0000) | al; |
| |
| /* Set PF, ZF, SF */ |
| ctxt->src.type = OP_IMM; |
| ctxt->src.val = 0; |
| ctxt->src.bytes = 1; |
| fastop(ctxt, em_or); |
| |
| return X86EMUL_CONTINUE; |
| } |
| |
| static int em_call(struct x86_emulate_ctxt *ctxt) |
| { |
| int rc; |
| long rel = ctxt->src.val; |
| |
| ctxt->src.val = (unsigned long)ctxt->_eip; |
| rc = jmp_rel(ctxt, rel); |
| if (rc != X86EMUL_CONTINUE) |
| return rc; |
| return em_push(ctxt); |
| } |
| |
| static int em_call_far(struct x86_emulate_ctxt *ctxt) |
| { |
| u16 sel, old_cs; |
| ulong old_eip; |
| int rc; |
| struct desc_struct old_desc, new_desc; |
| const struct x86_emulate_ops *ops = ctxt->ops; |
| int cpl = ctxt->ops->cpl(ctxt); |
| |
| old_eip = ctxt->_eip; |
| ops->get_segment(ctxt, &old_cs, &old_desc, NULL, VCPU_SREG_CS); |
| |
| memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2); |
| rc = __load_segment_descriptor(ctxt, sel, VCPU_SREG_CS, cpl, false, |
| &new_desc); |
| if (rc != X86EMUL_CONTINUE) |
| return X86EMUL_CONTINUE; |
| |
| rc = assign_eip_far(ctxt, ctxt->src.val, &new_desc); |
| if (rc != X86EMUL_CONTINUE) |
| goto fail; |
| |
| ctxt->src.val = old_cs; |
| rc = em_push(ctxt); |
| if (rc != X86EMUL_CONTINUE) |
| goto fail; |
| |
| ctxt->src.val = old_eip; |
| rc = em_push(ctxt); |
| /* If we failed, we tainted the memory, but the very least we should |
| restore cs */ |
| if (rc != X86EMUL_CONTINUE) |
| goto fail; |
| return rc; |
| fail: |
| ops->set_segment(ctxt, old_cs, &old_desc, 0, VCPU_SREG_CS); |
| return rc; |
| |
| } |
| |
| static int em_ret_near_imm(struct x86_emulate_ctxt *ctxt) |
| { |
| int rc; |
| unsigned long eip; |
| |
| rc = emulate_pop(ctxt, &eip, ctxt->op_bytes); |
| if (rc != X86EMUL_CONTINUE) |
| return rc; |
| rc = assign_eip_near(ctxt, eip); |
| if (rc != X86EMUL_CONTINUE) |
| return rc; |
| rsp_increment(ctxt, ctxt->src.val); |
| return X86EMUL_CONTINUE; |
| } |
| |
| static int em_xchg(struct x86_emulate_ctxt *ctxt) |
| { |
| /* Write back the register source. */ |
| ctxt->src.val = ctxt->dst.val; |
| write_register_operand(&ctxt->src); |
| |
| /* Write back the memory destination with implicit LOCK prefix. */ |
| ctxt->dst.val = ctxt->src.orig_val; |
| ctxt->lock_prefix = 1; |
| return X86EMUL_CONTINUE; |
| } |
| |
| static int em_imul_3op(struct x86_emulate_ctxt *ctxt) |
| { |
| ctxt->dst.val = ctxt->src2.val; |
| return fastop(ctxt, em_imul); |
| } |
| |
| static int em_cwd(struct x86_emulate_ctxt *ctxt) |
| { |
| ctxt->dst.type = OP_REG; |
| ctxt->dst.bytes = ctxt->src.bytes; |
| ctxt->dst.addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX); |
| ctxt->dst.val = ~((ctxt->src.val >> (ctxt->src.bytes * 8 - 1)) - 1); |
| |
| return X86EMUL_CONTINUE; |
| } |
| |
| static int em_rdtsc(struct x86_emulate_ctxt *ctxt) |
| { |
| u64 tsc = 0; |
| |
| ctxt->ops->get_msr(ctxt, MSR_IA32_TSC, &tsc); |
| *reg_write(ctxt, VCPU_REGS_RAX) = (u32)tsc; |
| *reg_write(ctxt, VCPU_REGS_RDX) = tsc >> 32; |
| return X86EMUL_CONTINUE; |
| } |
| |
| static int em_rdpmc(struct x86_emulate_ctxt *ctxt) |
| { |
| u64 pmc; |
| |
| if (ctxt->ops->read_pmc(ctxt, reg_read(ctxt, VCPU_REGS_RCX), &pmc)) |
| return emulate_gp(ctxt, 0); |
| *reg_write(ctxt, VCPU_REGS_RAX) = (u32)pmc; |
| *reg_write(ctxt, VCPU_REGS_RDX) = pmc >> 32; |
| return X86EMUL_CONTINUE; |
| } |
| |
| static int em_mov(struct x86_emulate_ctxt *ctxt) |
| { |
| memcpy(ctxt->dst.valptr, ctxt->src.valptr, sizeof(ctxt->src.valptr)); |
| return X86EMUL_CONTINUE; |
| } |
| |
| #define FFL(x) bit(X86_FEATURE_##x) |
| |
| static int em_movbe(struct x86_emulate_ctxt *ctxt) |
| { |
| u32 ebx, ecx, edx, eax = 1; |
| u16 tmp; |
| |
| /* |
| * Check MOVBE is set in the guest-visible CPUID leaf. |
| */ |
| ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx); |
| if (!(ecx & FFL(MOVBE))) |
| return emulate_ud(ctxt); |
| |
| switch (ctxt->op_bytes) { |
| case 2: |
| /* |
| * From MOVBE definition: "...When the operand size is 16 bits, |
| * the upper word of the destination register remains unchanged |
| * ..." |
| * |
| * Both casting ->valptr and ->val to u16 breaks strict aliasing |
| * rules so we have to do the operation almost per hand. |
| */ |
| tmp = (u16)ctxt->src.val; |
| ctxt->dst.val &= ~0xffffUL; |
| ctxt->dst.val |= (unsigned long)swab16(tmp); |
| break; |
| case 4: |
| ctxt->dst.val = swab32((u32)ctxt->src.val); |
| break; |
| case 8: |
| ctxt->dst.val = swab64(ctxt->src.val); |
| break; |
| default: |
| BUG(); |
| } |
| return X86EMUL_CONTINUE; |
| } |
| |
| static int em_cr_write(struct x86_emulate_ctxt *ctxt) |
| { |
| if (ctxt->ops->set_cr(ctxt, ctxt->modrm_reg, ctxt->src.val)) |
| return emulate_gp(ctxt, 0); |
| |
| /* Disable writeback. */ |
| ctxt->dst.type = OP_NONE; |
| return X86EMUL_CONTINUE; |
| } |
| |
| static int em_dr_write(struct x86_emulate_ctxt *ctxt) |
| { |
| unsigned long val; |
| |
| if (ctxt->mode == X86EMUL_MODE_PROT64) |
| val = ctxt->src.val & ~0ULL; |
| else |
| val = ctxt->src.val & ~0U; |
| |
| /* #UD condition is already handled. */ |
| if (ctxt->ops->set_dr(ctxt, ctxt->modrm_reg, val) < 0) |
| return emulate_gp(ctxt, 0); |
| |
| /* Disable writeback. */ |
| ctxt->dst.type = OP_NONE; |
| return X86EMUL_CONTINUE; |
| } |
| |
| static int em_wrmsr(struct x86_emulate_ctxt *ctxt) |
| { |
| u64 msr_data; |
| |
| msr_data = (u32)reg_read(ctxt, VCPU_REGS_RAX) |
| | ((u64)reg_read(ctxt, VCPU_REGS_RDX) << 32); |
| if (ctxt->ops->set_msr(ctxt, reg_read(ctxt, VCPU_REGS_RCX), msr_data)) |
| return emulate_gp(ctxt, 0); |
| |
| return X86EMUL_CONTINUE; |
| } |
| |
| static int em_rdmsr(struct x86_emulate_ctxt *ctxt) |
| { |
| u64 msr_data; |
| |
| if (ctxt->ops->get_msr(ctxt, reg_read(ctxt, VCPU_REGS_RCX), &msr_data)) |
| return emulate_gp(ctxt, 0); |
| |
| *reg_write(ctxt, VCPU_REGS_RAX) = (u32)msr_data; |
| *reg_write(ctxt, VCPU_REGS_RDX) = msr_data >> 32; |
| return X86EMUL_CONTINUE; |
| } |
| |
| static int em_mov_rm_sreg(struct x86_emulate_ctxt *ctxt) |
| { |
| if (ctxt->modrm_reg > VCPU_SREG_GS) |
| return emulate_ud(ctxt); |
| |
| ctxt->dst.val = get_segment_selector(ctxt, ctxt->modrm_reg); |
| if (ctxt->dst.bytes == 4 && ctxt->dst.type == OP_MEM) |
| ctxt->dst.bytes = 2; |
| return X86EMUL_CONTINUE; |
| } |
| |
| static int em_mov_sreg_rm(struct x86_emulate_ctxt *ctxt) |
| { |
| u16 sel = ctxt->src.val; |
| |
| if (ctxt->modrm_reg == VCPU_SREG_CS || ctxt->modrm_reg > VCPU_SREG_GS) |
| return emulate_ud(ctxt); |
| |
| if (ctxt->modrm_reg == VCPU_SREG_SS) |
| ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS; |
| |
| /* Disable writeback. */ |
| ctxt->dst.type = OP_NONE; |
| return load_segment_descriptor(ctxt, sel, ctxt->modrm_reg); |
| } |
| |
| static int em_lldt(struct x86_emulate_ctxt *ctxt) |
| { |
| u16 sel = ctxt->src.val; |
| |
| /* Disable writeback. */ |
| ctxt->dst.type = OP_NONE; |
| return load_segment_descriptor(ctxt, sel, VCPU_SREG_LDTR); |
| } |
| |
| static int em_ltr(struct x86_emulate_ctxt *ctxt) |
| { |
| u16 sel = ctxt->src.val; |
| |
| /* Disable writeback. */ |
| ctxt->dst.type = OP_NONE; |
| return load_segment_descriptor(ctxt, sel, VCPU_SREG_TR); |
| } |
| |
| static int em_invlpg(struct x86_emulate_ctxt *ctxt) |
| { |
| int rc; |
| ulong linear; |
| |
| rc = linearize(ctxt, ctxt->src.addr.mem, 1, false, &linear); |
| if (rc == X86EMUL_CONTINUE) |
| ctxt->ops->invlpg(ctxt, linear); |
| /* Disable writeback. */ |
| ctxt->dst.type = OP_NONE; |
| return X86EMUL_CONTINUE; |
| } |
| |
| static int em_clts(struct x86_emulate_ctxt *ctxt) |
| { |
| ulong cr0; |
| |
| cr0 = ctxt->ops->get_cr(ctxt, 0); |
| cr0 &= ~X86_CR0_TS; |
| ctxt->ops->set_cr(ctxt, 0, cr0); |
| return X86EMUL_CONTINUE; |
| } |
| |
| static int em_vmcall(struct x86_emulate_ctxt *ctxt) |
| { |
| int rc = ctxt->ops->fix_hypercall(ctxt); |
| |
| if (rc != X86EMUL_CONTINUE) |
| return rc; |
| |
| /* Let the processor re-execute the fixed hypercall */ |
| ctxt->_eip = ctxt->eip; |
| /* Disable writeback. */ |
| ctxt->dst.type = OP_NONE; |
| return X86EMUL_CONTINUE; |
| } |
| |
| static int emulate_store_desc_ptr(struct x86_emulate_ctxt *ctxt, |
| void (*get)(struct x86_emulate_ctxt *ctxt, |
| struct desc_ptr *ptr)) |
| { |
| struct desc_ptr desc_ptr; |
| |
| if (ctxt->mode == X86EMUL_MODE_PROT64) |
| ctxt->op_bytes = 8; |
| get(ctxt, &desc_ptr); |
| if (ctxt->op_bytes == 2) { |
| ctxt->op_bytes = 4; |
| desc_ptr.address &= 0x00ffffff; |
| } |
| /* Disable writeback. */ |
| ctxt->dst.type = OP_NONE; |
| return segmented_write(ctxt, ctxt->dst.addr.mem, |
| &desc_ptr, 2 + ctxt->op_bytes); |
| } |
| |
| static int em_sgdt(struct x86_emulate_ctxt *ctxt) |
| { |
| return emulate_store_desc_ptr(ctxt, ctxt->ops->get_gdt); |
| } |
| |
| static int em_sidt(struct x86_emulate_ctxt *ctxt) |
| { |
| return emulate_store_desc_ptr(ctxt, ctxt->ops->get_idt); |
| } |
| |
| static int em_lgdt_lidt(struct x86_emulate_ctxt *ctxt, bool lgdt) |
| { |
| struct desc_ptr desc_ptr; |
| int rc; |
| |
| if (ctxt->mode == X86EMUL_MODE_PROT64) |
| ctxt->op_bytes = 8; |
| rc = read_descriptor(ctxt, ctxt->src.addr.mem, |
| &desc_ptr.size, &desc_ptr.address, |
| ctxt->op_bytes); |
| if (rc != X86EMUL_CONTINUE) |
| return rc; |
| if (ctxt->mode == X86EMUL_MODE_PROT64 && |
| is_noncanonical_address(desc_ptr.address)) |
| return emulate_gp(ctxt, 0); |
| if (lgdt) |
| ctxt->ops->set_gdt(ctxt, &desc_ptr); |
| else |
| ctxt->ops->set_idt(ctxt, &desc_ptr); |
| /* Disable writeback. */ |
| ctxt->dst.type = OP_NONE; |
| return X86EMUL_CONTINUE; |
| } |
| |
| static int em_lgdt(struct x86_emulate_ctxt *ctxt) |
| { |
| return em_lgdt_lidt(ctxt, true); |
| } |
| |
| static int em_vmmcall(struct x86_emulate_ctxt *ctxt) |
| { |
| int rc; |
| |
| rc = ctxt->ops->fix_hypercall(ctxt); |
| |
| /* Disable writeback. */ |
| ctxt->dst.type = OP_NONE; |
| return rc; |
| } |
| |
| static int em_lidt(struct x86_emulate_ctxt *ctxt) |
| { |
| return em_lgdt_lidt(ctxt, false); |
| } |
| |
| static int em_smsw(struct x86_emulate_ctxt *ctxt) |
| { |
| if (ctxt->dst.type == OP_MEM) |
| ctxt->dst.bytes = 2; |
| ctxt->dst.val = ctxt->ops->get_cr(ctxt, 0); |
| return X86EMUL_CONTINUE; |
| } |
| |
| static int em_lmsw(struct x86_emulate_ctxt *ctxt) |
| { |
| ctxt->ops->set_cr(ctxt, 0, (ctxt->ops->get_cr(ctxt, 0) & ~0x0eul) |
| | (ctxt->src.val & 0x0f)); |
| ctxt->dst.type = OP_NONE; |
| return X86EMUL_CONTINUE; |
| } |
| |
| static int em_loop(struct x86_emulate_ctxt *ctxt) |
| { |
| int rc = X86EMUL_CONTINUE; |
| |
| register_address_increment(ctxt, VCPU_REGS_RCX, -1); |
| if ((address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) != 0) && |
| (ctxt->b == 0xe2 || test_cc(ctxt->b ^ 0x5, ctxt->eflags))) |
| rc = jmp_rel(ctxt, ctxt->src.val); |
| |
| return rc; |
| } |
| |
| static int em_jcxz(struct x86_emulate_ctxt *ctxt) |
| { |
| int rc = X86EMUL_CONTINUE; |
| |
| if (address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) == 0) |
| rc = jmp_rel(ctxt, ctxt->src.val); |
| |
| return rc; |
| } |
| |
| static int em_in(struct x86_emulate_ctxt *ctxt) |
| { |
| if (!pio_in_emulated(ctxt, ctxt->dst.bytes, ctxt->src.val, |
| &ctxt->dst.val)) |
| return X86EMUL_IO_NEEDED; |
| |
| return X86EMUL_CONTINUE; |
| } |
| |
| static int em_out(struct x86_emulate_ctxt *ctxt) |
| { |
| ctxt->ops->pio_out_emulated(ctxt, ctxt->src.bytes, ctxt->dst.val, |
| &ctxt->src.val, 1); |
| /* Disable writeback. */ |
| ctxt->dst.type = OP_NONE; |
| return X86EMUL_CONTINUE; |
| } |
| |
| static int em_cli(struct x86_emulate_ctxt *ctxt) |
| { |
| if (emulator_bad_iopl(ctxt)) |
| return emulate_gp(ctxt, 0); |
| |
| ctxt->eflags &= ~X86_EFLAGS_IF; |
| return X86EMUL_CONTINUE; |
| } |
| |
| static int em_sti(struct x86_emulate_ctxt *ctxt) |
| { |
| if (emulator_bad_iopl(ctxt)) |
| return emulate_gp(ctxt, 0); |
| |
| ctxt->interruptibility = KVM_X86_SHADOW_INT_STI; |
| ctxt->eflags |= X86_EFLAGS_IF; |
| return X86EMUL_CONTINUE; |
| } |
| |
| static int em_cpuid(struct x86_emulate_ctxt *ctxt) |
| { |
| u32 eax, ebx, ecx, edx; |
| |
| eax = reg_read(ctxt, VCPU_REGS_RAX); |
| ecx = reg_read(ctxt, VCPU_REGS_RCX); |
| ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx); |
| *reg_write(ctxt, VCPU_REGS_RAX) = eax; |
| *reg_write(ctxt, VCPU_REGS_RBX) = ebx; |
| *reg_write(ctxt, VCPU_REGS_RCX) = ecx; |
| *reg_write(ctxt, VCPU_REGS_RDX) = edx; |
| return X86EMUL_CONTINUE; |
| } |
| |
| static int em_sahf(struct x86_emulate_ctxt *ctxt) |
| { |
| u32 flags; |
| |
| flags = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF; |
| flags &= *reg_rmw(ctxt, VCPU_REGS_RAX) >> 8; |
| |
| ctxt->eflags &= ~0xffUL; |
| ctxt->eflags |= flags | X86_EFLAGS_FIXED; |
| return X86EMUL_CONTINUE; |
| } |
| |
| static int em_lahf(struct x86_emulate_ctxt *ctxt) |
| { |
| *reg_rmw(ctxt, VCPU_REGS_RAX) &= ~0xff00UL; |
| *reg_rmw(ctxt, VCPU_REGS_RAX) |= (ctxt->eflags & 0xff) << 8; |
| return X86EMUL_CONTINUE; |
| } |
| |
| static int em_bswap(struct x86_emulate_ctxt *ctxt) |
| { |
| switch (ctxt->op_bytes) { |
| #ifdef CONFIG_X86_64 |
| case 8: |
| asm("bswap %0" : "+r"(ctxt->dst.val)); |
| break; |
| #endif |
| default: |
| asm("bswap %0" : "+r"(*(u32 *)&ctxt->dst.val)); |
| break; |
| } |
| return X86EMUL_CONTINUE; |
| } |
| |
| static int em_clflush(struct x86_emulate_ctxt *ctxt) |
| { |
| /* emulating clflush regardless of cpuid */ |
| return X86EMUL_CONTINUE; |
| } |
| |
| static bool valid_cr(int nr) |
| { |
| switch (nr) { |
| case 0: |
| case 2 ... 4: |
| case 8: |
| return true; |
| default: |
| return false; |
| } |
| } |
| |
| static int check_cr_read(struct x86_emulate_ctxt *ctxt) |
| { |
| if (!valid_cr(ctxt->modrm_reg)) |
| return emulate_ud(ctxt); |
| |
| return X86EMUL_CONTINUE; |
| } |
| |
| static int check_cr_write(struct x86_emulate_ctxt *ctxt) |
| { |
| u64 new_val = ctxt->src.val64; |
| int cr = ctxt->modrm_reg; |
| u64 efer = 0; |
| |
| static u64 cr_reserved_bits[] = { |
| 0xffffffff00000000ULL, |
| 0, 0, 0, /* CR3 checked later */ |
| CR4_RESERVED_BITS, |
| 0, 0, 0, |
| CR8_RESERVED_BITS, |
| }; |
| |
| if (!valid_cr(cr)) |
| return emulate_ud(ctxt); |
| |
| if (new_val & cr_reserved_bits[cr]) |
| return emulate_gp(ctxt, 0); |
| |
| switch (cr) { |
| case 0: { |
| u64 cr4; |
| if (((new_val & X86_CR0_PG) && !(new_val & X86_CR0_PE)) || |
| ((new_val & X86_CR0_NW) && !(new_val & X86_CR0_CD))) |
| return emulate_gp(ctxt, 0); |
| |
| cr4 = ctxt->ops->get_cr(ctxt, 4); |
| ctxt->ops->get_msr(ctxt, MSR_EFER, &efer); |
| |
| if ((new_val & X86_CR0_PG) && (efer & EFER_LME) && |
| !(cr4 & X86_CR4_PAE)) |
| return emulate_gp(ctxt, 0); |
| |
| break; |
| } |
| case 3: { |
| u64 rsvd = 0; |
| |
| ctxt->ops->get_msr(ctxt, MSR_EFER, &efer); |
| if (efer & EFER_LMA) |
| rsvd = CR3_L_MODE_RESERVED_BITS & ~CR3_PCID_INVD; |
| |
| if (new_val & rsvd) |
| return emulate_gp(ctxt, 0); |
| |
| break; |
| } |
| case 4: { |
| ctxt->ops->get_msr(ctxt, MSR_EFER, &efer); |
| |
| if ((efer & EFER_LMA) && !(new_val & X86_CR4_PAE)) |
| return emulate_gp(ctxt, 0); |
| |
| break; |
| } |
| } |
| |
| return X86EMUL_CONTINUE; |
| } |
| |
| static int check_dr7_gd(struct x86_emulate_ctxt *ctxt) |
| { |
| unsigned long dr7; |
| |
| ctxt->ops->get_dr(ctxt, 7, &dr7); |
| |
| /* Check if DR7.Global_Enable is set */ |
| return dr7 & (1 << 13); |
| } |
| |
| static int check_dr_read(struct x86_emulate_ctxt *ctxt) |
| { |
| int dr = ctxt->modrm_reg; |
| u64 cr4; |
| |
| if (dr > 7) |
| return emulate_ud(ctxt); |
| |
| cr4 = ctxt->ops->get_cr(ctxt, 4); |
| if ((cr4 & X86_CR4_DE) && (dr == 4 || dr == 5)) |
| return emulate_ud(ctxt); |
| |
| if (check_dr7_gd(ctxt)) { |
| ulong dr6; |
| |
| ctxt->ops->get_dr(ctxt, 6, &dr6); |
| dr6 &= ~15; |
| dr6 |= DR6_BD | DR6_RTM; |
| ctxt->ops->set_dr(ctxt, 6, dr6); |
| return emulate_db(ctxt); |
| } |
| |
| return X86EMUL_CONTINUE; |
| } |
| |
| static int check_dr_write(struct x86_emulate_ctxt *ctxt) |
| { |
| u64 new_val = ctxt->src.val64; |
| int dr = ctxt->modrm_reg; |
| |
| if ((dr == 6 || dr == 7) && (new_val & 0xffffffff00000000ULL)) |
| return emulate_gp(ctxt, 0); |
| |
| return check_dr_read(ctxt); |
| } |
| |
| static int check_svme(struct x86_emulate_ctxt *ctxt) |
| { |
| u64 efer; |
| |
| ctxt->ops->get_msr(ctxt, MSR_EFER, &efer); |
| |
| if (!(efer & EFER_SVME)) |
| return emulate_ud(ctxt); |
| |
| return X86EMUL_CONTINUE; |
| } |
| |
| static int check_svme_pa(struct x86_emulate_ctxt *ctxt) |
| { |
| u64 rax = reg_read(ctxt, VCPU_REGS_RAX); |
| |
| /* Valid physical address? */ |
| if (rax & 0xffff000000000000ULL) |
| return emulate_gp(ctxt, 0); |
| |
| return check_svme(ctxt); |
| } |
| |
| static int check_rdtsc(struct x86_emulate_ctxt *ctxt) |
| { |
| u64 cr4 = ctxt->ops->get_cr(ctxt, 4); |
| |
| if (cr4 & X86_CR4_TSD && ctxt->ops->cpl(ctxt)) |
| return emulate_ud(ctxt); |
| |
| return X86EMUL_CONTINUE; |
| } |
| |
| static int check_rdpmc(struct x86_emulate_ctxt *ctxt) |
| { |
| u64 cr4 = ctxt->ops->get_cr(ctxt, 4); |
| u64 rcx = reg_read(ctxt, VCPU_REGS_RCX); |
| |
| if ((!(cr4 & X86_CR4_PCE) && ctxt->ops->cpl(ctxt)) || |
| ctxt->ops->check_pmc(ctxt, rcx)) |
| return emulate_gp(ctxt, 0); |
| |
| return X86EMUL_CONTINUE; |
| } |
| |
| static int check_perm_in(struct x86_emulate_ctxt *ctxt) |
| { |
| ctxt->dst.bytes = min(ctxt->dst.bytes, 4u); |
| if (!emulator_io_permited(ctxt, ctxt->src.val, ctxt->dst.bytes)) |
| return emulate_gp(ctxt, 0); |
| |
| return X86EMUL_CONTINUE; |
| } |
| |
| static int check_perm_out(struct x86_emulate_ctxt *ctxt) |
| { |
| ctxt->src.bytes = min(ctxt->src.bytes, 4u); |
| if (!emulator_io_permited(ctxt, ctxt->dst.val, ctxt->src.bytes)) |
| return emulate_gp(ctxt, 0); |
| |
| return X86EMUL_CONTINUE; |
| } |
| |
| #define D(_y) { .flags = (_y) } |
| #define DI(_y, _i) { .flags = (_y)|Intercept, .intercept = x86_intercept_##_i } |
| #define DIP(_y, _i, _p) { .flags = (_y)|Intercept|CheckPerm, \ |
| .intercept = x86_intercept_##_i, .check_perm = (_p) } |
| #define N D(NotImpl) |
| #define EXT(_f, _e) { .flags = ((_f) | RMExt), .u.group = (_e) } |
| #define G(_f, _g) { .flags = ((_f) | Group | ModRM), .u.group = (_g) } |
| #define GD(_f, _g) { .flags = ((_f) | GroupDual | ModRM), .u.gdual = (_g) } |
| #define ID(_f, _i) { .flags = ((_f) | InstrDual | ModRM), .u.idual = (_i) } |
| #define E(_f, _e) { .flags = ((_f) | Escape | ModRM), .u.esc = (_e) } |
| #define I(_f, _e) { .flags = (_f), .u.execute = (_e) } |
| #define F(_f, _e) { .flags = (_f) | Fastop, .u.fastop = (_e) } |
| #define II(_f, _e, _i) \ |
| { .flags = (_f)|Intercept, .u.execute = (_e), .intercept = x86_intercept_##_i } |
| #define IIP(_f, _e, _i, _p) \ |
| { .flags = (_f)|Intercept|CheckPerm, .u.execute = (_e), \ |
| .intercept = x86_intercept_##_i, .check_perm = (_p) } |
| #define GP(_f, _g) { .flags = ((_f) | Prefix), .u.gprefix = (_g) } |
| |
| #define D2bv(_f) D((_f) | ByteOp), D(_f) |
| #define D2bvIP(_f, _i, _p) DIP((_f) | ByteOp, _i, _p), DIP(_f, _i, _p) |
| #define I2bv(_f, _e) I((_f) | ByteOp, _e), I(_f, _e) |
| #define F2bv(_f, _e) F((_f) | ByteOp, _e), F(_f, _e) |
| #define I2bvIP(_f, _e, _i, _p) \ |
| IIP((_f) | ByteOp, _e, _i, _p), IIP(_f, _e, _i, _p) |
| |
| #define F6ALU(_f, _e) F2bv((_f) | DstMem | SrcReg | ModRM, _e), \ |
| F2bv(((_f) | DstReg | SrcMem | ModRM) & ~Lock, _e), \ |
| F2bv(((_f) & ~Lock) | DstAcc | SrcImm, _e) |
| |
| static const struct opcode group7_rm0[] = { |
| N, |
| I(SrcNone | Priv | EmulateOnUD, em_vmcall), |
| N, N, N, N, N, N, |
| }; |
| |
| static const struct opcode group7_rm1[] = { |
| DI(SrcNone | Priv, monitor), |
| DI(SrcNone | Priv, mwait), |
| N, N, N, N, N, N, |
| }; |
| |
| static const struct opcode group7_rm3[] = { |
| DIP(SrcNone | Prot | Priv, vmrun, check_svme_pa), |
| II(SrcNone | Prot | EmulateOnUD, em_vmmcall, vmmcall), |
| DIP(SrcNone | Prot | Priv, vmload, check_svme_pa), |
| DIP(SrcNone | Prot | Priv, vmsave, check_svme_pa), |
| DIP(SrcNone | Prot | Priv, stgi, check_svme), |
| DIP(SrcNone | Prot | Priv, clgi, check_svme), |
| DIP(SrcNone | Prot | Priv, skinit, check_svme), |
| DIP(SrcNone | Prot | Priv, invlpga, check_svme), |
| }; |
| |
| static const struct opcode group7_rm7[] = { |
| N, |
| DIP(SrcNone, rdtscp, check_rdtsc), |
| N, N, N, N, N, N, |
| }; |
| |
| static const struct opcode group1[] = { |
| F(Lock, em_add), |
| F(Lock | PageTable, em_or), |
| F(Lock, em_adc), |
| F(Lock, em_sbb), |
| F(Lock | PageTable, em_and), |
| F(Lock, em_sub), |
| F(Lock, em_xor), |
| F(NoWrite, em_cmp), |
| }; |
| |
| static const struct opcode group1A[] = { |
| I(DstMem | SrcNone | Mov | Stack, em_pop), N, N, N, N, N, N, N, |
| }; |
| |
| static const struct opcode group2[] = { |
| F(DstMem | ModRM, em_rol), |
| F(DstMem | ModRM, em_ror), |
| F(DstMem | ModRM, em_rcl), |
| F(DstMem | ModRM, em_rcr), |
| F(DstMem | ModRM, em_shl), |
| F(DstMem | ModRM, em_shr), |
| F(DstMem | ModRM, em_shl), |
| F(DstMem | ModRM, em_sar), |
| }; |
| |
| static const struct opcode group3[] = { |
| F(DstMem | SrcImm | NoWrite, em_test), |
| F(DstMem | SrcImm | NoWrite, em_test), |
| F(DstMem | SrcNone | Lock, em_not), |
| F(DstMem | SrcNone | Lock, em_neg), |
| F(DstXacc | Src2Mem, em_mul_ex), |
| F(DstXacc | Src2Mem, em_imul_ex), |
| F(DstXacc | Src2Mem, em_div_ex), |
| F(DstXacc | Src2Mem, em_idiv_ex), |
| }; |
| |
| static const struct opcode group4[] = { |
| F(ByteOp | DstMem | SrcNone | Lock, em_inc), |
| F(ByteOp | DstMem | SrcNone | Lock, em_dec), |
| N, N, N, N, N, N, |
| }; |
| |
| static const struct opcode group5[] = { |
| F(DstMem | SrcNone | Lock, em_inc), |
| F(DstMem | SrcNone | Lock, em_dec), |
| I(SrcMem | NearBranch, em_call_near_abs), |
| I(SrcMemFAddr | ImplicitOps | Stack, em_call_far), |
| I(SrcMem | NearBranch, em_jmp_abs), |
| I(SrcMemFAddr | ImplicitOps, em_jmp_far), |
| I(SrcMem | Stack, em_push), D(Undefined), |
| }; |
| |
| static const struct opcode group6[] = { |
| DI(Prot, sldt), |
| DI(Prot, str), |
| II(Prot | Priv | SrcMem16, em_lldt, lldt), |
| II(Prot | Priv | SrcMem16, em_ltr, ltr), |
| N, N, N, N, |
| }; |
| |
| static const struct group_dual group7 = { { |
| II(Mov | DstMem, em_sgdt, sgdt), |
| II(Mov | DstMem, em_sidt, sidt), |
| II(SrcMem | Priv, em_lgdt, lgdt), |
| II(SrcMem | Priv, em_lidt, lidt), |
| II(SrcNone | DstMem | Mov, em_smsw, smsw), N, |
| II(SrcMem16 | Mov | Priv, em_lmsw, lmsw), |
| II(SrcMem | ByteOp | Priv | NoAccess, em_invlpg, invlpg), |
| }, { |
| EXT(0, group7_rm0), |
| EXT(0, group7_rm1), |
| N, EXT(0, group7_rm3), |
| II(SrcNone | DstMem | Mov, em_smsw, smsw), N, |
| II(SrcMem16 | Mov | Priv, em_lmsw, lmsw), |
| EXT(0, group7_rm7), |
| } }; |
| |
| static const struct opcode group8[] = { |
| N, N, N, N, |
| F(DstMem | SrcImmByte | NoWrite, em_bt), |
| F(DstMem | SrcImmByte | Lock | PageTable, em_bts), |
| F(DstMem | SrcImmByte | Lock, em_btr), |
| F(DstMem | SrcImmByte | Lock | PageTable, em_btc), |
| }; |
| |
| static const struct group_dual group9 = { { |
| N, I(DstMem64 | Lock | PageTable, em_cmpxchg8b), N, N, N, N, N, N, |
| }, { |
| N, N, N, N, N, N, N, N, |
| } }; |
| |
| static const struct opcode group11[] = { |
| I(DstMem | SrcImm | Mov | PageTable, em_mov), |
| X7(D(Undefined)), |
| }; |
| |
| static const struct gprefix pfx_0f_ae_7 = { |
| I(SrcMem | ByteOp, em_clflush), N, N, N, |
| }; |
| |
| static const struct group_dual group15 = { { |
| N, N, N, N, N, N, N, GP(0, &pfx_0f_ae_7), |
| }, { |
| N, N, N, N, N, N, N, N, |
| } }; |
| |
| static const struct gprefix pfx_0f_6f_0f_7f = { |
| I(Mmx, em_mov), I(Sse | Aligned, em_mov), N, I(Sse | Unaligned, em_mov), |
| }; |
| |
| static const struct instr_dual instr_dual_0f_2b = { |
| I(0, em_mov), N |
| }; |
| |
| static const struct gprefix pfx_0f_2b = { |
| ID(0, &instr_dual_0f_2b), ID(0, &instr_dual_0f_2b), N, N, |
| }; |
| |
| static const struct gprefix pfx_0f_28_0f_29 = { |
| I(Aligned, em_mov), I(Aligned, em_mov), N, N, |
| }; |
| |
| static const struct gprefix pfx_0f_e7 = { |
| N, I(Sse, em_mov), N, N, |
| }; |
| |
| static const struct escape escape_d9 = { { |
| N, N, N, N, N, N, N, I(DstMem, em_fnstcw), |
| }, { |
| /* 0xC0 - 0xC7 */ |
| N, N, N, N, N, N, N, N, |
| /* 0xC8 - 0xCF */ |
| N, N, N, N, N, N, N, N, |
| /* 0xD0 - 0xC7 */ |
| N, N, N, N, N, N, N, N, |
| /* 0xD8 - 0xDF */ |
| N, N, N, N, N, N, N, N, |
| /* 0xE0 - 0xE7 */ |
| N, N, N, N, N, N, N, N, |
| /* 0xE8 - 0xEF */ |
| N, N, N, N, N, N, N, N, |
| /* 0xF0 - 0xF7 */ |
| N, N, N, N, N, N, N, N, |
| /* 0xF8 - 0xFF */ |
| N, N, N, N, N, N, N, N, |
| } }; |
| |
| static const struct escape escape_db = { { |
| N, N, N, N, N, N, N, N, |
| }, { |
| /* 0xC0 - 0xC7 */ |
| N, N, N, N, N, N, N, N, |
| /* 0xC8 - 0xCF */ |
| N, N, N, N, N, N, N, N, |
| /* 0xD0 - 0xC7 */ |
| N, N, N, N, N, N, N, N, |
| /* 0xD8 - 0xDF */ |
| N, N, N, N, N, N, N, N, |
| /* 0xE0 - 0xE7 */ |
| N, N, N, I(ImplicitOps, em_fninit), N, N, N, N, |
| /* 0xE8 - 0xEF */ |
| N, N, N, N, N, N, N, N, |
| /* 0xF0 - 0xF7 */ |
| N, N, N, N, N, N, N, N, |
| /* 0xF8 - 0xFF */ |
| N, N, N, N, N, N, N, N, |
| } }; |
| |
| static const struct escape escape_dd = { { |
| N, N, N, N, N, N, N, I(DstMem, em_fnstsw), |
| }, { |
| /* 0xC0 - 0xC7 */ |
| N, N, N, N, N, N, N, N, |
| /* 0xC8 - 0xCF */ |
| N, N, N, N, N, N, N, N, |
| /* 0xD0 - 0xC7 */ |
| N, N, N, N, N, N, N, N, |
| /* 0xD8 - 0xDF */ |
| N, N, N, N, N, N, N, N, |
| /* 0xE0 - 0xE7 */ |
| N, N, N, N, N, N, N, N, |
| /* 0xE8 - 0xEF */ |
| N, N, N, N, N, N, N, N, |
| /* 0xF0 - 0xF7 */ |
| N, N, N, N, N, N, N, N, |
| /* 0xF8 - 0xFF */ |
| N, N, N, N, N, N, N, N, |
| } }; |
| |
| static const struct instr_dual instr_dual_0f_c3 = { |
| I(DstMem | SrcReg | ModRM | No16 | Mov, em_mov), N |
| }; |
| |
| static const struct opcode opcode_table[256] = { |
| /* 0x00 - 0x07 */ |
| F6ALU(Lock, em_add), |
| I(ImplicitOps | Stack | No64 | Src2ES, em_push_sreg), |
| I(ImplicitOps | Stack | No64 | Src2ES, em_pop_sreg), |
| /* 0x08 - 0x0F */ |
| F6ALU(Lock | PageTable, em_or), |
| I(ImplicitOps | Stack | No64 | Src2CS, em_push_sreg), |
| N, |
| /* 0x10 - 0x17 */ |
| F6ALU(Lock, em_adc), |
| I(ImplicitOps | Stack | No64 | Src2SS, em_push_sreg), |
| I(ImplicitOps | Stack | No64 | Src2SS, em_pop_sreg), |
| /* 0x18 - 0x1F */ |
| F6ALU(Lock, em_sbb), |
| I(ImplicitOps | Stack | No64 | Src2DS, em_push_sreg), |
| I(ImplicitOps | Stack | No64 | Src2DS, em_pop_sreg), |
| /* 0x20 - 0x27 */ |
| F6ALU(Lock | PageTable, em_and), N, N, |
| /* 0x28 - 0x2F */ |
| F6ALU(Lock, em_sub), N, I(ByteOp | DstAcc | No64, em_das), |
| /* 0x30 - 0x37 */ |
| F6ALU(Lock, em_xor), N, N, |
| /* 0x38 - 0x3F */ |
| F6ALU(NoWrite, em_cmp), N, N, |
| /* 0x40 - 0x4F */ |
| X8(F(DstReg, em_inc)), X8(F(DstReg, em_dec)), |
| /* 0x50 - 0x57 */ |
| X8(I(SrcReg | Stack, em_push)), |
| /* 0x58 - 0x5F */ |
| X8(I(DstReg | Stack, em_pop)), |
| /* 0x60 - 0x67 */ |
| I(ImplicitOps | Stack | No64, em_pusha), |
| I(ImplicitOps | Stack | No64, em_popa), |
| N, D(DstReg | SrcMem32 | ModRM | Mov) /* movsxd (x86/64) */ , |
| N, N, N, N, |
| /* 0x68 - 0x6F */ |
| I(SrcImm | Mov | Stack, em_push), |
| I(DstReg | SrcMem | ModRM | Src2Imm, em_imul_3op), |
| I(SrcImmByte | Mov | Stack, em_push), |
| I(DstReg | SrcMem | ModRM | Src2ImmByte, em_imul_3op), |
| I2bvIP(DstDI | SrcDX | Mov | String | Unaligned, em_in, ins, check_perm_in), /* insb, insw/insd */ |
| I2bvIP(SrcSI | DstDX | String, em_out, outs, check_perm_out), /* outsb, outsw/outsd */ |
| /* 0x70 - 0x7F */ |
| X16(D(SrcImmByte | NearBranch)), |
| /* 0x80 - 0x87 */ |
| G(ByteOp | DstMem | SrcImm, group1), |
| G(DstMem | SrcImm, group1), |
| G(ByteOp | DstMem | SrcImm | No64, group1), |
| G(DstMem | SrcImmByte, group1), |
| F2bv(DstMem | SrcReg | ModRM | NoWrite, em_test), |
| I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_xchg), |
| /* 0x88 - 0x8F */ |
| I2bv(DstMem | SrcReg | ModRM | Mov | PageTable, em_mov), |
| I2bv(DstReg | SrcMem | ModRM | Mov, em_mov), |
| I(DstMem | SrcNone | ModRM | Mov | PageTable, em_mov_rm_sreg), |
| D(ModRM | SrcMem | NoAccess | DstReg), |
| I(ImplicitOps | SrcMem16 | ModRM, em_mov_sreg_rm), |
| G(0, group1A), |
| /* 0x90 - 0x97 */ |
| DI(SrcAcc | DstReg, pause), X7(D(SrcAcc | DstReg)), |
| /* 0x98 - 0x9F */ |
| D(DstAcc | SrcNone), I(ImplicitOps | SrcAcc, em_cwd), |
| I(SrcImmFAddr | No64, em_call_far), N, |
| II(ImplicitOps | Stack, em_pushf, pushf), |
| II(ImplicitOps | Stack, em_popf, popf), |
| I(ImplicitOps, em_sahf), I(ImplicitOps, em_lahf), |
| /* 0xA0 - 0xA7 */ |
| I2bv(DstAcc | SrcMem | Mov | MemAbs, em_mov), |
| I2bv(DstMem | SrcAcc | Mov | MemAbs | PageTable, em_mov), |
| I2bv(SrcSI | DstDI | Mov | String, em_mov), |
| F2bv(SrcSI | DstDI | String | NoWrite, em_cmp_r), |
| /* 0xA8 - 0xAF */ |
| F2bv(DstAcc | SrcImm | NoWrite, em_test), |
| I2bv(SrcAcc | DstDI | Mov | String, em_mov), |
| I2bv(SrcSI | DstAcc | Mov | String, em_mov), |
| F2bv(SrcAcc | DstDI | String | NoWrite, em_cmp_r), |
| /* 0xB0 - 0xB7 */ |
| X8(I(ByteOp | DstReg | SrcImm | Mov, em_mov)), |
| /* 0xB8 - 0xBF */ |
| X8(I(DstReg | SrcImm64 | Mov, em_mov)), |
| /* 0xC0 - 0xC7 */ |
| G(ByteOp | Src2ImmByte, group2), G(Src2ImmByte, group2), |
| I(ImplicitOps | NearBranch | SrcImmU16, em_ret_near_imm), |
| I(ImplicitOps | NearBranch, em_ret), |
| I(DstReg | SrcMemFAddr | ModRM | No64 | Src2ES, em_lseg), |
| I(DstReg | SrcMemFAddr | ModRM | No64 | Src2DS, em_lseg), |
| G(ByteOp, group11), G(0, group11), |
| /* 0xC8 - 0xCF */ |
| I(Stack | SrcImmU16 | Src2ImmByte, em_enter), I(Stack, em_leave), |
| I(ImplicitOps | Stack | SrcImmU16, em_ret_far_imm), |
| I(ImplicitOps | Stack, em_ret_far), |
| D(ImplicitOps), DI(SrcImmByte, intn), |
| D(ImplicitOps | No64), II(ImplicitOps, em_iret, iret), |
| /* 0xD0 - 0xD7 */ |
| G(Src2One | ByteOp, group2), G(Src2One, group2), |
| G(Src2CL | ByteOp, group2), G(Src2CL, group2), |
| I(DstAcc | SrcImmUByte | No64, em_aam), |
| I(DstAcc | SrcImmUByte | No64, em_aad), |
| F(DstAcc | ByteOp | No64, em_salc), |
| I(DstAcc | SrcXLat | ByteOp, em_mov), |
| /* 0xD8 - 0xDF */ |
| N, E(0, &escape_d9), N, E(0, &escape_db), N, E(0, &escape_dd), N, N, |
| /* 0xE0 - 0xE7 */ |
| X3(I(SrcImmByte | NearBranch, em_loop)), |
| I(SrcImmByte | NearBranch, em_jcxz), |
| I2bvIP(SrcImmUByte | DstAcc, em_in, in, check_perm_in), |
| I2bvIP(SrcAcc | DstImmUByte, em_out, out, check_perm_out), |
| /* 0xE8 - 0xEF */ |
| I(SrcImm | NearBranch, em_call), D(SrcImm | ImplicitOps | NearBranch), |
| I(SrcImmFAddr | No64, em_jmp_far), |
| D(SrcImmByte | ImplicitOps | NearBranch), |
| I2bvIP(SrcDX | DstAcc, em_in, in, check_perm_in), |
| I2bvIP(SrcAcc | DstDX, em_out, out, check_perm_out), |
| /* 0xF0 - 0xF7 */ |
| N, DI(ImplicitOps, icebp), N, N, |
| DI(ImplicitOps | Priv, hlt), D(ImplicitOps), |
| G(ByteOp, group3), G(0, group3), |
| /* 0xF8 - 0xFF */ |
| D(ImplicitOps), D(ImplicitOps), |
| I(ImplicitOps, em_cli), I(ImplicitOps, em_sti), |
| D(ImplicitOps), D(ImplicitOps), G(0, group4), G(0, group5), |
| }; |
| |
| static const struct opcode twobyte_table[256] = { |
| /* 0x00 - 0x0F */ |
| G(0, group6), GD(0, &group7), N, N, |
| N, I(ImplicitOps | EmulateOnUD, em_syscall), |
| II(ImplicitOps | Priv, em_clts, clts), N, |
| DI(ImplicitOps | Priv, invd), DI(ImplicitOps | Priv, wbinvd), N, N, |
| N, D(ImplicitOps | ModRM | SrcMem | NoAccess), N, N, |
| /* 0x10 - 0x1F */ |
| N, N, N, N, N, N, N, N, |
| D(ImplicitOps | ModRM | SrcMem | NoAccess), |
| N, N, N, N, N, N, D(ImplicitOps | ModRM | SrcMem | NoAccess), |
| /* 0x20 - 0x2F */ |
| DIP(ModRM | DstMem | Priv | Op3264 | NoMod, cr_read, check_cr_read), |
| DIP(ModRM | DstMem | Priv | Op3264 | NoMod, dr_read, check_dr_read), |
| IIP(ModRM | SrcMem | Priv | Op3264 | NoMod, em_cr_write, cr_write, |
| check_cr_write), |
| IIP(ModRM | SrcMem | Priv | Op3264 | NoMod, em_dr_write, dr_write, |
| check_dr_write), |
| N, N, N, N, |
| GP(ModRM | DstReg | SrcMem | Mov | Sse, &pfx_0f_28_0f_29), |
| GP(ModRM | DstMem | SrcReg | Mov | Sse, &pfx_0f_28_0f_29), |
| N, GP(ModRM | DstMem | SrcReg | Mov | Sse, &pfx_0f_2b), |
| N, N, N, N, |
| /* 0x30 - 0x3F */ |
| II(ImplicitOps | Priv, em_wrmsr, wrmsr), |
| IIP(ImplicitOps, em_rdtsc, rdtsc, check_rdtsc), |
| II(ImplicitOps | Priv, em_rdmsr, rdmsr), |
| IIP(ImplicitOps, em_rdpmc, rdpmc, check_rdpmc), |
| I(ImplicitOps | EmulateOnUD, em_sysenter), |
| I(ImplicitOps | Priv | EmulateOnUD, em_sysexit), |
| N, N, |
| N, N, N, N, N, N, N, N, |
| /* 0x40 - 0x4F */ |
| X16(D(DstReg | SrcMem | ModRM)), |
| /* 0x50 - 0x5F */ |
| N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, |
| /* 0x60 - 0x6F */ |
| N, N, N, N, |
| N, N, N, N, |
| N, N, N, N, |
| N, N, N, GP(SrcMem | DstReg | ModRM | Mov, &pfx_0f_6f_0f_7f), |
| /* 0x70 - 0x7F */ |
| N, N, N, N, |
| N, N, N, N, |
| N, N, N, N, |
| N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_6f_0f_7f), |
| /* 0x80 - 0x8F */ |
| X16(D(SrcImm | NearBranch)), |
| /* 0x90 - 0x9F */ |
| X16(D(ByteOp | DstMem | SrcNone | ModRM| Mov)), |
| /* 0xA0 - 0xA7 */ |
| I(Stack | Src2FS, em_push_sreg), I(Stack | Src2FS, em_pop_sreg), |
| II(ImplicitOps, em_cpuid, cpuid), |
| F(DstMem | SrcReg | ModRM | BitOp | NoWrite, em_bt), |
| F(DstMem | SrcReg | Src2ImmByte | ModRM, em_shld), |
| F(DstMem | SrcReg | Src2CL | ModRM, em_shld), N, N, |
| /* 0xA8 - 0xAF */ |
| I(Stack | Src2GS, em_push_sreg), I(Stack | Src2GS, em_pop_sreg), |
| DI(ImplicitOps, rsm), |
| F(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_bts), |
| F(DstMem | SrcReg | Src2ImmByte | ModRM, em_shrd), |
| F(DstMem | SrcReg | Src2CL | ModRM, em_shrd), |
| GD(0, &group15), F(DstReg | SrcMem | ModRM, em_imul), |
| /* 0xB0 - 0xB7 */ |
| I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_cmpxchg), |
| I(DstReg | SrcMemFAddr | ModRM | Src2SS, em_lseg), |
| F(DstMem | SrcReg | ModRM | BitOp | Lock, em_btr), |
| I(DstReg | SrcMemFAddr | ModRM | Src2FS, em_lseg), |
| I(DstReg | SrcMemFAddr | ModRM | Src2GS, em_lseg), |
| D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov), |
| /* 0xB8 - 0xBF */ |
| N, N, |
| G(BitOp, group8), |
| F(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_btc), |
| F(DstReg | SrcMem | ModRM, em_bsf), F(DstReg | SrcMem | ModRM, em_bsr), |
| D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov), |
| /* 0xC0 - 0xC7 */ |
| F2bv(DstMem | SrcReg | ModRM | SrcWrite | Lock, em_xadd), |
| N, ID(0, &instr_dual_0f_c3), |
| N, N, N, GD(0, &group9), |
| /* 0xC8 - 0xCF */ |
| X8(I(DstReg, em_bswap)), |
| /* 0xD0 - 0xDF */ |
| N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, |
| /* 0xE0 - 0xEF */ |
| N, N, N, N, N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_e7), |
| N, N, N, N, N, N, N, N, |
| /* 0xF0 - 0xFF */ |
| N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N |
| }; |
| |
| static const struct instr_dual instr_dual_0f_38_f0 = { |
| I(DstReg | SrcMem | Mov, em_movbe), N |
| }; |
| |
| static const struct instr_dual instr_dual_0f_38_f1 = { |
| I(DstMem | SrcReg | Mov, em_movbe), N |
| }; |
| |
| static const struct gprefix three_byte_0f_38_f0 = { |
| ID(0, &instr_dual_0f_38_f0), N, N, N |
| }; |
| |
| static const struct gprefix three_byte_0f_38_f1 = { |
| ID(0, &instr_dual_0f_38_f1), N, N, N |
| }; |
| |
| /* |
| * Insns below are selected by the prefix which indexed by the third opcode |
| * byte. |
| */ |
| static const struct opcode opcode_map_0f_38[256] = { |
| /* 0x00 - 0x7f */ |
| X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), |
| /* 0x80 - 0xef */ |
| X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), |
| /* 0xf0 - 0xf1 */ |
| GP(EmulateOnUD | ModRM, &three_byte_0f_38_f0), |
| GP(EmulateOnUD | ModRM, &three_byte_0f_38_f1), |
| /* 0xf2 - 0xff */ |
| N, N, X4(N), X8(N) |
| }; |
| |
| #undef D |
| #undef N |
| #undef G |
| #undef GD |
| #undef I |
| #undef GP |
| #undef EXT |
| |
| #undef D2bv |
| #undef D2bvIP |
| #undef I2bv |
| #undef I2bvIP |
| #undef I6ALU |
| |
| static unsigned imm_size(struct x86_emulate_ctxt *ctxt) |
| { |
| unsigned size; |
| |
| size = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes; |
| if (size == 8) |
| size = 4; |
| return size; |
| } |
| |
| static int decode_imm(struct x86_emulate_ctxt *ctxt, struct operand *op, |
| unsigned size, bool sign_extension) |
| { |
| int rc = X86EMUL_CONTINUE; |
| |
| op->type = OP_IMM; |
| op->bytes = size; |
| op->addr.mem.ea = ctxt->_eip; |
| /* NB. Immediates are sign-extended as necessary. */ |
| switch (op->bytes) { |
| case 1: |
| op->val = insn_fetch(s8, ctxt); |
| break; |
| case 2: |
| op->val = insn_fetch(s16, ctxt); |
| break; |
| case 4: |
| op->val = insn_fetch(s32, ctxt); |
| break; |
| case 8: |
| op->val = insn_fetch(s64, ctxt); |
| break; |
| } |
| if (!sign_extension) { |
| switch (op->bytes) { |
| case 1: |
| op->val &= 0xff; |
| break; |
| case 2: |
| op->val &= 0xffff; |
| break; |
| case 4: |
| op->val &= 0xffffffff; |
| break; |
| } |
| } |
| done: |
| return rc; |
| } |
| |
| static int decode_operand(struct x86_emulate_ctxt *ctxt, struct operand *op, |
| unsigned d) |
| { |
| int rc = X86EMUL_CONTINUE; |
| |
| switch (d) { |
| case OpReg: |
| decode_register_operand(ctxt, op); |
| break; |
| case OpImmUByte: |
| rc = decode_imm(ctxt, op, 1, false); |
| break; |
| case OpMem: |
| ctxt->memop.bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes; |
| mem_common: |
| *op = ctxt->memop; |
| ctxt->memopp = op; |
| if (ctxt->d & BitOp) |
| fetch_bit_operand(ctxt); |
| op->orig_val = op->val; |
| break; |
| case OpMem64: |
| ctxt->memop.bytes = (ctxt->op_bytes == 8) ? 16 : 8; |
| goto mem_common; |
| case OpAcc: |
| op->type = OP_REG; |
| op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes; |
| op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX); |
| fetch_register_operand(op); |
| op->orig_val = op->val; |
| break; |
| case OpAccLo: |
| op->type = OP_REG; |
| op->bytes = (ctxt->d & ByteOp) ? 2 : ctxt->op_bytes; |
| op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX); |
| fetch_register_operand(op); |
| op->orig_val = op->val; |
| break; |
| case OpAccHi: |
| if (ctxt->d & ByteOp) { |
| op->type = OP_NONE; |
| break; |
| } |
| op->type = OP_REG; |
| op->bytes = ctxt->op_bytes; |
| op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX); |
| fetch_register_operand(op); |
| op->orig_val = op->val; |
| break; |
| case OpDI: |
| op->type = OP_MEM; |
| op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes; |
| op->addr.mem.ea = |
| register_address(ctxt, VCPU_REGS_RDI); |
| op->addr.mem.seg = VCPU_SREG_ES; |
| op->val = 0; |
| op->count = 1; |
| break; |
| case OpDX: |
| op->type = OP_REG; |
| op->bytes = 2; |
| op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX); |
| fetch_register_operand(op); |
| break; |
| case OpCL: |
| op->bytes = 1; |
| op->val = reg_read(ctxt, VCPU_REGS_RCX) & 0xff; |
| break; |
| case OpImmByte: |
| rc = decode_imm(ctxt, op, 1, true); |
| break; |
| case OpOne: |
| op->bytes = 1; |
| op->val = 1; |
| break; |
| case OpImm: |
| rc = decode_imm(ctxt, op, imm_size(ctxt), true); |
| break; |
| case OpImm64: |
| rc = decode_imm(ctxt, op, ctxt->op_bytes, true); |
| break; |
| case OpMem8: |
| ctxt->memop.bytes = 1; |
| if (ctxt->memop.type == OP_REG) { |
| ctxt->memop.addr.reg = decode_register(ctxt, |
| ctxt->modrm_rm, true); |
| fetch_register_operand(&ctxt->memop); |
| } |
| goto mem_common; |
| case OpMem16: |
| ctxt->memop.bytes = 2; |
| goto mem_common; |
| case OpMem32: |
| ctxt->memop.bytes = 4; |
| goto mem_common; |
| case OpImmU16: |
| rc = decode_imm(ctxt, op, 2, false); |
| break; |
| case OpImmU: |
| rc = decode_imm(ctxt, op, imm_size(ctxt), false); |
| break; |
| case OpSI: |
| op->type = OP_MEM; |
| op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes; |
| op->addr.mem.ea = |
| register_address(ctxt, VCPU_REGS_RSI); |
| op->addr.mem.seg = ctxt->seg_override; |
| op->val = 0; |
| op->count = 1; |
| break; |
| case OpXLat: |
| op->type = OP_MEM; |
| op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes; |
| op->addr.mem.ea = |
| address_mask(ctxt, |
| reg_read(ctxt, VCPU_REGS_RBX) + |
| (reg_read(ctxt, VCPU_REGS_RAX) & 0xff)); |
| op->addr.mem.seg = ctxt->seg_override; |
| op->val = 0; |
| break; |
| case OpImmFAddr: |
| op->type = OP_IMM; |
| op->addr.mem.ea = ctxt->_eip; |
| op->bytes = ctxt->op_bytes + 2; |
| insn_fetch_arr(op->valptr, op->bytes, ctxt); |
| break; |
| case OpMemFAddr: |
| ctxt->memop.bytes = ctxt->op_bytes + 2; |
| goto mem_common; |
| case OpES: |
| op->val = VCPU_SREG_ES; |
| break; |
| case OpCS: |
| op->val = VCPU_SREG_CS; |
| break; |
| case OpSS: |
| op->val = VCPU_SREG_SS; |
| break; |
| case OpDS: |
| op->val = VCPU_SREG_DS; |
| break; |
| case OpFS: |
| op->val = VCPU_SREG_FS; |
| break; |
| case OpGS: |
| op->val = VCPU_SREG_GS; |
| break; |
| case OpImplicit: |
| /* Special instructions do their own operand decoding. */ |
| default: |
| op->type = OP_NONE; /* Disable writeback. */ |
| break; |
| } |
| |
| done: |
| return rc; |
| } |
| |
| int x86_decode_insn(struct x86_emulate_ctxt *ctxt, void *insn, int insn_len) |
| { |
| int rc = X86EMUL_CONTINUE; |
| int mode = ctxt->mode; |
| int def_op_bytes, def_ad_bytes, goffset, simd_prefix; |
| bool op_prefix = false; |
| bool has_seg_override = false; |
| struct opcode opcode; |
| |
| ctxt->memop.type = OP_NONE; |
| ctxt->memopp = NULL; |
| ctxt->_eip = ctxt->eip; |
| ctxt->fetch.ptr = ctxt->fetch.data; |
| ctxt->fetch.end = ctxt->fetch.data + insn_len; |
| ctxt->opcode_len = 1; |
| if (insn_len > 0) |
| memcpy(ctxt->fetch.data, insn, insn_len); |
| else { |
| rc = __do_insn_fetch_bytes(ctxt, 1); |
| if (rc != X86EMUL_CONTINUE) |
| return rc; |
| } |
| |
| switch (mode) { |
| case X86EMUL_MODE_REAL: |
| case X86EMUL_MODE_VM86: |
| case X86EMUL_MODE_PROT16: |
| def_op_bytes = def_ad_bytes = 2; |
| break; |
| case X86EMUL_MODE_PROT32: |
| def_op_bytes = def_ad_bytes = 4; |
| break; |
| #ifdef CONFIG_X86_64 |
| case X86EMUL_MODE_PROT64: |
| def_op_bytes = 4; |
| def_ad_bytes = 8; |
| break; |
| #endif |
| default: |
| return EMULATION_FAILED; |
| } |
| |
| ctxt->op_bytes = def_op_bytes; |
| ctxt->ad_bytes = def_ad_bytes; |
| |
| /* Legacy prefixes. */ |
| for (;;) { |
| switch (ctxt->b = insn_fetch(u8, ctxt)) { |
| case 0x66: /* operand-size override */ |
| op_prefix = true; |
| /* switch between 2/4 bytes */ |
| ctxt->op_bytes = def_op_bytes ^ 6; |
| break; |
| case 0x67: /* address-size override */ |
| if (mode == X86EMUL_MODE_PROT64) |
| /* switch between 4/8 bytes */ |
| ctxt->ad_bytes = def_ad_bytes ^ 12; |
| else |
| /* switch between 2/4 bytes */ |
| ctxt->ad_bytes = def_ad_bytes ^ 6; |
| break; |
| case 0x26: /* ES override */ |
| case 0x2e: /* CS override */ |
| case 0x36: /* SS override */ |
| case 0x3e: /* DS override */ |
| has_seg_override = true; |
| ctxt->seg_override = (ctxt->b >> 3) & 3; |
| break; |
| case 0x64: /* FS override */ |
| case 0x65: /* GS override */ |
| has_seg_override = true; |
| ctxt->seg_override = ctxt->b & 7; |
| break; |
| case 0x40 ... 0x4f: /* REX */ |
| if (mode != X86EMUL_MODE_PROT64) |
| goto done_prefixes; |
| ctxt->rex_prefix = ctxt->b; |
| continue; |
| case 0xf0: /* LOCK */ |
| ctxt->lock_prefix = 1; |
| break; |
| case 0xf2: /* REPNE/REPNZ */ |
| case 0xf3: /* REP/REPE/REPZ */ |
| ctxt->rep_prefix = ctxt->b; |
| break; |
| default: |
| goto done_prefixes; |
| } |
| |
| /* Any legacy prefix after a REX prefix nullifies its effect. */ |
| |
| ctxt->rex_prefix = 0; |
| } |
| |
| done_prefixes: |
| |
| /* REX prefix. */ |
| if (ctxt->rex_prefix & 8) |
| ctxt->op_bytes = 8; /* REX.W */ |
| |
| /* Opcode byte(s). */ |
| opcode = opcode_table[ctxt->b]; |
| /* Two-byte opcode? */ |
| if (ctxt->b == 0x0f) { |
| ctxt->opcode_len = 2; |
| ctxt->b = insn_fetch(u8, ctxt); |
| opcode = twobyte_table[ctxt->b]; |
| |
| /* 0F_38 opcode map */ |
| if (ctxt->b == 0x38) { |
| ctxt->opcode_len = 3; |
| ctxt->b = insn_fetch(u8, ctxt); |
| opcode = opcode_map_0f_38[ctxt->b]; |
| } |
| } |
| ctxt->d = opcode.flags; |
| |
| if (ctxt->d & ModRM) |
| ctxt->modrm = insn_fetch(u8, ctxt); |
| |
| /* vex-prefix instructions are not implemented */ |
| if (ctxt->opcode_len == 1 && (ctxt->b == 0xc5 || ctxt->b == 0xc4) && |
| (mode == X86EMUL_MODE_PROT64 || (ctxt->modrm & 0xc0) == 0xc0)) { |
| ctxt->d = NotImpl; |
| } |
| |
| while (ctxt->d & GroupMask) { |
| switch (ctxt->d & GroupMask) { |
| case Group: |
| goffset = (ctxt->modrm >> 3) & 7; |
| opcode = opcode.u.group[goffset]; |
| break; |
| case GroupDual: |
| goffset = (ctxt->modrm >> 3) & 7; |
| if ((ctxt->modrm >> 6) == 3) |
| opcode = opcode.u.gdual->mod3[goffset]; |
| else |
| opcode = opcode.u.gdual->mod012[goffset]; |
| break; |
| case RMExt: |
| goffset = ctxt->modrm & 7; |
| opcode = opcode.u.group[goffset]; |
| break; |
| case Prefix: |
| if (ctxt->rep_prefix && op_prefix) |
| return EMULATION_FAILED; |
| simd_prefix = op_prefix ? 0x66 : ctxt->rep_prefix; |
| switch (simd_prefix) { |
| case 0x00: opcode = opcode.u.gprefix->pfx_no; break; |
| case 0x66: opcode = opcode.u.gprefix->pfx_66; break; |
| case 0xf2: opcode = opcode.u.gprefix->pfx_f2; break; |
| case 0xf3: opcode = opcode.u.gprefix->pfx_f3; break; |
| } |
| break; |
| case Escape: |
| if (ctxt->modrm > 0xbf) |
| opcode = opcode.u.esc->high[ctxt->modrm - 0xc0]; |
| else |
| opcode = opcode.u.esc->op[(ctxt->modrm >> 3) & 7]; |
| break; |
| case InstrDual: |
| if ((ctxt->modrm >> 6) == 3) |
| opcode = opcode.u.idual->mod3; |
| else |
| opcode = opcode.u.idual->mod012; |
| break; |
| default: |
| return EMULATION_FAILED; |
| } |
| |
| ctxt->d &= ~(u64)GroupMask; |
| ctxt->d |= opcode.flags; |
| } |
| |
| /* Unrecognised? */ |
| if (ctxt->d == 0) |
| return EMULATION_FAILED; |
| |
| ctxt->execute = opcode.u.execute; |
| |
| if (unlikely(ctxt->ud) && likely(!(ctxt->d & EmulateOnUD))) |
| return EMULATION_FAILED; |
| |
| if (unlikely(ctxt->d & |
| (NotImpl|Stack|Op3264|Sse|Mmx|Intercept|CheckPerm|NearBranch| |
| No16))) { |
| /* |
| * These are copied unconditionally here, and checked unconditionally |
| * in x86_emulate_insn. |
| */ |
| ctxt->check_perm = opcode.check_perm; |
| ctxt->intercept = opcode.intercept; |
| |
| if (ctxt->d & NotImpl) |
| return EMULATION_FAILED; |
| |
| if (mode == X86EMUL_MODE_PROT64) { |
| if (ctxt->op_bytes == 4 && (ctxt->d & Stack)) |
| ctxt->op_bytes = 8; |
| else if (ctxt->d & NearBranch) |
| ctxt->op_bytes = 8; |
| } |
| |
| if (ctxt->d & Op3264) { |
| if (mode == X86EMUL_MODE_PROT64) |
| ctxt->op_bytes = 8; |
| else |
| ctxt->op_bytes = 4; |
| } |
| |
| if ((ctxt->d & No16) && ctxt->op_bytes == 2) |
| ctxt->op_bytes = 4; |
| |
| if (ctxt->d & Sse) |
| ctxt->op_bytes = 16; |
| else if (ctxt->d & Mmx) |
| ctxt->op_bytes = 8; |
| } |
| |
| /* ModRM and SIB bytes. */ |
| if (ctxt->d & ModRM) { |
| rc = decode_modrm(ctxt, &ctxt->memop); |
| if (!has_seg_override) { |
| has_seg_override = true; |
| ctxt->seg_override = ctxt->modrm_seg; |
| } |
| } else if (ctxt->d & MemAbs) |
| rc = decode_abs(ctxt, &ctxt->memop); |
| if (rc != X86EMUL_CONTINUE) |
| goto done; |
| |
| if (!has_seg_override) |
| ctxt->seg_override = VCPU_SREG_DS; |
| |
| ctxt->memop.addr.mem.seg = ctxt->seg_override; |
| |
| /* |
| * Decode and fetch the source operand: register, memory |
| * or immediate. |
| */ |
| rc = decode_operand(ctxt, &ctxt->src, (ctxt->d >> SrcShift) & OpMask); |
| if (rc != X86EMUL_CONTINUE) |
| goto done; |
| |
| /* |
| * Decode and fetch the second source operand: register, memory |
| * or immediate. |
| */ |
| rc = decode_operand(ctxt, &ctxt->src2, (ctxt->d >> Src2Shift) & OpMask); |
| if (rc != X86EMUL_CONTINUE) |
| goto done; |
| |
| /* Decode and fetch the destination operand: register or memory. */ |
| rc = decode_operand(ctxt, &ctxt->dst, (ctxt->d >> DstShift) & OpMask); |
| |
| if (ctxt->rip_relative) |
| ctxt->memopp->addr.mem.ea = address_mask(ctxt, |
| ctxt->memopp->addr.mem.ea + ctxt->_eip); |
| |
| done: |
| return (rc != X86EMUL_CONTINUE) ? EMULATION_FAILED : EMULATION_OK; |
| } |
| |
| bool x86_page_table_writing_insn(struct x86_emulate_ctxt *ctxt) |
| { |
| return ctxt->d & PageTable; |
| } |
| |
| static bool string_insn_completed(struct x86_emulate_ctxt *ctxt) |
| { |
| /* The second termination condition only applies for REPE |
| * and REPNE. Test if the repeat string operation prefix is |
| * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the |
| * corresponding termination condition according to: |
| * - if REPE/REPZ and ZF = 0 then done |
| * - if REPNE/REPNZ and ZF = 1 then done |
| */ |
| if (((ctxt->b == 0xa6) || (ctxt->b == 0xa7) || |
| (ctxt->b == 0xae) || (ctxt->b == 0xaf)) |
| && (((ctxt->rep_prefix == REPE_PREFIX) && |
| ((ctxt->eflags & EFLG_ZF) == 0)) |
| || ((ctxt->rep_prefix == REPNE_PREFIX) && |
| ((ctxt->eflags & EFLG_ZF) == EFLG_ZF)))) |
| return true; |
| |
| return false; |
| } |
| |
| static int flush_pending_x87_faults(struct x86_emulate_ctxt *ctxt) |
| { |
| bool fault = false; |
| |
| ctxt->ops->get_fpu(ctxt); |
| asm volatile("1: fwait \n\t" |
| "2: \n\t" |
| ".pushsection .fixup,\"ax\" \n\t" |
| "3: \n\t" |
| "movb $1, %[fault] \n\t" |
| "jmp 2b \n\t" |
| ".popsection \n\t" |
| _ASM_EXTABLE(1b, 3b) |
| : [fault]"+qm"(fault)); |
| ctxt->ops->put_fpu(ctxt); |
| |
| if (unlikely(fault)) |
| return emulate_exception(ctxt, MF_VECTOR, 0, false); |
| |
| return X86EMUL_CONTINUE; |
| } |
| |
| static void fetch_possible_mmx_operand(struct x86_emulate_ctxt *ctxt, |
| struct operand *op) |
| { |
| if (op->type == OP_MM) |
| read_mmx_reg(ctxt, &op->mm_val, op->addr.mm); |
| } |
| |
| static int fastop(struct x86_emulate_ctxt *ctxt, void (*fop)(struct fastop *)) |
| { |
| ulong flags = (ctxt->eflags & EFLAGS_MASK) | X86_EFLAGS_IF; |
| if (!(ctxt->d & ByteOp)) |
| fop += __ffs(ctxt->dst.bytes) * FASTOP_SIZE; |
| asm("push %[flags]; popf; call *%[fastop]; pushf; pop %[flags]\n" |
| : "+a"(ctxt->dst.val), "+d"(ctxt->src.val), [flags]"+D"(flags), |
| [fastop]"+S"(fop) |
| : "c"(ctxt->src2.val)); |
| ctxt->eflags = (ctxt->eflags & ~EFLAGS_MASK) | (flags & EFLAGS_MASK); |
| if (!fop) /* exception is returned in fop variable */ |
| return emulate_de(ctxt); |
| return X86EMUL_CONTINUE; |
| } |
| |
| void init_decode_cache(struct x86_emulate_ctxt *ctxt) |
| { |
| memset(&ctxt->rip_relative, 0, |
| (void *)&ctxt->modrm - (void *)&ctxt->rip_relative); |
| |
| ctxt->io_read.pos = 0; |
| ctxt->io_read.end = 0; |
| ctxt->mem_read.end = 0; |
| } |
| |
| int x86_emulate_insn(struct x86_emulate_ctxt *ctxt) |
| { |
| const struct x86_emulate_ops *ops = ctxt->ops; |
| int rc = X86EMUL_CONTINUE; |
| int saved_dst_type = ctxt->dst.type; |
| |
| ctxt->mem_read.pos = 0; |
| |
| /* LOCK prefix is allowed only with some instructions */ |
| if (ctxt->lock_prefix && (!(ctxt->d & Lock) || ctxt->dst.type != OP_MEM)) { |
| rc = emulate_ud(ctxt); |
| goto done; |
| } |
| |
| if ((ctxt->d & SrcMask) == SrcMemFAddr && ctxt->src.type != OP_MEM) { |
| rc = emulate_ud(ctxt); |
| goto done; |
| } |
| |
| if (unlikely(ctxt->d & |
| (No64|Undefined|Sse|Mmx|Intercept|CheckPerm|Priv|Prot|String))) { |
| if ((ctxt->mode == X86EMUL_MODE_PROT64 && (ctxt->d & No64)) || |
| (ctxt->d & Undefined)) { |
| rc = emulate_ud(ctxt); |
| goto done; |
| } |
| |
| if (((ctxt->d & (Sse|Mmx)) && ((ops->get_cr(ctxt, 0) & X86_CR0_EM))) |
| || ((ctxt->d & Sse) && !(ops->get_cr(ctxt, 4) & X86_CR4_OSFXSR))) { |
| rc = emulate_ud(ctxt); |
| goto done; |
| } |
| |
| if ((ctxt->d & (Sse|Mmx)) && (ops->get_cr(ctxt, 0) & X86_CR0_TS)) { |
| rc = emulate_nm(ctxt); |
| goto done; |
| } |
| |
| if (ctxt->d & Mmx) { |
| rc = flush_pending_x87_faults(ctxt); |
| if (rc != X86EMUL_CONTINUE) |
| goto done; |
| /* |
| * Now that we know the fpu is exception safe, we can fetch |
| * operands from it. |
| */ |
| fetch_possible_mmx_operand(ctxt, &ctxt->src); |
| fetch_possible_mmx_operand(ctxt, &ctxt->src2); |
| if (!(ctxt->d & Mov)) |
| fetch_possible_mmx_operand(ctxt, &ctxt->dst); |
| } |
| |
| if (unlikely(ctxt->guest_mode) && (ctxt->d & Intercept)) { |
| rc = emulator_check_intercept(ctxt, ctxt->intercept, |
| X86_ICPT_PRE_EXCEPT); |
| if (rc != X86EMUL_CONTINUE) |
| goto done; |
| } |
| |
| /* Instruction can only be executed in protected mode */ |
| if ((ctxt->d & Prot) && ctxt->mode < X86EMUL_MODE_PROT16) { |
| rc = emulate_ud(ctxt); |
| goto done; |
| } |
| |
| /* Privileged instruction can be executed only in CPL=0 */ |
| if ((ctxt->d & Priv) && ops->cpl(ctxt)) { |
| if (ctxt->d & PrivUD) |
| rc = emulate_ud(ctxt); |
| else |
| rc = emulate_gp(ctxt, 0); |
| goto done; |
| } |
| |
| /* Do instruction specific permission checks */ |
| if (ctxt->d & CheckPerm) { |
| rc = ctxt->check_perm(ctxt); |
| if (rc != X86EMUL_CONTINUE) |
| goto done; |
| } |
| |
| if (unlikely(ctxt->guest_mode) && (ctxt->d & Intercept)) { |
| rc = emulator_check_intercept(ctxt, ctxt->intercept, |
| X86_ICPT_POST_EXCEPT); |
| if (rc != X86EMUL_CONTINUE) |
| goto done; |
| } |
| |
| if (ctxt->rep_prefix && (ctxt->d & String)) { |
| /* All REP prefixes have the same first termination condition */ |
| if (address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) == 0) { |
| ctxt->eip = ctxt->_eip; |
| ctxt->eflags &= ~EFLG_RF; |
| goto done; |
| } |
| } |
| } |
| |
| if ((ctxt->src.type == OP_MEM) && !(ctxt->d & NoAccess)) { |
| rc = segmented_read(ctxt, ctxt->src.addr.mem, |
| ctxt->src.valptr, ctxt->src.bytes); |
| if (rc != X86EMUL_CONTINUE) |
| goto done; |
| ctxt->src.orig_val64 = ctxt->src.val64; |
| } |
| |
| if (ctxt->src2.type == OP_MEM) { |
| rc = segmented_read(ctxt, ctxt->src2.addr.mem, |
| &ctxt->src2.val, ctxt->src2.bytes); |
| if (rc != X86EMUL_CONTINUE) |
| goto done; |
| } |
| |
| if ((ctxt->d & DstMask) == ImplicitOps) |
| goto special_insn; |
| |
| |
| if ((ctxt->dst.type == OP_MEM) && !(ctxt->d & Mov)) { |
| /* optimisation - avoid slow emulated read if Mov */ |
| rc = segmented_read(ctxt, ctxt->dst.addr.mem, |
| &ctxt->dst.val, ctxt->dst.bytes); |
| if (rc != X86EMUL_CONTINUE) |
| goto done; |
| } |
| ctxt->dst.orig_val = ctxt->dst.val; |
| |
| special_insn: |
| |
| if (unlikely(ctxt->guest_mode) && (ctxt->d & Intercept)) { |
| rc = emulator_check_intercept(ctxt, ctxt->intercept, |
| X86_ICPT_POST_MEMACCESS); |
| if (rc != X86EMUL_CONTINUE) |
| goto done; |
| } |
| |
| if (ctxt->rep_prefix && (ctxt->d & String)) |
| ctxt->eflags |= EFLG_RF; |
| else |
| ctxt->eflags &= ~EFLG_RF; |
| |
| if (ctxt->execute) { |
| if (ctxt->d & Fastop) { |
| void (*fop)(struct fastop *) = (void *)ctxt->execute; |
| rc = fastop(ctxt, fop); |
| if (rc != X86EMUL_CONTINUE) |
| goto done; |
| goto writeback; |
| } |
| rc = ctxt->execute(ctxt); |
| if (rc != X86EMUL_CONTINUE) |
| goto done; |
| goto writeback; |
| } |
| |
| if (ctxt->opcode_len == 2) |
| goto twobyte_insn; |
| else if (ctxt->opcode_len == 3) |
| goto threebyte_insn; |
| |
| switch (ctxt->b) { |
| case 0x63: /* movsxd */ |
| if (ctxt->mode != X86EMUL_MODE_PROT64) |
| goto cannot_emulate; |
| ctxt->dst.val = (s32) ctxt->src.val; |
| break; |
| case 0x70 ... 0x7f: /* jcc (short) */ |
| if (test_cc(ctxt->b, ctxt->eflags)) |
| rc = jmp_rel(ctxt, ctxt->src.val); |
| break; |
| case 0x8d: /* lea r16/r32, m */ |
| ctxt->dst.val = ctxt->src.addr.mem.ea; |
| break; |
| case 0x90 ... 0x97: /* nop / xchg reg, rax */ |
| if (ctxt->dst.addr.reg == reg_rmw(ctxt, VCPU_REGS_RAX)) |
| ctxt->dst.type = OP_NONE; |
| else |
| rc = em_xchg(ctxt); |
| break; |
| case 0x98: /* cbw/cwde/cdqe */ |
| switch (ctxt->op_bytes) { |
| case 2: ctxt->dst.val = (s8)ctxt->dst.val; break; |
| case 4: ctxt->dst.val = (s16)ctxt->dst.val; break; |
| case 8: ctxt->dst.val = (s32)ctxt->dst.val; break; |
| } |
| break; |
| case 0xcc: /* int3 */ |
| rc = emulate_int(ctxt, 3); |
| break; |
| case 0xcd: /* int n */ |
| rc = emulate_int(ctxt, ctxt->src.val); |
| break; |
| case 0xce: /* into */ |
| if (ctxt->eflags & EFLG_OF) |
| rc = emulate_int(ctxt, 4); |
| break; |
| case 0xe9: /* jmp rel */ |
| case 0xeb: /* jmp rel short */ |
| rc = jmp_rel(ctxt, ctxt->src.val); |
| ctxt->dst.type = OP_NONE; /* Disable writeback. */ |
| break; |
| case 0xf4: /* hlt */ |
| ctxt->ops->halt(ctxt); |
| break; |
| case 0xf5: /* cmc */ |
| /* complement carry flag from eflags reg */ |
| ctxt->eflags ^= EFLG_CF; |
| break; |
| case 0xf8: /* clc */ |
| ctxt->eflags &= ~EFLG_CF; |
| break; |
| case 0xf9: /* stc */ |
| ctxt->eflags |= EFLG_CF; |
| break; |
| case 0xfc: /* cld */ |
| ctxt->eflags &= ~EFLG_DF; |
| break; |
| case 0xfd: /* std */ |
| ctxt->eflags |= EFLG_DF; |
| break; |
| default: |
| goto cannot_emulate; |
| } |
| |
| if (rc != X86EMUL_CONTINUE) |
| goto done; |
| |
| writeback: |
| if (ctxt->d & SrcWrite) { |
| BUG_ON(ctxt->src.type == OP_MEM || ctxt->src.type == OP_MEM_STR); |
| rc = writeback(ctxt, &ctxt->src); |
| if (rc != X86EMUL_CONTINUE) |
| goto done; |
| } |
| if (!(ctxt->d & NoWrite)) { |
| rc = writeback(ctxt, &ctxt->dst); |
| if (rc != X86EMUL_CONTINUE) |
| goto done; |
| } |
| |
| /* |
| * restore dst type in case the decoding will be reused |
| * (happens for string instruction ) |
| */ |
| ctxt->dst.type = saved_dst_type; |
| |
| if ((ctxt->d & SrcMask) == SrcSI) |
| string_addr_inc(ctxt, VCPU_REGS_RSI, &ctxt->src); |
| |
| if ((ctxt->d & DstMask) == DstDI) |
| string_addr_inc(ctxt, VCPU_REGS_RDI, &ctxt->dst); |
| |
| if (ctxt->rep_prefix && (ctxt->d & String)) { |
| unsigned int count; |
| struct read_cache *r = &ctxt->io_read; |
| if ((ctxt->d & SrcMask) == SrcSI) |
| count = ctxt->src.count; |
| else |
| count = ctxt->dst.count; |
| register_address_increment(ctxt, VCPU_REGS_RCX, -count); |
| |
| if (!string_insn_completed(ctxt)) { |
| /* |
| * Re-enter guest when pio read ahead buffer is empty |
| * or, if it is not used, after each 1024 iteration. |
| */ |
| if ((r->end != 0 || reg_read(ctxt, VCPU_REGS_RCX) & 0x3ff) && |
| (r->end == 0 || r->end != r->pos)) { |
| /* |
| * Reset read cache. Usually happens before |
| * decode, but since instruction is restarted |
| * we have to do it here. |
| */ |
| ctxt->mem_read.end = 0; |
| writeback_registers(ctxt); |
| return EMULATION_RESTART; |
| } |
| goto done; /* skip rip writeback */ |
| } |
| ctxt->eflags &= ~EFLG_RF; |
| } |
| |
| ctxt->eip = ctxt->_eip; |
| |
| done: |
| if (rc == X86EMUL_PROPAGATE_FAULT) { |
| WARN_ON(ctxt->exception.vector > 0x1f); |
| ctxt->have_exception = true; |
| } |
| if (rc == X86EMUL_INTERCEPTED) |
| return EMULATION_INTERCEPTED; |
| |
| if (rc == X86EMUL_CONTINUE) |
| writeback_registers(ctxt); |
| |
| return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK; |
| |
| twobyte_insn: |
| switch (ctxt->b) { |
| case 0x09: /* wbinvd */ |
| (ctxt->ops->wbinvd)(ctxt); |
| break; |
| case 0x08: /* invd */ |
| case 0x0d: /* GrpP (prefetch) */ |
| case 0x18: /* Grp16 (prefetch/nop) */ |
| case 0x1f: /* nop */ |
| break; |
| case 0x20: /* mov cr, reg */ |
| ctxt->dst.val = ops->get_cr(ctxt, ctxt->modrm_reg); |
| break; |
| case 0x21: /* mov from dr to reg */ |
| ops->get_dr(ctxt, ctxt->modrm_reg, &ctxt->dst.val); |
| break; |
| case 0x40 ... 0x4f: /* cmov */ |
| if (test_cc(ctxt->b, ctxt->eflags)) |
| ctxt->dst.val = ctxt->src.val; |
| else if (ctxt->mode != X86EMUL_MODE_PROT64 || |
| ctxt->op_bytes != 4) |
| ctxt->dst.type = OP_NONE; /* no writeback */ |
| break; |
| case 0x80 ... 0x8f: /* jnz rel, etc*/ |
| if (test_cc(ctxt->b, ctxt->eflags)) |
| rc = jmp_rel(ctxt, ctxt->src.val); |
| break; |
| case 0x90 ... 0x9f: /* setcc r/m8 */ |
| ctxt->dst.val = test_cc(ctxt->b, ctxt->eflags); |
| break; |
| case 0xb6 ... 0xb7: /* movzx */ |
| ctxt->dst.bytes = ctxt->op_bytes; |
| ctxt->dst.val = (ctxt->src.bytes == 1) ? (u8) ctxt->src.val |
| : (u16) ctxt->src.val; |
| break; |
| case 0xbe ... 0xbf: /* movsx */ |
| ctxt->dst.bytes = ctxt->op_bytes; |
| ctxt->dst.val = (ctxt->src.bytes == 1) ? (s8) ctxt->src.val : |
| (s16) ctxt->src.val; |
| break; |
| default: |
| goto cannot_emulate; |
| } |
| |
| threebyte_insn: |
| |
| if (rc != X86EMUL_CONTINUE) |
| goto done; |
| |
| goto writeback; |
| |
| cannot_emulate: |
| return EMULATION_FAILED; |
| } |
| |
| void emulator_invalidate_register_cache(struct x86_emulate_ctxt *ctxt) |
| { |
| invalidate_registers(ctxt); |
| } |
| |
| void emulator_writeback_register_cache(struct x86_emulate_ctxt *ctxt) |
| { |
| writeback_registers(ctxt); |
| } |