Staging: brcm80211: s/uint32/u32/
Use the kernel types, don't invent your own.
Cc: Brett Rudley <brudley@broadcom.com>
Cc: Henry Ptasinski <henryp@broadcom.com>
Cc: Nohee Ko <noheek@broadcom.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
diff --git a/drivers/staging/brcm80211/util/aiutils.c b/drivers/staging/brcm80211/util/aiutils.c
index 5a020d1..c8e535c 100644
--- a/drivers/staging/brcm80211/util/aiutils.c
+++ b/drivers/staging/brcm80211/util/aiutils.c
@@ -33,10 +33,10 @@
/* EROM parsing */
-static uint32
-get_erom_ent(si_t *sih, uint32 **eromptr, uint32 mask, uint32 match)
+static u32
+get_erom_ent(si_t *sih, u32 **eromptr, u32 mask, u32 match)
{
- uint32 ent;
+ u32 ent;
uint inv = 0, nom = 0;
while (TRUE) {
@@ -68,11 +68,11 @@
return ent;
}
-static uint32
-get_asd(si_t *sih, uint32 **eromptr, uint sp, uint ad, uint st,
- uint32 *addrl, uint32 *addrh, uint32 *sizel, uint32 *sizeh)
+static u32
+get_asd(si_t *sih, u32 **eromptr, uint sp, uint ad, uint st,
+ u32 *addrl, u32 *addrh, u32 *sizel, u32 *sizeh)
{
- uint32 asd, sz, szd;
+ u32 asd, sz, szd;
asd = get_erom_ent(sih, eromptr, ER_VALID, ER_VALID);
if (((asd & ER_TAG1) != ER_ADD) ||
@@ -112,13 +112,13 @@
{
si_info_t *sii = SI_INFO(sih);
chipcregs_t *cc = (chipcregs_t *) regs;
- uint32 erombase, *eromptr, *eromlim;
+ u32 erombase, *eromptr, *eromlim;
erombase = R_REG(sii->osh, &cc->eromptr);
switch (BUSTYPE(sih->bustype)) {
case SI_BUS:
- eromptr = (uint32 *) REG_MAP(erombase, SI_CORE_SIZE);
+ eromptr = (u32 *) REG_MAP(erombase, SI_CORE_SIZE);
break;
case PCI_BUS:
@@ -134,7 +134,7 @@
case SPI_BUS:
case SDIO_BUS:
#endif /* BCMSDIO */
- eromptr = (uint32 *) (uintptr) erombase;
+ eromptr = (u32 *) (uintptr) erombase;
break;
default:
@@ -143,13 +143,13 @@
ASSERT(0);
return;
}
- eromlim = eromptr + (ER_REMAPCONTROL / sizeof(uint32));
+ eromlim = eromptr + (ER_REMAPCONTROL / sizeof(u32));
SI_VMSG(("ai_scan: regs = 0x%p, erombase = 0x%08x, eromptr = 0x%p, eromlim = 0x%p\n", regs, erombase, eromptr, eromlim));
while (eromptr < eromlim) {
- uint32 cia, cib, cid, mfg, crev, nmw, nsw, nmp, nsp;
- uint32 mpd, asd, addrl, addrh, sizel, sizeh;
- uint32 *base;
+ u32 cia, cib, cid, mfg, crev, nmw, nsw, nmp, nsp;
+ u32 mpd, asd, addrl, addrh, sizel, sizeh;
+ u32 *base;
uint i, j, idx;
bool br;
@@ -317,8 +317,8 @@
void *ai_setcoreidx(si_t *sih, uint coreidx)
{
si_info_t *sii = SI_INFO(sih);
- uint32 addr = sii->coresba[coreidx];
- uint32 wrap = sii->wrapba[coreidx];
+ u32 addr = sii->coresba[coreidx];
+ u32 wrap = sii->wrapba[coreidx];
void *regs;
if (coreidx >= sii->numcores)
@@ -381,7 +381,7 @@
}
/* Return the address of the nth address space in the current core */
-uint32 ai_addrspace(si_t *sih, uint asidx)
+u32 ai_addrspace(si_t *sih, uint asidx)
{
si_info_t *sii;
uint cidx;
@@ -400,7 +400,7 @@
}
/* Return the size of the nth address space in the current core */
-uint32 ai_addrspacesize(si_t *sih, uint asidx)
+u32 ai_addrspacesize(si_t *sih, uint asidx)
{
si_info_t *sii;
uint cidx;
@@ -437,10 +437,10 @@
{
}
-void ai_write_wrap_reg(si_t *sih, uint32 offset, uint32 val)
+void ai_write_wrap_reg(si_t *sih, u32 offset, u32 val)
{
si_info_t *sii = SI_INFO(sih);
- uint32 *w = (uint32 *) sii->curwrap;
+ u32 *w = (u32 *) sii->curwrap;
W_REG(sii->osh, w + (offset / 4), val);
return;
}
@@ -448,7 +448,7 @@
uint ai_corevendor(si_t *sih)
{
si_info_t *sii;
- uint32 cia;
+ u32 cia;
sii = SI_INFO(sih);
cia = sii->cia[sii->curidx];
@@ -458,7 +458,7 @@
uint ai_corerev(si_t *sih)
{
si_info_t *sii;
- uint32 cib;
+ u32 cib;
sii = SI_INFO(sih);
cib = sii->cib[sii->curidx];
@@ -490,7 +490,7 @@
uint ai_corereg(si_t *sih, uint coreidx, uint regoff, uint mask, uint val)
{
uint origidx = 0;
- uint32 *r = NULL;
+ u32 *r = NULL;
uint w;
uint intr_val = 0;
bool fast = FALSE;
@@ -514,7 +514,7 @@
SI_CORE_SIZE);
ASSERT(GOODREGS(sii->regs[coreidx]));
}
- r = (uint32 *) ((unsigned char *) sii->regs[coreidx] + regoff);
+ r = (u32 *) ((unsigned char *) sii->regs[coreidx] + regoff);
} else if (BUSTYPE(sih->bustype) == PCI_BUS) {
/* If pci/pcie, we can get at pci/pcie regs and on newer cores to chipc */
@@ -522,7 +522,7 @@
/* Chipc registers are mapped at 12KB */
fast = TRUE;
- r = (uint32 *) ((char *)sii->curmap +
+ r = (u32 *) ((char *)sii->curmap +
PCI_16KB0_CCREGS_OFFSET + regoff);
} else if (sii->pub.buscoreidx == coreidx) {
/* pci registers are at either in the last 2KB of an 8KB window
@@ -530,11 +530,11 @@
*/
fast = TRUE;
if (SI_FAST(sii))
- r = (uint32 *) ((char *)sii->curmap +
+ r = (u32 *) ((char *)sii->curmap +
PCI_16KB0_PCIREGS_OFFSET +
regoff);
else
- r = (uint32 *) ((char *)sii->curmap +
+ r = (u32 *) ((char *)sii->curmap +
((regoff >= SBCONFIGOFF) ?
PCI_BAR0_PCISBR_OFFSET :
PCI_BAR0_PCIREGS_OFFSET) +
@@ -549,7 +549,7 @@
origidx = si_coreidx(&sii->pub);
/* switch core */
- r = (uint32 *) ((unsigned char *) ai_setcoreidx(&sii->pub, coreidx) +
+ r = (u32 *) ((unsigned char *) ai_setcoreidx(&sii->pub, coreidx) +
regoff);
}
ASSERT(r != NULL);
@@ -574,10 +574,10 @@
return w;
}
-void ai_core_disable(si_t *sih, uint32 bits)
+void ai_core_disable(si_t *sih, u32 bits)
{
si_info_t *sii;
- volatile uint32 dummy;
+ volatile u32 dummy;
aidmp_t *ai;
sii = SI_INFO(sih);
@@ -602,11 +602,11 @@
* bits - core specific bits that are set during and after reset sequence
* resetbits - core specific bits that are set only during reset sequence
*/
-void ai_core_reset(si_t *sih, uint32 bits, uint32 resetbits)
+void ai_core_reset(si_t *sih, u32 bits, u32 resetbits)
{
si_info_t *sii;
aidmp_t *ai;
- volatile uint32 dummy;
+ volatile u32 dummy;
sii = SI_INFO(sih);
ASSERT(GOODREGS(sii->curwrap));
@@ -630,11 +630,11 @@
OSL_DELAY(1);
}
-void ai_core_cflags_wo(si_t *sih, uint32 mask, uint32 val)
+void ai_core_cflags_wo(si_t *sih, u32 mask, u32 val)
{
si_info_t *sii;
aidmp_t *ai;
- uint32 w;
+ u32 w;
sii = SI_INFO(sih);
@@ -655,11 +655,11 @@
}
}
-uint32 ai_core_cflags(si_t *sih, uint32 mask, uint32 val)
+u32 ai_core_cflags(si_t *sih, u32 mask, u32 val)
{
si_info_t *sii;
aidmp_t *ai;
- uint32 w;
+ u32 w;
sii = SI_INFO(sih);
if (BCM47162_DMP()) {
@@ -681,11 +681,11 @@
return R_REG(sii->osh, &ai->ioctrl);
}
-uint32 ai_core_sflags(si_t *sih, uint32 mask, uint32 val)
+u32 ai_core_sflags(si_t *sih, u32 mask, u32 val)
{
si_info_t *sii;
aidmp_t *ai;
- uint32 w;
+ u32 w;
sii = SI_INFO(sih);
if (BCM47162_DMP()) {
diff --git a/drivers/staging/brcm80211/util/bcmotp.c b/drivers/staging/brcm80211/util/bcmotp.c
index 5bfc0ee..2a18943 100644
--- a/drivers/staging/brcm80211/util/bcmotp.c
+++ b/drivers/staging/brcm80211/util/bcmotp.c
@@ -85,7 +85,7 @@
u16 wsize; /* Size of otp in words */
u16 rows; /* Geometry */
u16 cols; /* Geometry */
- uint32 status; /* Flag bits (lock/prog/rv).
+ u32 status; /* Flag bits (lock/prog/rv).
* (Reflected only when OTP is power cycled)
*/
u16 hwbase; /* hardware subregion offset */
@@ -189,7 +189,7 @@
{
otpinfo_t *oi = (otpinfo_t *) oh;
uint k, row, col;
- uint32 otpp, st;
+ u32 otpp, st;
row = off / oi->cols;
col = off % oi->cols;
@@ -240,7 +240,7 @@
static void BCMNMIATTACHFN(_ipxotp_init) (otpinfo_t *oi, chipcregs_t *cc)
{
uint k;
- uint32 otpp, st;
+ u32 otpp, st;
/* record word offset of General Use Region for various chipcommon revs */
if (oi->sih->ccrev == 21 || oi->sih->ccrev == 24
@@ -274,7 +274,7 @@
if ((CHIPID(oi->sih->chip) == BCM43224_CHIP_ID)
|| (CHIPID(oi->sih->chip) == BCM43225_CHIP_ID)) {
- uint32 p_bits;
+ u32 p_bits;
p_bits =
(ipxotp_otpr(oi, cc, oi->otpgu_base + OTPGU_P_OFF) &
OTPGU_P_MSK)
@@ -603,7 +603,7 @@
{
otpinfo_t *oi = (otpinfo_t *) oh;
uint k, row, col;
- uint32 otpp, st;
+ u32 otpp, st;
osl_t *osh;
osh = si_osh(oi->sih);
@@ -635,7 +635,7 @@
uint idx;
chipcregs_t *cc;
otpinfo_t *oi;
- uint32 cap = 0, clkdiv, otpdiv = 0;
+ u32 cap = 0, clkdiv, otpdiv = 0;
void *ret = NULL;
osl_t *osh;
@@ -709,7 +709,7 @@
static int hndotp_read_region(void *oh, int region, u16 *data, uint *wlen)
{
otpinfo_t *oi = (otpinfo_t *) oh;
- uint32 idx, st;
+ u32 idx, st;
chipcregs_t *cc;
int i;
@@ -740,9 +740,9 @@
{
int rc = 0;
otpinfo_t *oi = (otpinfo_t *) oh;
- uint32 base, bound, lim = 0, st;
+ u32 base, bound, lim = 0, st;
int i, chunk, gchunks, tsz = 0;
- uint32 idx;
+ u32 idx;
chipcregs_t *cc;
uint offset;
u16 *rawotp = NULL;
diff --git a/drivers/staging/brcm80211/util/bcmsrom.c b/drivers/staging/brcm80211/util/bcmsrom.c
index 73e48a6..3b3f3b1 100644
--- a/drivers/staging/brcm80211/util/bcmsrom.c
+++ b/drivers/staging/brcm80211/util/bcmsrom.c
@@ -85,7 +85,7 @@
#if defined(BCMNVRAMR)
static int otp_read_pci(osl_t *osh, si_t *sih, u16 *buf, uint bufsz);
#endif
-static u16 srom_cc_cmd(si_t *sih, osl_t *osh, void *ccregs, uint32 cmd,
+static u16 srom_cc_cmd(si_t *sih, osl_t *osh, void *ccregs, u32 cmd,
uint wordoff, u16 data);
static int initvars_table(osl_t *osh, char *start, char *end, char **vars,
@@ -388,7 +388,7 @@
u8 *cis, tup, tlen, sromrev = 1;
int i, j;
bool ag_init = FALSE;
- uint32 w32;
+ u32 w32;
uint funcid;
uint cisnum;
int32 boardnum;
@@ -1413,7 +1413,7 @@
* not in the bus cores.
*/
static u16
-srom_cc_cmd(si_t *sih, osl_t *osh, void *ccregs, uint32 cmd, uint wordoff,
+srom_cc_cmd(si_t *sih, osl_t *osh, void *ccregs, u32 cmd, uint wordoff,
u16 data)
{
chipcregs_t *cc = (chipcregs_t *) ccregs;
@@ -1708,11 +1708,11 @@
BCMATTACHFN(_initvars_srom_pci) (u8 sromrev, u16 *srom, uint off,
varbuf_t *b) {
u16 w;
- uint32 val;
+ u32 val;
const sromvar_t *srv;
uint width;
uint flags;
- uint32 sr = (1 << sromrev);
+ u32 sr = (1 << sromrev);
varbuf_append(b, "sromrev=%d", sromrev);
@@ -1786,7 +1786,7 @@
*(oncount >> 24) (offcount >> 8)
*/
else if (flags & SRFL_LEDDC) {
- uint32 w32 = (((val >> 8) & 0xff) << 24) | /* oncount */
+ u32 w32 = (((val >> 8) & 0xff) << 24) | /* oncount */
(((val & 0xff)) << 8); /* offcount */
varbuf_append(b, "leddc=%d", w32);
} else if (flags & SRFL_PRHEX)
@@ -1858,7 +1858,7 @@
uint *count) {
u16 *srom, *sromwindow;
u8 sromrev = 0;
- uint32 sr;
+ u32 sr;
varbuf_t b;
char *vp, *base = NULL;
osl_t *osh = si_osh(sih);
@@ -1922,7 +1922,7 @@
*/
if (err) {
char *value;
- uint32 val;
+ u32 val;
val = 0;
value = si_getdevpathvar(sih, "sromrev");
diff --git a/drivers/staging/brcm80211/util/bcmutils.c b/drivers/staging/brcm80211/util/bcmutils.c
index e36937a..03240ac 100644
--- a/drivers/staging/brcm80211/util/bcmutils.c
+++ b/drivers/staging/brcm80211/util/bcmutils.c
@@ -566,13 +566,13 @@
#if defined(BCMDBG)
int
-bcm_format_flags(const bcm_bit_desc_t *bd, uint32 flags, char *buf, int len)
+bcm_format_flags(const bcm_bit_desc_t *bd, u32 flags, char *buf, int len)
{
int i;
char *p = buf;
char hexstr[16];
int slen = 0, nlen = 0;
- uint32 bit;
+ u32 bit;
const char *name;
if (len < 2 || !buf)
diff --git a/drivers/staging/brcm80211/util/hnddma.c b/drivers/staging/brcm80211/util/hnddma.c
index dd6e0d9..6a6bba2 100644
--- a/drivers/staging/brcm80211/util/hnddma.c
+++ b/drivers/staging/brcm80211/util/hnddma.c
@@ -109,8 +109,8 @@
dmaaddr_t txdpa; /* Aligned physical address of descriptor ring */
dmaaddr_t txdpaorig; /* Original physical address of descriptor ring */
u16 txdalign; /* #bytes added to alloc'd mem to align txd */
- uint32 txdalloc; /* #bytes allocated for the ring */
- uint32 xmtptrbase; /* When using unaligned descriptors, the ptr register
+ u32 txdalloc; /* #bytes allocated for the ring */
+ u32 xmtptrbase; /* When using unaligned descriptors, the ptr register
* is not just an index, it needs all 13 bits to be
* an offset from the addr register.
*/
@@ -124,8 +124,8 @@
dmaaddr_t rxdpa; /* Aligned physical address of descriptor ring */
dmaaddr_t rxdpaorig; /* Original physical address of descriptor ring */
u16 rxdalign; /* #bytes added to alloc'd mem to align rxd */
- uint32 rxdalloc; /* #bytes allocated for the ring */
- uint32 rcvptrbase; /* Base for ptr reg when using unaligned descriptors */
+ u32 rxdalloc; /* #bytes allocated for the ring */
+ u32 rcvptrbase; /* Base for ptr reg when using unaligned descriptors */
/* tunables */
u16 rxbufsize; /* rx buffer size in bytes,
@@ -223,7 +223,7 @@
static void _dma_fifoloopbackenable(dma_info_t *di);
static uint _dma_ctrlflags(dma_info_t *di, uint mask, uint flags);
static u8 dma_align_sizetobits(uint size);
-static void *dma_ringalloc(osl_t *osh, uint32 boundary, uint size,
+static void *dma_ringalloc(osl_t *osh, u32 boundary, uint size,
u16 *alignbits, uint *alloced,
dmaaddr_t *descpa, osldma_t **dmah);
@@ -273,7 +273,7 @@
static bool dma64_rxenabled(dma_info_t *di);
static bool _dma64_addrext(osl_t *osh, dma64regs_t *dma64regs);
-static inline uint32 parity32(uint32 data);
+static inline u32 parity32(u32 data);
const di_fcn_t dma64proc = {
(di_detach_t) _dma_detach,
@@ -548,11 +548,11 @@
if ((di->ddoffsetlow != 0) && !di->addrext) {
if (PHYSADDRLO(di->txdpa) > SI_PCI_DMA_SZ) {
- DMA_ERROR(("%s: dma_attach: txdpa 0x%x: addrext not supported\n", di->name, (uint32) PHYSADDRLO(di->txdpa)));
+ DMA_ERROR(("%s: dma_attach: txdpa 0x%x: addrext not supported\n", di->name, (u32) PHYSADDRLO(di->txdpa)));
goto fail;
}
if (PHYSADDRLO(di->rxdpa) > SI_PCI_DMA_SZ) {
- DMA_ERROR(("%s: dma_attach: rxdpa 0x%x: addrext not supported\n", di->name, (uint32) PHYSADDRLO(di->rxdpa)));
+ DMA_ERROR(("%s: dma_attach: rxdpa 0x%x: addrext not supported\n", di->name, (u32) PHYSADDRLO(di->rxdpa)));
goto fail;
}
}
@@ -588,7 +588,7 @@
/* init the tx or rx descriptor */
static inline void
dma32_dd_upd(dma_info_t *di, dma32dd_t *ddring, dmaaddr_t pa, uint outidx,
- uint32 *flags, uint32 bufcount)
+ u32 *flags, u32 bufcount)
{
/* dma32 uses 32-bit control to fit both flags and bufcounter */
*flags = *flags | (bufcount & CTRL_BC_MASK);
@@ -599,7 +599,7 @@
W_SM(&ddring[outidx].ctrl, BUS_SWAP32(*flags));
} else {
/* address extension */
- uint32 ae;
+ u32 ae;
ASSERT(di->addrext);
ae = (PHYSADDRLO(pa) & PCI32ADDR_HIGH) >> PCI32ADDR_HIGH_SHIFT;
PHYSADDRLO(pa) &= ~PCI32ADDR_HIGH;
@@ -612,7 +612,7 @@
}
/* Check for odd number of 1's */
-static inline uint32 parity32(uint32 data)
+static inline u32 parity32(u32 data)
{
data ^= data >> 16;
data ^= data >> 8;
@@ -627,9 +627,9 @@
static inline void
dma64_dd_upd(dma_info_t *di, dma64dd_t *ddring, dmaaddr_t pa, uint outidx,
- uint32 *flags, uint32 bufcount)
+ u32 *flags, u32 bufcount)
{
- uint32 ctrl2 = bufcount & D64_CTRL2_BC_MASK;
+ u32 ctrl2 = bufcount & D64_CTRL2_BC_MASK;
/* PCI bus with big(>1G) physical address, use address extension */
#if defined(__mips__) && defined(IL_BIGENDIAN)
@@ -648,7 +648,7 @@
W_SM(&ddring[outidx].ctrl2, BUS_SWAP32(ctrl2));
} else {
/* address extension for 32-bit PCI */
- uint32 ae;
+ u32 ae;
ASSERT(di->addrext);
ae = (PHYSADDRLO(pa) & PCI32ADDR_HIGH) >> PCI32ADDR_HIGH_SHIFT;
@@ -673,7 +673,7 @@
static bool _dma32_addrext(osl_t *osh, dma32regs_t *dma32regs)
{
- uint32 w;
+ u32 w;
OR_REG(osh, &dma32regs->control, XC_AE);
w = R_REG(osh, &dma32regs->control);
@@ -751,7 +751,7 @@
static bool _dma_descriptor_align(dma_info_t *di)
{
if (DMA64_ENAB(di) && DMA64_MODE(di)) {
- uint32 addrl;
+ u32 addrl;
/* Check to see if the descriptors need to be aligned on 4K/8K or not */
if (di->d64txregs != NULL) {
@@ -827,7 +827,7 @@
}
} else {
/* DMA64 32bits address extension */
- uint32 ae;
+ u32 ae;
ASSERT(di->addrext);
ASSERT(PHYSADDRHI(pa) == 0);
@@ -865,7 +865,7 @@
(PHYSADDRLO(pa) + di->ddoffsetlow));
} else {
/* dma32 address extension */
- uint32 ae;
+ u32 ae;
ASSERT(di->addrext);
/* shift the high bit(s) from pa to ae */
@@ -941,7 +941,7 @@
DMA_TRACE(("%s: dma_rxenable\n", di->name));
if (DMA64_ENAB(di) && DMA64_MODE(di)) {
- uint32 control =
+ u32 control =
(R_REG(di->osh, &di->d64rxregs->control) & D64_RC_AE) |
D64_RC_RE;
@@ -954,7 +954,7 @@
W_REG(di->osh, &di->d64rxregs->control,
((di->rxoffset << D64_RC_RO_SHIFT) | control));
} else if (DMA32_ENAB(di)) {
- uint32 control =
+ u32 control =
(R_REG(di->osh, &di->d32rxregs->control) & RC_AE) | RC_RE;
if ((dmactrlflags & DMA_CTRL_PEN) == 0)
@@ -1065,7 +1065,7 @@
{
void *p;
u16 rxin, rxout;
- uint32 flags = 0;
+ u32 flags = 0;
uint n;
uint i;
dmaaddr_t pa;
@@ -1124,7 +1124,7 @@
/* Do a cached write instead of uncached write since DMA_MAP
* will flush the cache.
*/
- *(uint32 *) (PKTDATA(p)) = 0;
+ *(u32 *) (PKTDATA(p)) = 0;
if (DMASGLIST_ENAB)
bzero(&di->rxp_dmah[rxout], sizeof(hnddma_seg_map_t));
@@ -1335,7 +1335,7 @@
/* If trying to enable parity, check if parity is actually supported */
if (dmactrlflags & DMA_CTRL_PEN) {
- uint32 control;
+ u32 control;
if (DMA64_ENAB(di) && DMA64_MODE(di)) {
control = R_REG(di->osh, &di->d64txregs->control);
@@ -1405,20 +1405,20 @@
* descriptor ring size aligned location. This will ensure that the ring will
* not cross page boundary
*/
-static void *dma_ringalloc(osl_t *osh, uint32 boundary, uint size,
+static void *dma_ringalloc(osl_t *osh, u32 boundary, uint size,
u16 *alignbits, uint *alloced,
dmaaddr_t *descpa, osldma_t **dmah)
{
void *va;
- uint32 desc_strtaddr;
- uint32 alignbytes = 1 << *alignbits;
+ u32 desc_strtaddr;
+ u32 alignbytes = 1 << *alignbits;
va = DMA_ALLOC_CONSISTENT(osh, size, *alignbits, alloced, descpa,
dmah);
if (NULL == va)
return NULL;
- desc_strtaddr = (uint32) ROUNDUP((uintptr) va, alignbytes);
+ desc_strtaddr = (u32) ROUNDUP((uintptr) va, alignbytes);
if (((desc_strtaddr + size - 1) & boundary) != (desc_strtaddr
& boundary)) {
*alignbits = dma_align_sizetobits(size);
@@ -1433,7 +1433,7 @@
static void dma32_txinit(dma_info_t *di)
{
- uint32 control = XC_XE;
+ u32 control = XC_XE;
DMA_TRACE(("%s: dma_txinit\n", di->name));
@@ -1454,7 +1454,7 @@
static bool dma32_txenabled(dma_info_t *di)
{
- uint32 xc;
+ u32 xc;
/* If the chip is dead, it is not enabled :-) */
xc = R_REG(di->osh, &di->d32txregs->control);
@@ -1581,7 +1581,7 @@
static bool dma32_txreset(dma_info_t *di)
{
- uint32 status;
+ u32 status;
if (di->ntxd == 0)
return TRUE;
@@ -1617,7 +1617,7 @@
static bool dma32_rxreset(dma_info_t *di)
{
- uint32 status;
+ u32 status;
if (di->nrxd == 0)
return TRUE;
@@ -1632,7 +1632,7 @@
static bool dma32_rxenabled(dma_info_t *di)
{
- uint32 rc;
+ u32 rc;
rc = R_REG(di->osh, &di->d32rxregs->control);
return (rc != 0xffffffff) && (rc & RC_RE);
@@ -1667,7 +1667,7 @@
unsigned char *data;
uint len;
u16 txout;
- uint32 flags = 0;
+ u32 flags = 0;
dmaaddr_t pa;
DMA_TRACE(("%s: dma_txfast\n", di->name));
@@ -1922,7 +1922,7 @@
uint nactive;
uint rot;
u16 old, new;
- uint32 w;
+ u32 w;
u16 first, last;
ASSERT(dma32_txsuspendedidle(di));
@@ -1988,7 +1988,7 @@
static void dma64_txinit(dma_info_t *di)
{
- uint32 control = D64_XC_XE;
+ u32 control = D64_XC_XE;
DMA_TRACE(("%s: dma_txinit\n", di->name));
@@ -2020,7 +2020,7 @@
static bool dma64_txenabled(dma_info_t *di)
{
- uint32 xc;
+ u32 xc;
/* If the chip is dead, it is not enabled :-) */
xc = R_REG(di->osh, &di->d64txregs->control);
@@ -2146,7 +2146,7 @@
static bool dma64_txreset(dma_info_t *di)
{
- uint32 status;
+ u32 status;
if (di->ntxd == 0)
return TRUE;
@@ -2182,7 +2182,7 @@
static bool dma64_rxreset(dma_info_t *di)
{
- uint32 status;
+ u32 status;
if (di->nrxd == 0)
return TRUE;
@@ -2197,7 +2197,7 @@
static bool dma64_rxenabled(dma_info_t *di)
{
- uint32 rc;
+ u32 rc;
rc = R_REG(di->osh, &di->d64rxregs->control);
return (rc != 0xffffffff) && (rc & D64_RC_RE);
@@ -2227,7 +2227,7 @@
{
void *va;
bool idle;
- uint32 cd_offset;
+ u32 cd_offset;
if (direction == DMA_TX) {
cd_offset =
@@ -2261,7 +2261,7 @@
static int dma64_txunframed(dma_info_t *di, void *buf, uint len, bool commit)
{
u16 txout;
- uint32 flags = 0;
+ u32 flags = 0;
dmaaddr_t pa; /* phys addr */
txout = di->txout;
@@ -2318,7 +2318,7 @@
unsigned char *data;
uint len;
u16 txout;
- uint32 flags = 0;
+ u32 flags = 0;
dmaaddr_t pa;
DMA_TRACE(("%s: dma_txfast\n", di->name));
@@ -2577,7 +2577,7 @@
static bool _dma64_addrext(osl_t *osh, dma64regs_t * dma64regs)
{
- uint32 w;
+ u32 w;
OR_REG(osh, &dma64regs->control, D64_XC_AE);
w = R_REG(osh, &dma64regs->control);
AND_REG(osh, &dma64regs->control, ~D64_XC_AE);
@@ -2593,7 +2593,7 @@
uint nactive;
uint rot;
u16 old, new;
- uint32 w;
+ u32 w;
u16 first, last;
ASSERT(dma64_txsuspendedidle(di));
diff --git a/drivers/staging/brcm80211/util/hndpmu.c b/drivers/staging/brcm80211/util/hndpmu.c
index 4ba758a..1e954c7 100644
--- a/drivers/staging/brcm80211/util/hndpmu.c
+++ b/drivers/staging/brcm80211/util/hndpmu.c
@@ -43,20 +43,20 @@
/* PLL controls/clocks */
static void si_pmu1_pllinit0(si_t *sih, osl_t *osh, chipcregs_t *cc,
- uint32 xtal);
-static uint32 si_pmu1_cpuclk0(si_t *sih, osl_t *osh, chipcregs_t *cc);
-static uint32 si_pmu1_alpclk0(si_t *sih, osl_t *osh, chipcregs_t *cc);
+ u32 xtal);
+static u32 si_pmu1_cpuclk0(si_t *sih, osl_t *osh, chipcregs_t *cc);
+static u32 si_pmu1_alpclk0(si_t *sih, osl_t *osh, chipcregs_t *cc);
/* PMU resources */
static bool si_pmu_res_depfltr_bb(si_t *sih);
static bool si_pmu_res_depfltr_ncb(si_t *sih);
static bool si_pmu_res_depfltr_paldo(si_t *sih);
static bool si_pmu_res_depfltr_npaldo(si_t *sih);
-static uint32 si_pmu_res_deps(si_t *sih, osl_t *osh, chipcregs_t *cc,
- uint32 rsrcs, bool all);
+static u32 si_pmu_res_deps(si_t *sih, osl_t *osh, chipcregs_t *cc,
+ u32 rsrcs, bool all);
static uint si_pmu_res_uptime(si_t *sih, osl_t *osh, chipcregs_t *cc,
u8 rsrc);
-static void si_pmu_res_masks(si_t *sih, uint32 * pmin, uint32 * pmax);
+static void si_pmu_res_masks(si_t *sih, u32 * pmin, u32 * pmax);
static void si_pmu_spuravoid_pllupdate(si_t *sih, chipcregs_t *cc,
osl_t *osh, u8 spuravoid);
@@ -69,7 +69,7 @@
#define FVCO_960 960000 /* 960MHz */
/* Read/write a chipcontrol reg */
-uint32 si_pmu_chipcontrol(si_t *sih, uint reg, uint32 mask, uint32 val)
+u32 si_pmu_chipcontrol(si_t *sih, uint reg, u32 mask, u32 val)
{
si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, chipcontrol_addr), ~0,
reg);
@@ -78,7 +78,7 @@
}
/* Read/write a regcontrol reg */
-uint32 si_pmu_regcontrol(si_t *sih, uint reg, uint32 mask, uint32 val)
+u32 si_pmu_regcontrol(si_t *sih, uint reg, u32 mask, u32 val)
{
si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, regcontrol_addr), ~0,
reg);
@@ -87,7 +87,7 @@
}
/* Read/write a pllcontrol reg */
-uint32 si_pmu_pllcontrol(si_t *sih, uint reg, uint32 mask, uint32 val)
+u32 si_pmu_pllcontrol(si_t *sih, uint reg, u32 mask, u32 val)
{
si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, pllcontrol_addr), ~0,
reg);
@@ -117,10 +117,10 @@
ASSERT(cc != NULL);
W_REG(osh, &cc->regcontrol_addr, 0x01);
- W_REG(osh, &cc->regcontrol_data, (uint32) (bb_voltage & 0x1f) << 22);
+ W_REG(osh, &cc->regcontrol_data, (u32) (bb_voltage & 0x1f) << 22);
W_REG(osh, &cc->regcontrol_addr, 0x00);
- W_REG(osh, &cc->regcontrol_data, (uint32) (rf_voltage & 0x1f) << 14);
+ W_REG(osh, &cc->regcontrol_data, (u32) (rf_voltage & 0x1f) << 14);
/* Return to original core */
si_setcoreidx(sih, origidx);
@@ -218,7 +218,7 @@
if (ISSIM_ENAB(sih))
delay = 70;
else {
- uint32 ilp = si_ilp_clock(sih);
+ u32 ilp = si_ilp_clock(sih);
delay =
(si_pmu_res_uptime(sih, osh, cc, RES4329_HT_AVAIL) +
D11SCC_SLOW2FAST_TRANSITION) * ((1000000 + ilp -
@@ -233,7 +233,7 @@
if (ISSIM_ENAB(sih))
delay = 70;
else {
- uint32 ilp = si_ilp_clock(sih);
+ u32 ilp = si_ilp_clock(sih);
delay =
(si_pmu_res_uptime(sih, osh, cc, RES4336_HT_AVAIL) +
D11SCC_SLOW2FAST_TRANSITION) * ((1000000 + ilp -
@@ -245,7 +245,7 @@
if (ISSIM_ENAB(sih))
delay = 70;
else {
- uint32 ilp = si_ilp_clock(sih);
+ u32 ilp = si_ilp_clock(sih);
delay =
(si_pmu_res_uptime(sih, osh, cc, RES4330_HT_AVAIL) +
D11SCC_SLOW2FAST_TRANSITION) * ((1000000 + ilp -
@@ -262,11 +262,11 @@
return (u16) delay;
}
-uint32 BCMATTACHFN(si_pmu_force_ilp) (si_t *sih, osl_t *osh, bool force)
+u32 BCMATTACHFN(si_pmu_force_ilp) (si_t *sih, osl_t *osh, bool force)
{
chipcregs_t *cc;
uint origidx;
- uint32 oldpmucontrol;
+ u32 oldpmucontrol;
ASSERT(sih->cccaps & CC_CAP_PMU);
@@ -297,9 +297,9 @@
/* Change resource dependancies masks */
typedef struct {
- uint32 res_mask; /* resources (chip specific) */
+ u32 res_mask; /* resources (chip specific) */
s8 action; /* action */
- uint32 depend_mask; /* changes to the dependancies mask */
+ u32 depend_mask; /* changes to the dependancies mask */
bool(*filter) (si_t *sih); /* action is taken when filter is NULL or return TRUE */
} pmu_res_depend_t;
@@ -592,9 +592,9 @@
sih->boardtype == BCM94325BGABU_BOARD)
/* Determine min/max rsrc masks. Value 0 leaves hardware at default. */
-static void si_pmu_res_masks(si_t *sih, uint32 * pmin, uint32 * pmax)
+static void si_pmu_res_masks(si_t *sih, u32 * pmin, u32 * pmax)
{
- uint32 min_mask = 0, max_mask = 0;
+ u32 min_mask = 0, max_mask = 0;
uint rsrcs;
char *val;
@@ -666,13 +666,13 @@
val = getvar(NULL, "rmin");
if (val != NULL) {
PMU_MSG(("Applying rmin=%s to min_mask\n", val));
- min_mask = (uint32) simple_strtoul(val, NULL, 0);
+ min_mask = (u32) simple_strtoul(val, NULL, 0);
}
/* Apply nvram override to max mask */
val = getvar(NULL, "rmax");
if (val != NULL) {
PMU_MSG(("Applying rmax=%s to max_mask\n", val));
- max_mask = (uint32) simple_strtoul(val, NULL, 0);
+ max_mask = (u32) simple_strtoul(val, NULL, 0);
}
*pmin = min_mask;
@@ -688,7 +688,7 @@
uint pmu_res_updown_table_sz = 0;
const pmu_res_depend_t *pmu_res_depend_table = NULL;
uint pmu_res_depend_table_sz = 0;
- uint32 min_mask = 0, max_mask = 0;
+ u32 min_mask = 0, max_mask = 0;
char name[8], *val;
uint i, rsrcs;
@@ -788,9 +788,9 @@
continue;
PMU_MSG(("Applying %s=%s to rsrc %d res_updn_timer\n", name,
val, i));
- W_REG(osh, &cc->res_table_sel, (uint32) i);
+ W_REG(osh, &cc->res_table_sel, (u32) i);
W_REG(osh, &cc->res_updn_timer,
- (uint32) simple_strtoul(val, NULL, 0));
+ (u32) simple_strtoul(val, NULL, 0));
}
/* Program resource dependencies table */
@@ -839,9 +839,9 @@
continue;
PMU_MSG(("Applying %s=%s to rsrc %d res_dep_mask\n", name, val,
i));
- W_REG(osh, &cc->res_table_sel, (uint32) i);
+ W_REG(osh, &cc->res_table_sel, (u32) i);
W_REG(osh, &cc->res_dep_mask,
- (uint32) simple_strtoul(val, NULL, 0));
+ (u32) simple_strtoul(val, NULL, 0));
}
/* Determine min/max rsrc masks */
@@ -875,7 +875,7 @@
u16 freq;
u8 xf;
u8 wbint;
- uint32 wbfrac;
+ u32 wbfrac;
} pmu0_xtaltab0_t;
/* the following table is based on 880Mhz fvco */
@@ -907,7 +907,7 @@
u8 p1div;
u8 p2div;
u8 ndiv_int;
- uint32 ndiv_frac;
+ u32 ndiv_frac;
} pmu1_xtaltab0_t;
static const pmu1_xtaltab0_t BCMINITDATA(pmu1_xtaltab0_880_4329)[] = {
@@ -1152,7 +1152,7 @@
}
/* select default pll fvco for each chip */
-static uint32 BCMINITFN(si_pmu1_pllfvco0) (si_t *sih)
+static u32 BCMINITFN(si_pmu1_pllfvco0) (si_t *sih)
{
#ifdef BCMDBG
char chn[8];
@@ -1180,11 +1180,11 @@
}
/* query alp/xtal clock frequency */
-static uint32
+static u32
BCMINITFN(si_pmu1_alpclk0) (si_t *sih, osl_t *osh, chipcregs_t *cc)
{
const pmu1_xtaltab0_t *xt;
- uint32 xf;
+ u32 xf;
/* Find the frequency in the table */
xf = (R_REG(osh, &cc->pmucontrol) & PCTL_XTALFREQ_MASK) >>
@@ -1208,10 +1208,10 @@
*/
static void
BCMATTACHFN(si_pmu1_pllinit0) (si_t *sih, osl_t *osh, chipcregs_t *cc,
- uint32 xtal) {
+ u32 xtal) {
const pmu1_xtaltab0_t *xt;
- uint32 tmp;
- uint32 buf_strength = 0;
+ u32 tmp;
+ u32 buf_strength = 0;
u8 ndiv_mode = 1;
/* Use h/w default PLL config */
@@ -1451,15 +1451,15 @@
}
/* query the CPU clock frequency */
-static uint32
+static u32
BCMINITFN(si_pmu1_cpuclk0) (si_t *sih, osl_t *osh, chipcregs_t *cc)
{
- uint32 tmp, m1div;
+ u32 tmp, m1div;
#ifdef BCMDBG
- uint32 ndiv_int, ndiv_frac, p2div, p1div, fvco;
- uint32 fref;
+ u32 ndiv_int, ndiv_frac, p2div, p1div, fvco;
+ u32 fref;
#endif
- uint32 FVCO = si_pmu1_pllfvco0(sih);
+ u32 FVCO = si_pmu1_pllfvco0(sih);
/* Read m1div from pllcontrol[1] */
W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL1);
@@ -1559,11 +1559,11 @@
}
/* query alp/xtal clock frequency */
-uint32 BCMINITFN(si_pmu_alp_clock) (si_t *sih, osl_t *osh)
+u32 BCMINITFN(si_pmu_alp_clock) (si_t *sih, osl_t *osh)
{
chipcregs_t *cc;
uint origidx;
- uint32 clock = ALP_CLOCK;
+ u32 clock = ALP_CLOCK;
#ifdef BCMDBG
char chn[8];
#endif
@@ -1619,10 +1619,10 @@
/* Find the output of the "m" pll divider given pll controls that start with
* pllreg "pll0" i.e. 12 for main 6 for phy, 0 for misc.
*/
-static uint32
+static u32
BCMINITFN(si_pmu5_clock) (si_t *sih, osl_t *osh, chipcregs_t *cc, uint pll0,
uint m) {
- uint32 tmp, div, ndiv, p1, p2, fc;
+ u32 tmp, div, ndiv, p1, p2, fc;
if ((pll0 & 3) || (pll0 > PMU4716_MAINPLL_PLL0)) {
PMU_ERROR(("%s: Bad pll0: %d\n", __func__, pll0));
@@ -1673,11 +1673,11 @@
/* For designs that feed the same clock to both backplane
* and CPU just return the CPU clock speed.
*/
-uint32 BCMINITFN(si_pmu_si_clock) (si_t *sih, osl_t *osh)
+u32 BCMINITFN(si_pmu_si_clock) (si_t *sih, osl_t *osh)
{
chipcregs_t *cc;
uint origidx;
- uint32 clock = HT_CLOCK;
+ u32 clock = HT_CLOCK;
#ifdef BCMDBG
char chn[8];
#endif
@@ -1752,11 +1752,11 @@
}
/* query CPU clock frequency */
-uint32 BCMINITFN(si_pmu_cpu_clock) (si_t *sih, osl_t *osh)
+u32 BCMINITFN(si_pmu_cpu_clock) (si_t *sih, osl_t *osh)
{
chipcregs_t *cc;
uint origidx;
- uint32 clock;
+ u32 clock;
ASSERT(sih->cccaps & CC_CAP_PMU);
@@ -1796,11 +1796,11 @@
}
/* query memory clock frequency */
-uint32 BCMINITFN(si_pmu_mem_clock) (si_t *sih, osl_t *osh)
+u32 BCMINITFN(si_pmu_mem_clock) (si_t *sih, osl_t *osh)
{
chipcregs_t *cc;
uint origidx;
- uint32 clock;
+ u32 clock;
ASSERT(sih->cccaps & CC_CAP_PMU);
@@ -1843,16 +1843,16 @@
/* Measure ILP clock frequency */
#define ILP_CALC_DUR 10 /* ms, make sure 1000 can be divided by it. */
-static uint32 ilpcycles_per_sec;
+static u32 ilpcycles_per_sec;
-uint32 BCMINITFN(si_pmu_ilp_clock) (si_t *sih, osl_t *osh)
+u32 BCMINITFN(si_pmu_ilp_clock) (si_t *sih, osl_t *osh)
{
if (ISSIM_ENAB(sih))
return ILP_CLOCK;
if (ilpcycles_per_sec == 0) {
- uint32 start, end, delta;
- uint32 origidx = si_coreidx(sih);
+ u32 start, end, delta;
+ u32 origidx = si_coreidx(sih);
chipcregs_t *cc = si_setcoreidx(sih, SI_CC_IDX);
ASSERT(cc != NULL);
start = R_REG(osh, &cc->pmutimer);
@@ -1910,12 +1910,12 @@
void
BCMINITFN(si_sdiod_drive_strength_init) (si_t *sih, osl_t *osh,
- uint32 drivestrength) {
+ u32 drivestrength) {
chipcregs_t *cc;
uint origidx, intr_val = 0;
sdiod_drive_str_t *str_tab = NULL;
- uint32 str_mask = 0;
- uint32 str_shift = 0;
+ u32 str_mask = 0;
+ u32 str_shift = 0;
#ifdef BCMDBG
char chn[8];
#endif
@@ -1953,8 +1953,8 @@
}
if (str_tab != NULL) {
- uint32 drivestrength_sel = 0;
- uint32 cc_data_temp;
+ u32 drivestrength_sel = 0;
+ u32 cc_data_temp;
int i;
for (i = 0; str_tab[i].strength != 0; i++) {
@@ -2014,9 +2014,9 @@
static uint
BCMINITFN(si_pmu_res_uptime) (si_t *sih, osl_t *osh, chipcregs_t *cc,
u8 rsrc) {
- uint32 deps;
+ u32 deps;
uint up, i, dup, dmax;
- uint32 min_mask = 0, max_mask = 0;
+ u32 min_mask = 0, max_mask = 0;
/* uptime of resource 'rsrc' */
W_REG(osh, &cc->res_table_sel, rsrc);
@@ -2048,12 +2048,12 @@
}
/* Return dependancies (direct or all/indirect) for the given resources */
-static uint32
-si_pmu_res_deps(si_t *sih, osl_t *osh, chipcregs_t *cc, uint32 rsrcs,
+static u32
+si_pmu_res_deps(si_t *sih, osl_t *osh, chipcregs_t *cc, u32 rsrcs,
bool all)
{
- uint32 deps = 0;
- uint32 i;
+ u32 deps = 0;
+ u32 i;
for (i = 0; i <= PMURES_MAX_RESNUM; i++) {
if (!(rsrcs & PMURES_BIT(i)))
@@ -2073,7 +2073,7 @@
{
chipcregs_t *cc;
uint origidx;
- uint32 rsrcs = 0; /* rsrcs to turn on/off OTP power */
+ u32 rsrcs = 0; /* rsrcs to turn on/off OTP power */
ASSERT(sih->cccaps & CC_CAP_PMU);
@@ -2106,11 +2106,11 @@
}
if (rsrcs != 0) {
- uint32 otps;
+ u32 otps;
/* Figure out the dependancies (exclude min_res_mask) */
- uint32 deps = si_pmu_res_deps(sih, osh, cc, rsrcs, TRUE);
- uint32 min_mask = 0, max_mask = 0;
+ u32 deps = si_pmu_res_deps(sih, osh, cc, rsrcs, TRUE);
+ u32 min_mask = 0, max_mask = 0;
si_pmu_res_masks(sih, &min_mask, &max_mask);
deps &= ~min_mask;
/* Turn on/off the power */
@@ -2154,7 +2154,7 @@
switch (CHIPID(sih->chip)) {
case BCM4329_CHIP_ID:{
u8 rcal_code;
- uint32 val;
+ u32 val;
/* Kick RCal */
W_REG(osh, &cc->chipcontrol_addr, 1);
@@ -2182,12 +2182,12 @@
val =
R_REG(osh,
&cc->
- regcontrol_data) & ~((uint32) 0x07 << 29);
- val |= (uint32) (rcal_code & 0x07) << 29;
+ regcontrol_data) & ~((u32) 0x07 << 29);
+ val |= (u32) (rcal_code & 0x07) << 29;
W_REG(osh, &cc->regcontrol_data, val);
W_REG(osh, &cc->regcontrol_addr, 1);
- val = R_REG(osh, &cc->regcontrol_data) & ~(uint32) 0x01;
- val |= (uint32) ((rcal_code >> 3) & 0x01);
+ val = R_REG(osh, &cc->regcontrol_data) & ~(u32) 0x01;
+ val |= (u32) ((rcal_code >> 3) & 0x01);
W_REG(osh, &cc->regcontrol_data, val);
/* Write RCal code into pmu_chip_ctrl[33:30] */
@@ -2195,13 +2195,13 @@
val =
R_REG(osh,
&cc->
- chipcontrol_data) & ~((uint32) 0x03 << 30);
- val |= (uint32) (rcal_code & 0x03) << 30;
+ chipcontrol_data) & ~((u32) 0x03 << 30);
+ val |= (u32) (rcal_code & 0x03) << 30;
W_REG(osh, &cc->chipcontrol_data, val);
W_REG(osh, &cc->chipcontrol_addr, 1);
val =
- R_REG(osh, &cc->chipcontrol_data) & ~(uint32) 0x03;
- val |= (uint32) ((rcal_code >> 2) & 0x03);
+ R_REG(osh, &cc->chipcontrol_data) & ~(u32) 0x03;
+ val |= (u32) ((rcal_code >> 2) & 0x03);
W_REG(osh, &cc->chipcontrol_data, val);
/* Set override in pmu_chip_ctrl[29] */
@@ -2226,7 +2226,7 @@
{
chipcregs_t *cc;
uint origidx, intr_val;
- uint32 tmp = 0;
+ u32 tmp = 0;
/* Remember original core before switch to chipc */
cc = (chipcregs_t *) si_switch_core(sih, CC_CORE_ID, &origidx,
@@ -2262,7 +2262,7 @@
si_pmu_spuravoid_pllupdate(si_t *sih, chipcregs_t *cc, osl_t *osh,
u8 spuravoid)
{
- uint32 tmp = 0;
+ u32 tmp = 0;
u8 phypll_offset = 0;
u8 bcm5357_bcm43236_p1div[] = { 0x1, 0x5, 0x5 };
u8 bcm5357_bcm43236_ndiv[] = { 0x30, 0xf6, 0xfc };
@@ -2581,18 +2581,18 @@
case BCM4319_CHIP_ID:
if (enable)
si_write_wrapperreg(sih, AI_OOBSELOUTB74,
- (uint32) 0x868584);
+ (u32) 0x868584);
else
si_write_wrapperreg(sih, AI_OOBSELOUTB74,
- (uint32) 0x060584);
+ (u32) 0x060584);
break;
}
}
/* Wait for a particular clock level to be on the backplane */
-uint32
-si_pmu_waitforclk_on_backplane(si_t *sih, osl_t *osh, uint32 clk,
- uint32 delay)
+u32
+si_pmu_waitforclk_on_backplane(si_t *sih, osl_t *osh, u32 clk,
+ u32 delay)
{
chipcregs_t *cc;
uint origidx;
@@ -2620,11 +2620,11 @@
#define EXT_ILP_HZ 32768
-uint32 BCMATTACHFN(si_pmu_measure_alpclk) (si_t *sih, osl_t *osh)
+u32 BCMATTACHFN(si_pmu_measure_alpclk) (si_t *sih, osl_t *osh)
{
chipcregs_t *cc;
uint origidx;
- uint32 alp_khz;
+ u32 alp_khz;
if (sih->pmurev < 10)
return 0;
@@ -2637,7 +2637,7 @@
ASSERT(cc != NULL);
if (R_REG(osh, &cc->pmustatus) & PST_EXTLPOAVAIL) {
- uint32 ilp_ctr, alp_hz;
+ u32 ilp_ctr, alp_hz;
/* Enable the reg to measure the freq, in case disabled before */
W_REG(osh, &cc->pmu_xtalfreq,
@@ -2670,9 +2670,9 @@
static void BCMATTACHFN(si_pmu_set_4330_plldivs) (si_t *sih)
{
- uint32 FVCO = si_pmu1_pllfvco0(sih) / 1000;
- uint32 m1div, m2div, m3div, m4div, m5div, m6div;
- uint32 pllc1, pllc2;
+ u32 FVCO = si_pmu1_pllfvco0(sih) / 1000;
+ u32 m1div, m2div, m3div, m4div, m5div, m6div;
+ u32 pllc1, pllc2;
m2div = m3div = m4div = m6div = FVCO / 80;
m5div = FVCO / 160;
diff --git a/drivers/staging/brcm80211/util/linux_osl.c b/drivers/staging/brcm80211/util/linux_osl.c
index b0fb370e..8ad97d4 100644
--- a/drivers/staging/brcm80211/util/linux_osl.c
+++ b/drivers/staging/brcm80211/util/linux_osl.c
@@ -73,7 +73,7 @@
};
/* Global ASSERT type flag */
-uint32 g_assert_type;
+u32 g_assert_type;
#ifdef BRCM_FULLMAC
static s16 linuxbcmerrormap[] = { 0, /* 0 */
@@ -358,7 +358,7 @@
}
#endif /* defined(BRCM_FULLMAC) && defined(DHD_USE_STATIC_BUF) */
-uint32 osl_pci_read_config(osl_t *osh, uint offset, uint size)
+u32 osl_pci_read_config(osl_t *osh, uint offset, uint size)
{
uint val = 0;
uint retry = PCI_CFG_RETRY;
@@ -558,7 +558,7 @@
ASSERT((osh && (osh->magic == OS_HANDLE_MAGIC)));
dir = (direction == DMA_TX) ? PCI_DMA_TODEVICE : PCI_DMA_FROMDEVICE;
- pci_unmap_single(osh->pdev, (uint32) pa, size, dir);
+ pci_unmap_single(osh->pdev, (u32) pa, size, dir);
}
#if defined(BCMDBG_ASSERT)
@@ -636,12 +636,12 @@
return (u16) ((rreg) (ctx, (void *)r, sizeof(u16)));
}
-uint32 osl_readl(osl_t *osh, volatile uint32 *r)
+u32 osl_readl(osl_t *osh, volatile u32 *r)
{
osl_rreg_fn_t rreg = ((osl_pubinfo_t *) osh)->rreg_fn;
void *ctx = ((osl_pubinfo_t *) osh)->reg_ctx;
- return (uint32) ((rreg) (ctx, (void *)r, sizeof(uint32)));
+ return (u32) ((rreg) (ctx, (void *)r, sizeof(u32)));
}
void osl_writeb(osl_t *osh, volatile u8 *r, u8 v)
@@ -660,11 +660,11 @@
((wreg) (ctx, (void *)r, v, sizeof(u16)));
}
-void osl_writel(osl_t *osh, volatile uint32 *r, uint32 v)
+void osl_writel(osl_t *osh, volatile u32 *r, u32 v)
{
osl_wreg_fn_t wreg = ((osl_pubinfo_t *) osh)->wreg_fn;
void *ctx = ((osl_pubinfo_t *) osh)->reg_ctx;
- ((wreg) (ctx, (void *)r, v, sizeof(uint32)));
+ ((wreg) (ctx, (void *)r, v, sizeof(u32)));
}
#endif /* BCMSDIO */
diff --git a/drivers/staging/brcm80211/util/nicpci.c b/drivers/staging/brcm80211/util/nicpci.c
index e6b16ea..0a23a4c 100644
--- a/drivers/staging/brcm80211/util/nicpci.c
+++ b/drivers/staging/brcm80211/util/nicpci.c
@@ -89,14 +89,14 @@
(WORD_VAL(OSL_PCI_READ_CONFIG(osh, DWORD_ALIGN(a), 4), a) & 0xffff)
#define write_pci_cfg_byte(a, val) do { \
- uint32 tmpval; \
+ u32 tmpval; \
tmpval = (OSL_PCI_READ_CONFIG(osh, DWORD_ALIGN(a), 4) & ~0xFF << BYTE_POS(a)) | \
val << BYTE_POS(a); \
OSL_PCI_WRITE_CONFIG(osh, DWORD_ALIGN(a), 4, tmpval); \
} while (0)
#define write_pci_cfg_word(a, val) do { \
- uint32 tmpval; \
+ u32 tmpval; \
tmpval = (OSL_PCI_READ_CONFIG(osh, DWORD_ALIGN(a), 4) & ~0xFFFF << WORD_POS(a)) | \
val << WORD_POS(a); \
OSL_PCI_WRITE_CONFIG(osh, DWORD_ALIGN(a), 4, tmpval); \
@@ -154,11 +154,11 @@
/* Note that it's caller's responsibility to make sure it's a pci bus */
u8
pcicore_find_pci_capability(osl_t *osh, u8 req_cap_id, unsigned char *buf,
- uint32 *buflen)
+ u32 *buflen)
{
u8 cap_id;
u8 cap_ptr = 0;
- uint32 bufsize;
+ u32 bufsize;
u8 byte_val;
/* check for Header type 0 */
@@ -367,25 +367,25 @@
}
/* ***** Support functions ***** */
-u8 pcie_clkreq(void *pch, uint32 mask, uint32 val)
+u8 pcie_clkreq(void *pch, u32 mask, u32 val)
{
pcicore_info_t *pi = (pcicore_info_t *) pch;
- uint32 reg_val;
+ u32 reg_val;
u8 offset;
offset = pi->pciecap_lcreg_offset;
if (!offset)
return 0;
- reg_val = OSL_PCI_READ_CONFIG(pi->osh, offset, sizeof(uint32));
+ reg_val = OSL_PCI_READ_CONFIG(pi->osh, offset, sizeof(u32));
/* set operation */
if (mask) {
if (val)
reg_val |= PCIE_CLKREQ_ENAB;
else
reg_val &= ~PCIE_CLKREQ_ENAB;
- OSL_PCI_WRITE_CONFIG(pi->osh, offset, sizeof(uint32), reg_val);
- reg_val = OSL_PCI_READ_CONFIG(pi->osh, offset, sizeof(uint32));
+ OSL_PCI_WRITE_CONFIG(pi->osh, offset, sizeof(u32), reg_val);
+ reg_val = OSL_PCI_READ_CONFIG(pi->osh, offset, sizeof(u32));
}
if (reg_val & PCIE_CLKREQ_ENAB)
return 1;
@@ -395,7 +395,7 @@
static void pcie_extendL1timer(pcicore_info_t *pi, bool extend)
{
- uint32 w;
+ u32 w;
si_t *sih = pi->sih;
osl_t *osh = pi->osh;
sbpcieregs_t *pcieregs = pi->regs.pcieregs;
@@ -457,7 +457,7 @@
/* Done only once at attach time */
static void pcie_war_polarity(pcicore_info_t *pi)
{
- uint32 w;
+ u32 w;
if (pi->pcie_polarity != 0)
return;
@@ -485,7 +485,7 @@
sbpcieregs_t *pcieregs = pi->regs.pcieregs;
si_t *sih = pi->sih;
u16 val16, *reg16;
- uint32 w;
+ u32 w;
if (!PCIE_ASPM(sih))
return;
@@ -507,11 +507,11 @@
W_REG(pi->osh, reg16, val16);
w = OSL_PCI_READ_CONFIG(pi->osh, pi->pciecap_lcreg_offset,
- sizeof(uint32));
+ sizeof(u32));
w &= ~PCIE_ASPM_ENAB;
w |= pi->pcie_war_aspm_ovr;
OSL_PCI_WRITE_CONFIG(pi->osh, pi->pciecap_lcreg_offset,
- sizeof(uint32), w);
+ sizeof(u32), w);
}
reg16 = &pcieregs->sprom[SRSH_CLKREQ_OFFSET_REV5];
@@ -530,7 +530,7 @@
/* Needs to happen when coming out of 'standby'/'hibernate' */
static void pcie_war_serdes(pcicore_info_t *pi)
{
- uint32 w = 0;
+ u32 w = 0;
if (pi->pcie_polarity != 0)
pcie_mdiowrite(pi, MDIODATA_DEV_RX, SERDES_RX_CTRL,
@@ -583,7 +583,7 @@
si_t *sih = pi->sih;
osl_t *osh = pi->osh;
sbpcieregs_t *pcieregs = pi->regs.pcieregs;
- uint32 w;
+ u32 w;
if ((sih->buscorerev == 0) || (sih->buscorerev == 1)) {
w = pcie_readreg(osh, pcieregs, PCIE_PCIEREGS,
@@ -648,7 +648,7 @@
/* Determine if this board needs override */
if (PCIE_ASPM(sih)) {
- if ((uint32) getintvar(pvars, "boardflags2") & BFL2_PCIEWAR_OVR) {
+ if ((u32) getintvar(pvars, "boardflags2") & BFL2_PCIEWAR_OVR) {
pi->pcie_war_aspm_ovr = PCIE_ASPM_DISAB;
} else {
pi->pcie_war_aspm_ovr = PCIE_ASPM_ENAB;
@@ -693,15 +693,15 @@
void pcicore_sleep(void *pch)
{
pcicore_info_t *pi = (pcicore_info_t *) pch;
- uint32 w;
+ u32 w;
if (!pi || !PCIE_ASPM(pi->sih))
return;
w = OSL_PCI_READ_CONFIG(pi->osh, pi->pciecap_lcreg_offset,
- sizeof(uint32));
+ sizeof(u32));
w &= ~PCIE_CAP_LCREG_ASPML1;
- OSL_PCI_WRITE_CONFIG(pi->osh, pi->pciecap_lcreg_offset, sizeof(uint32),
+ OSL_PCI_WRITE_CONFIG(pi->osh, pi->pciecap_lcreg_offset, sizeof(u32),
w);
pi->pcie_pr42767 = FALSE;
@@ -725,7 +725,7 @@
bool pcicore_pmecap_fast(osl_t *osh)
{
u8 cap_ptr;
- uint32 pmecap;
+ u32 pmecap;
cap_ptr =
pcicore_find_pci_capability(osh, PCI_CAP_POWERMGMTCAP_ID, NULL,
@@ -734,7 +734,7 @@
if (!cap_ptr)
return FALSE;
- pmecap = OSL_PCI_READ_CONFIG(osh, cap_ptr, sizeof(uint32));
+ pmecap = OSL_PCI_READ_CONFIG(osh, cap_ptr, sizeof(u32));
return (pmecap & PME_CAP_PM_STATES) != 0;
}
@@ -745,7 +745,7 @@
static bool pcicore_pmecap(pcicore_info_t *pi)
{
u8 cap_ptr;
- uint32 pmecap;
+ u32 pmecap;
if (!pi->pmecap_offset) {
cap_ptr =
@@ -759,7 +759,7 @@
pmecap =
OSL_PCI_READ_CONFIG(pi->osh, pi->pmecap_offset,
- sizeof(uint32));
+ sizeof(u32));
/* At least one state can generate PME */
pi->pmecap = (pmecap & PME_CAP_PM_STATES) != 0;
@@ -772,17 +772,17 @@
void pcicore_pmeen(void *pch)
{
pcicore_info_t *pi = (pcicore_info_t *) pch;
- uint32 w;
+ u32 w;
/* if not pmecapable return */
if (!pcicore_pmecap(pi))
return;
w = OSL_PCI_READ_CONFIG(pi->osh, pi->pmecap_offset + PME_CSR_OFFSET,
- sizeof(uint32));
+ sizeof(u32));
w |= (PME_CSR_PME_EN);
OSL_PCI_WRITE_CONFIG(pi->osh, pi->pmecap_offset + PME_CSR_OFFSET,
- sizeof(uint32), w);
+ sizeof(u32), w);
}
/*
@@ -791,13 +791,13 @@
bool pcicore_pmestat(void *pch)
{
pcicore_info_t *pi = (pcicore_info_t *) pch;
- uint32 w;
+ u32 w;
if (!pcicore_pmecap(pi))
return FALSE;
w = OSL_PCI_READ_CONFIG(pi->osh, pi->pmecap_offset + PME_CSR_OFFSET,
- sizeof(uint32));
+ sizeof(u32));
return (w & PME_CSR_PME_STAT) == PME_CSR_PME_STAT;
}
@@ -807,13 +807,13 @@
void pcicore_pmeclr(void *pch)
{
pcicore_info_t *pi = (pcicore_info_t *) pch;
- uint32 w;
+ u32 w;
if (!pcicore_pmecap(pi))
return;
w = OSL_PCI_READ_CONFIG(pi->osh, pi->pmecap_offset + PME_CSR_OFFSET,
- sizeof(uint32));
+ sizeof(u32));
PCI_ERROR(("pcicore_pci_pmeclr PMECSR : 0x%x\n", w));
@@ -821,10 +821,10 @@
w &= ~(PME_CSR_PME_EN);
OSL_PCI_WRITE_CONFIG(pi->osh, pi->pmecap_offset + PME_CSR_OFFSET,
- sizeof(uint32), w);
+ sizeof(u32), w);
}
-uint32 pcie_lcreg(void *pch, uint32 mask, uint32 val)
+u32 pcie_lcreg(void *pch, u32 mask, u32 val)
{
pcicore_info_t *pi = (pcicore_info_t *) pch;
u8 offset;
@@ -835,15 +835,15 @@
/* set operation */
if (mask)
- OSL_PCI_WRITE_CONFIG(pi->osh, offset, sizeof(uint32), val);
+ OSL_PCI_WRITE_CONFIG(pi->osh, offset, sizeof(u32), val);
- return OSL_PCI_READ_CONFIG(pi->osh, offset, sizeof(uint32));
+ return OSL_PCI_READ_CONFIG(pi->osh, offset, sizeof(u32));
}
-uint32
-pcicore_pciereg(void *pch, uint32 offset, uint32 mask, uint32 val, uint type)
+u32
+pcicore_pciereg(void *pch, u32 offset, u32 mask, u32 val, uint type)
{
- uint32 reg_val = 0;
+ u32 reg_val = 0;
pcicore_info_t *pi = (pcicore_info_t *) pch;
sbpcieregs_t *pcieregs = pi->regs.pcieregs;
osl_t *osh = pi->osh;
@@ -864,11 +864,11 @@
return reg_val;
}
-uint32
-pcicore_pcieserdesreg(void *pch, uint32 mdioslave, uint32 offset, uint32 mask,
- uint32 val)
+u32
+pcicore_pcieserdesreg(void *pch, u32 mdioslave, u32 offset, u32 mask,
+ u32 val)
{
- uint32 reg_val = 0;
+ u32 reg_val = 0;
pcicore_info_t *pi = (pcicore_info_t *) pch;
if (mask) {
diff --git a/drivers/staging/brcm80211/util/qmath.c b/drivers/staging/brcm80211/util/qmath.c
index db06ecb..e9b9d21 100644
--- a/drivers/staging/brcm80211/util/qmath.c
+++ b/drivers/staging/brcm80211/util/qmath.c
@@ -83,7 +83,7 @@
*/
u16 qm_mulu16(u16 op1, u16 op2)
{
- return (u16) (((uint32) op1 * (uint32) op2) >> 16);
+ return (u16) (((u32) op1 * (u32) op2) >> 16);
}
/*
diff --git a/drivers/staging/brcm80211/util/sbutils.c b/drivers/staging/brcm80211/util/sbutils.c
index 0f0d5a5..acb78a0 100644
--- a/drivers/staging/brcm80211/util/sbutils.c
+++ b/drivers/staging/brcm80211/util/sbutils.c
@@ -28,10 +28,10 @@
#include "siutils_priv.h"
/* local prototypes */
-static uint _sb_coreidx(si_info_t *sii, uint32 sba);
-static uint _sb_scan(si_info_t *sii, uint32 sba, void *regs, uint bus,
- uint32 sbba, uint ncores);
-static uint32 _sb_coresba(si_info_t *sii);
+static uint _sb_coreidx(si_info_t *sii, u32 sba);
+static uint _sb_scan(si_info_t *sii, u32 sba, void *regs, uint bus,
+ u32 sbba, uint ncores);
+static u32 _sb_coresba(si_info_t *sii);
static void *_sb_setcoreidx(si_info_t *sii, uint coreidx);
#define SET_SBREG(sii, r, mask, val) \
@@ -49,12 +49,12 @@
#define OR_SBREG(sii, sbr, v) \
W_SBREG((sii), (sbr), (R_SBREG((sii), (sbr)) | (v)))
-static uint32 sb_read_sbreg(si_info_t *sii, volatile uint32 *sbr)
+static u32 sb_read_sbreg(si_info_t *sii, volatile u32 *sbr)
{
return R_REG(sii->osh, sbr);
}
-static void sb_write_sbreg(si_info_t *sii, volatile uint32 *sbr, uint32 v)
+static void sb_write_sbreg(si_info_t *sii, volatile u32 *sbr, u32 v)
{
W_REG(sii->osh, sbr, v);
}
@@ -72,7 +72,7 @@
}
/* return core index of the core with address 'sba' */
-static uint BCMATTACHFN(_sb_coreidx) (si_info_t *sii, uint32 sba)
+static uint BCMATTACHFN(_sb_coreidx) (si_info_t *sii, u32 sba)
{
uint i;
@@ -83,14 +83,14 @@
}
/* return core address of the current core */
-static uint32 BCMATTACHFN(_sb_coresba) (si_info_t *sii)
+static u32 BCMATTACHFN(_sb_coresba) (si_info_t *sii)
{
- uint32 sbaddr = 0;
+ u32 sbaddr = 0;
switch (BUSTYPE(sii->pub.bustype)) {
case SPI_BUS:
case SDIO_BUS:
- sbaddr = (uint32) (uintptr) sii->curmap;
+ sbaddr = (u32) (uintptr) sii->curmap;
break;
default:
ASSERT(0);
@@ -142,7 +142,7 @@
uint sb_corereg(si_t *sih, uint coreidx, uint regoff, uint mask, uint val)
{
uint origidx = 0;
- uint32 *r = NULL;
+ u32 *r = NULL;
uint w;
uint intr_val = 0;
bool fast = FALSE;
@@ -164,7 +164,7 @@
origidx = si_coreidx(&sii->pub);
/* switch core */
- r = (uint32 *) ((unsigned char *) sb_setcoreidx(&sii->pub, coreidx) +
+ r = (u32 *) ((unsigned char *) sb_setcoreidx(&sii->pub, coreidx) +
regoff);
}
ASSERT(r != NULL);
@@ -206,8 +206,8 @@
*/
#define SB_MAXBUSES 2
static uint
-BCMATTACHFN(_sb_scan) (si_info_t *sii, uint32 sba, void *regs, uint bus,
- uint32 sbba, uint numcores) {
+BCMATTACHFN(_sb_scan) (si_info_t *sii, u32 sba, void *regs, uint bus,
+ u32 sbba, uint numcores) {
uint next;
uint ncc = 0;
uint i;
@@ -237,7 +237,7 @@
/* chipc provides # cores */
if (sii->coreid[next] == CC_CORE_ID) {
chipcregs_t *cc = (chipcregs_t *) sii->curmap;
- uint32 ccrev = sb_corerev(&sii->pub);
+ u32 ccrev = sb_corerev(&sii->pub);
/* determine numcores - this is the
total # cores in the chip */
@@ -259,7 +259,7 @@
/* scan bridged SB(s) and add results to the end of the list */
else if (sii->coreid[next] == OCP_CORE_ID) {
sbconfig_t *sb = REGS2SB(sii->curmap);
- uint32 nsbba = R_SBREG(sii, &sb->sbadmatch1);
+ u32 nsbba = R_SBREG(sii, &sb->sbadmatch1);
uint nsbcc;
sii->numcores = next + 1;
@@ -290,7 +290,7 @@
void BCMATTACHFN(sb_scan) (si_t *sih, void *regs, uint devid)
{
si_info_t *sii;
- uint32 origsba;
+ u32 origsba;
sbconfig_t *sb;
sii = SI_INFO(sih);
@@ -341,7 +341,7 @@
*/
static void *_sb_setcoreidx(si_info_t *sii, uint coreidx)
{
- uint32 sbaddr = sii->coresba[coreidx];
+ u32 sbaddr = sii->coresba[coreidx];
void *regs;
switch (BUSTYPE(sii->pub.bustype)) {
@@ -403,9 +403,9 @@
uint origidx;
uint intr_val = 0;
bool rc = FALSE;
- uint32 inband = 0, serror = 0, timeout = 0;
+ u32 inband = 0, serror = 0, timeout = 0;
void *corereg = NULL;
- volatile uint32 imstate, tmstate;
+ volatile u32 imstate, tmstate;
sii = SI_INFO(sih);
@@ -453,10 +453,10 @@
return rc;
}
-void sb_core_disable(si_t *sih, uint32 bits)
+void sb_core_disable(si_t *sih, u32 bits)
{
si_info_t *sii;
- volatile uint32 dummy;
+ volatile u32 dummy;
sbconfig_t *sb;
sii = SI_INFO(sih);
@@ -512,11 +512,11 @@
* bits - core specific bits that are set during and after reset sequence
* resetbits - core specific bits that are set only during reset sequence
*/
-void sb_core_reset(si_t *sih, uint32 bits, uint32 resetbits)
+void sb_core_reset(si_t *sih, u32 bits, u32 resetbits)
{
si_info_t *sii;
sbconfig_t *sb;
- volatile uint32 dummy;
+ volatile u32 dummy;
sii = SI_INFO(sih);
ASSERT(GOODREGS(sii->curmap));
@@ -561,9 +561,9 @@
OSL_DELAY(1);
}
-uint32 sb_base(uint32 admatch)
+u32 sb_base(u32 admatch)
{
- uint32 base;
+ u32 base;
uint type;
type = admatch & SBAM_TYPE_MASK;
diff --git a/drivers/staging/brcm80211/util/siutils.c b/drivers/staging/brcm80211/util/siutils.c
index 9ed6dfe..42fe899 100644
--- a/drivers/staging/brcm80211/util/siutils.c
+++ b/drivers/staging/brcm80211/util/siutils.c
@@ -60,7 +60,7 @@
static bool si_buscore_prep(si_info_t *sii, uint bustype, uint devid,
void *sdh);
static bool si_buscore_setup(si_info_t *sii, chipcregs_t *cc, uint bustype,
- uint32 savewin, uint *origidx, void *regs);
+ u32 savewin, uint *origidx, void *regs);
static void si_nvram_process(si_info_t *sii, char *pvars);
/* dev path concatenation util */
@@ -71,7 +71,7 @@
u8 idx, u8 mtype);
/* global variable to indicate reservation/release of gpio's */
-static uint32 si_gpioreservation;
+static u32 si_gpioreservation;
/*
* Allocate a si handle.
@@ -167,7 +167,7 @@
static bool
BCMATTACHFN(si_buscore_setup) (si_info_t *sii, chipcregs_t *cc, uint bustype,
- uint32 savewin, uint *origidx, void *regs) {
+ u32 savewin, uint *origidx, void *regs) {
bool pci, pcie;
uint i;
uint pciidx, pcieidx, pcirev, pcierev;
@@ -313,7 +313,7 @@
switch (BUSTYPE(sii->pub.bustype)) {
case PCI_BUS:
/* do a pci config read to get subsystem id and subvendor id */
- w = OSL_PCI_READ_CONFIG(sii->osh, PCI_CFG_SVID, sizeof(uint32));
+ w = OSL_PCI_READ_CONFIG(sii->osh, PCI_CFG_SVID, sizeof(u32));
/* Let nvram variables override subsystem Vend/ID */
sii->pub.boardvendor = (u16)si_getdevpathintvar(&sii->pub,
"boardvendor");
@@ -371,7 +371,7 @@
uint bustype, void *sdh,
char **vars, uint *varsz) {
struct si_pub *sih = &sii->pub;
- uint32 w, savewin;
+ u32 w, savewin;
chipcregs_t *cc;
char *pvars = NULL;
uint origidx;
@@ -470,7 +470,7 @@
#ifndef BRCM_FULLMAC
/* PMU specific initializations */
if (PMUCTL_ENAB(sih)) {
- uint32 xtalfreq;
+ u32 xtalfreq;
si_pmu_init(sih, sii->osh);
si_pmu_chip_init(sih, sii->osh);
xtalfreq = getintvar(pvars, "xtalfreq");
@@ -506,7 +506,7 @@
uint bustype, void *sdh,
char **vars, uint *varsz) {
struct si_pub *sih = &sii->pub;
- uint32 w, savewin;
+ u32 w, savewin;
chipcregs_t *cc;
char *pvars = NULL;
uint origidx;
@@ -525,7 +525,7 @@
/* check to see if we are a si core mimic'ing a pci core */
if ((bustype == PCI_BUS) &&
- (OSL_PCI_READ_CONFIG(sii->osh, PCI_SPROM_CONTROL, sizeof(uint32)) ==
+ (OSL_PCI_READ_CONFIG(sii->osh, PCI_SPROM_CONTROL, sizeof(u32)) ==
0xffffffff)) {
SI_ERROR(("%s: incoming bus is PCI but it's a lie, switching to SI " "devid:0x%x\n", __func__, devid));
bustype = SI_BUS;
@@ -534,7 +534,7 @@
/* find Chipcommon address */
if (bustype == PCI_BUS) {
savewin =
- OSL_PCI_READ_CONFIG(sii->osh, PCI_BAR0_WIN, sizeof(uint32));
+ OSL_PCI_READ_CONFIG(sii->osh, PCI_BAR0_WIN, sizeof(u32));
if (!GOODCOREADDR(savewin, SI_ENUM_BASE))
savewin = SI_ENUM_BASE;
OSL_PCI_WRITE_CONFIG(sii->osh, PCI_BAR0_WIN, 4, SI_ENUM_BASE);
@@ -630,7 +630,7 @@
/* PMU specific initializations */
if (PMUCTL_ENAB(sih)) {
- uint32 xtalfreq;
+ u32 xtalfreq;
si_pmu_init(sih, sii->osh);
si_pmu_chip_init(sih, sii->osh);
xtalfreq = getintvar(pvars, "xtalfreq");
@@ -918,7 +918,7 @@
INTR_RESTORE(sii, intr_val);
}
-uint32 si_core_cflags(si_t *sih, uint32 mask, uint32 val)
+u32 si_core_cflags(si_t *sih, u32 mask, u32 val)
{
if (CHIPTYPE(sih->socitype) == SOCI_AI)
return ai_core_cflags(sih, mask, val);
@@ -928,7 +928,7 @@
}
}
-uint32 si_core_sflags(si_t *sih, uint32 mask, uint32 val)
+u32 si_core_sflags(si_t *sih, u32 mask, u32 val)
{
if (CHIPTYPE(sih->socitype) == SOCI_AI)
return ai_core_sflags(sih, mask, val);
@@ -952,7 +952,7 @@
}
}
-void si_write_wrapperreg(si_t *sih, uint32 offset, uint32 val)
+void si_write_wrapperreg(si_t *sih, u32 offset, u32 val)
{
/* only for 4319, no requirement for SOCI_SB */
if (CHIPTYPE(sih->socitype) == SOCI_AI) {
@@ -975,7 +975,7 @@
}
}
-void si_core_disable(si_t *sih, uint32 bits)
+void si_core_disable(si_t *sih, u32 bits)
{
if (CHIPTYPE(sih->socitype) == SOCI_AI)
@@ -986,7 +986,7 @@
#endif
}
-void si_core_reset(si_t *sih, uint32 bits, uint32 resetbits)
+void si_core_reset(si_t *sih, u32 bits, u32 resetbits)
{
if (CHIPTYPE(sih->socitype) == SOCI_AI)
ai_core_reset(sih, bits, resetbits);
@@ -996,7 +996,7 @@
#endif
}
-uint32 BCMINITFN(si_alp_clock) (si_t *sih)
+u32 BCMINITFN(si_alp_clock) (si_t *sih)
{
if (PMUCTL_ENAB(sih))
return si_pmu_alp_clock(sih, si_osh(sih));
@@ -1004,7 +1004,7 @@
return ALP_CLOCK;
}
-uint32 BCMINITFN(si_ilp_clock) (si_t *sih)
+u32 BCMINITFN(si_ilp_clock) (si_t *sih)
{
if (PMUCTL_ENAB(sih))
return si_pmu_ilp_clock(sih, si_osh(sih));
@@ -1092,7 +1092,7 @@
if (sii->pub.ccrev < 6) {
if ((BUSTYPE(sii->pub.bustype) == PCI_BUS) &&
- (OSL_PCI_READ_CONFIG(sii->osh, PCI_GPIO_OUT, sizeof(uint32))
+ (OSL_PCI_READ_CONFIG(sii->osh, PCI_GPIO_OUT, sizeof(u32))
& PCI_CFG_GPIO_SCS))
return SCC_SS_PCI;
else
@@ -1107,7 +1107,7 @@
/* return the ILP (slowclock) min or max frequency */
static uint si_slowclk_freq(si_info_t *sii, bool max_freq, chipcregs_t *cc)
{
- uint32 slowclk;
+ u32 slowclk;
uint div;
ASSERT(SI_FAST(sii) || si_coreid(&sii->pub) == CC_CORE_ID);
@@ -1262,7 +1262,7 @@
int si_clkctl_xtal(si_t *sih, uint what, bool on)
{
si_info_t *sii;
- uint32 in, out, outen;
+ u32 in, out, outen;
sii = SI_INFO(sih);
@@ -1278,12 +1278,12 @@
if (PCIE(sii))
return -1;
- in = OSL_PCI_READ_CONFIG(sii->osh, PCI_GPIO_IN, sizeof(uint32));
+ in = OSL_PCI_READ_CONFIG(sii->osh, PCI_GPIO_IN, sizeof(u32));
out =
- OSL_PCI_READ_CONFIG(sii->osh, PCI_GPIO_OUT, sizeof(uint32));
+ OSL_PCI_READ_CONFIG(sii->osh, PCI_GPIO_OUT, sizeof(u32));
outen =
OSL_PCI_READ_CONFIG(sii->osh, PCI_GPIO_OUTEN,
- sizeof(uint32));
+ sizeof(u32));
/*
* Avoid glitching the clock if GPRS is already using it.
@@ -1305,9 +1305,9 @@
if (what & PLL)
out |= PCI_CFG_GPIO_PLL;
OSL_PCI_WRITE_CONFIG(sii->osh, PCI_GPIO_OUT,
- sizeof(uint32), out);
+ sizeof(u32), out);
OSL_PCI_WRITE_CONFIG(sii->osh, PCI_GPIO_OUTEN,
- sizeof(uint32), outen);
+ sizeof(u32), outen);
OSL_DELAY(XTAL_ON_DELAY);
}
@@ -1315,7 +1315,7 @@
if (what & PLL) {
out &= ~PCI_CFG_GPIO_PLL;
OSL_PCI_WRITE_CONFIG(sii->osh, PCI_GPIO_OUT,
- sizeof(uint32), out);
+ sizeof(u32), out);
OSL_DELAY(2000);
}
} else {
@@ -1324,9 +1324,9 @@
if (what & PLL)
out |= PCI_CFG_GPIO_PLL;
OSL_PCI_WRITE_CONFIG(sii->osh, PCI_GPIO_OUT,
- sizeof(uint32), out);
+ sizeof(u32), out);
OSL_PCI_WRITE_CONFIG(sii->osh, PCI_GPIO_OUTEN,
- sizeof(uint32), outen);
+ sizeof(u32), outen);
}
default:
@@ -1365,7 +1365,7 @@
{
uint origidx = 0;
chipcregs_t *cc;
- uint32 scc;
+ u32 scc;
uint intr_val = 0;
bool fast = SI_FAST(sii);
@@ -1411,7 +1411,7 @@
/* wait for the PLL */
if (PMUCTL_ENAB(&sii->pub)) {
- uint32 htavail = CCS_HTAVAIL;
+ u32 htavail = CCS_HTAVAIL;
SPINWAIT(((R_REG(sii->osh, &cc->clk_ctl_st) & htavail)
== 0), PMU_MAX_TRANSITION_DLY);
ASSERT(R_REG(sii->osh, &cc->clk_ctl_st) & htavail);
@@ -1666,7 +1666,7 @@
{
si_info_t *sii;
sbpciregs_t *pciregs = NULL;
- uint32 siflag = 0, w;
+ u32 siflag = 0, w;
uint idx = 0;
sii = SI_INFO(sih);
@@ -1695,9 +1695,9 @@
*/
if (PCIE(sii) || (PCI(sii) && ((sii->pub.buscorerev) >= 6))) {
/* pci config write to set this core bit in PCIIntMask */
- w = OSL_PCI_READ_CONFIG(sii->osh, PCI_INT_MASK, sizeof(uint32));
+ w = OSL_PCI_READ_CONFIG(sii->osh, PCI_INT_MASK, sizeof(u32));
w |= (coremask << PCI_SBIM_SHIFT);
- OSL_PCI_WRITE_CONFIG(sii->osh, PCI_INT_MASK, sizeof(uint32), w);
+ OSL_PCI_WRITE_CONFIG(sii->osh, PCI_INT_MASK, sizeof(u32), w);
} else {
/* set sbintvec bit for our flag number */
si_setint(sih, siflag);
@@ -1770,7 +1770,7 @@
}
/* mask&set gpiocontrol bits */
-uint32 si_gpiocontrol(si_t *sih, uint32 mask, uint32 val, u8 priority)
+u32 si_gpiocontrol(si_t *sih, u32 mask, u32 val, u8 priority)
{
uint regoff;
@@ -1808,7 +1808,7 @@
}
/* Return the RAM size of the SOCRAM core */
-uint32 si_socram_size(si_t *sih)
+u32 si_socram_size(si_t *sih)
{
si_info_t *sii;
uint origidx;
@@ -1817,7 +1817,7 @@
sbsocramregs_t *regs;
bool wasup;
uint corerev;
- uint32 coreinfo;
+ u32 coreinfo;
uint memsize = 0;
sii = SI_INFO(sih);
@@ -1877,7 +1877,7 @@
si_info_t *sii;
chipcregs_t *cc;
uint origidx;
- uint32 val;
+ u32 val;
sii = SI_INFO(sih);
origidx = si_coreidx(sih);
@@ -1927,7 +1927,7 @@
/* check if the device is removed */
bool si_deviceremoved(si_t *sih)
{
- uint32 w;
+ u32 w;
si_info_t *sii;
sii = SI_INFO(sih);
@@ -1935,7 +1935,7 @@
switch (BUSTYPE(sih->bustype)) {
case PCI_BUS:
ASSERT(sii->osh != NULL);
- w = OSL_PCI_READ_CONFIG(sii->osh, PCI_CFG_VID, sizeof(uint32));
+ w = OSL_PCI_READ_CONFIG(sii->osh, PCI_CFG_VID, sizeof(u32));
if ((w & 0xFFFF) != VENDOR_BROADCOM)
return TRUE;
break;
@@ -1949,7 +1949,7 @@
si_info_t *sii;
uint origidx;
chipcregs_t *cc;
- uint32 sromctrl;
+ u32 sromctrl;
if ((sih->cccaps & CC_CAP_SROM) == 0)
return FALSE;
diff --git a/drivers/staging/brcm80211/util/siutils_priv.h b/drivers/staging/brcm80211/util/siutils_priv.h
index 51b8803..0284614 100644
--- a/drivers/staging/brcm80211/util/siutils_priv.h
+++ b/drivers/staging/brcm80211/util/siutils_priv.h
@@ -25,8 +25,8 @@
uint val);
extern bool sb_iscoreup(si_t *sih);
void *sb_setcoreidx(si_t *sih, uint coreidx);
-extern uint32 sb_base(uint32 admatch);
-extern void sb_core_reset(si_t *sih, uint32 bits, uint32 resetbits);
-extern void sb_core_disable(si_t *sih, uint32 bits);
+extern u32 sb_base(u32 admatch);
+extern void sb_core_reset(si_t *sih, u32 bits, u32 resetbits);
+extern void sb_core_disable(si_t *sih, u32 bits);
extern bool sb_taclear(si_t *sih, bool details);
#endif /* _siutils_priv_h_ */