MIPS: Emulate the new MIPS R6 BEQZC and JIC instructions
MIPS R6 uses the <R6 ldc2 opcode for the new BEQZC and JIC instructions
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
diff --git a/arch/mips/include/uapi/asm/inst.h b/arch/mips/include/uapi/asm/inst.h
index 32063c5..721f8fe 100644
--- a/arch/mips/include/uapi/asm/inst.h
+++ b/arch/mips/include/uapi/asm/inst.h
@@ -32,7 +32,7 @@
sb_op, sh_op, swl_op, sw_op,
sdl_op, sdr_op, swr_op, cache_op,
ll_op, lwc1_op, lwc2_op, bc6_op = lwc2_op, pref_op,
- lld_op, ldc1_op, ldc2_op, ld_op,
+ lld_op, ldc1_op, ldc2_op, beqzcjic_op = ldc2_op, ld_op,
sc_op, swc1_op, swc2_op, balc6_op = swc2_op, major_3b_op,
scd_op, sdc1_op, sdc2_op, sd_op
};
diff --git a/arch/mips/kernel/branch.c b/arch/mips/kernel/branch.c
index 1f28724..c61a41d 100644
--- a/arch/mips/kernel/branch.c
+++ b/arch/mips/kernel/branch.c
@@ -799,6 +799,14 @@
epc += 4 + (insn.i_format.simmediate << 2);
regs->cp0_epc = epc;
break;
+ case beqzcjic_op:
+ if (!cpu_has_mips_r6) {
+ ret = -SIGILL;
+ break;
+ }
+ /* Compact branch: BEQZC || JIC */
+ regs->cp0_epc += 8;
+ break;
#endif
case cbcond0_op:
case cbcond1_op:
diff --git a/arch/mips/math-emu/cp1emu.c b/arch/mips/math-emu/cp1emu.c
index d732100..f00af84 100644
--- a/arch/mips/math-emu/cp1emu.c
+++ b/arch/mips/math-emu/cp1emu.c
@@ -679,6 +679,13 @@
dec_insn.next_pc_inc;
return 1;
+ case beqzcjic_op:
+ if (!cpu_has_mips_r6)
+ break;
+ *contpc = regs->cp0_epc + dec_insn.pc_inc +
+ dec_insn.next_pc_inc;
+
+ return 1;
#endif
case cop0_op:
case cop1_op: