clk: msm: mdss: fix dp_link_2x_clk_mux clock ops for DP PLL on msm8998
The DP link clock path in the DSI PLL has a mux clock (dp_link_2x_clk_mux)
which allows the pixel clock to be either sourced out two divider clocks.
In the current code, the ops for this mux clock is overloaded
incorrectly which results in the link clock being always sourced
out of the first divider clock. Fix this by using
the default mux clock ops for this clock.
CRs-Fixed: 1009740
Change-Id: Ie12d5ab272dbd79fe97225864c2360fdde7325a7
Signed-off-by: Chandan Uddaraju <chandanu@codeaurora.org>
1 file changed