tree e6304ae02ad41ab2620776a7b54cdf61b1e31546
parent ea72dc2cf9552631e43327ce593bdbb0b9fdf058
parent 6f86341726cbec1921e925fd54a10c5b58e6f9f1
author Mike Turquette <mturquette@linaro.org> 1388353076 -0800
committer Mike Turquette <mturquette@linaro.org> 1388353076 -0800

Merge tag 'sunxi-clk-3.14-for-mike' of https://bitbucket.org/emiliolopez/linux into clk-next-sunxi

Allwinner sunXi SoCs clock changes

This contains the clk driver parts of the "[PATCH v3 00/13] clk: sunxi:
add PLL5 and PLL6 support" series. It adds support for PLL4/5/6 and
mod0 clocks on most sunxi platforms. Additionally, it contains "[PATCH
1/4] clk: sunxi: Allwinner A20 output clock support" (v2) from Chen-Yu
Tsai, which adds support for output clocks present on A20.