ARM: OMAP2: Change 24xx to use shared clock code and new reg access
This patch changes 24xx to use shared clock code and new register
access.
Note that patch adds some temporary OLD_CK defines to keep patch
more readable. These temporary defines will be removed in the next
patch. Also not all clocks are changed in this patch to limit the
size.
Also, the patch fixes few incorrect clock defines in clock24xx.h.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
diff --git a/arch/arm/mach-omap2/memory.c b/arch/arm/mach-omap2/memory.c
index b56c1a0..1247908 100644
--- a/arch/arm/mach-omap2/memory.c
+++ b/arch/arm/mach-omap2/memory.c
@@ -53,6 +53,54 @@
return mem_timings.m_type;
}
+/*
+ * Check the DLL lock state, and return tue if running in unlock mode.
+ * This is needed to compensate for the shifted DLL value in unlock mode.
+ */
+u32 omap2_dll_force_needed(void)
+{
+ /* dlla and dllb are a set */
+ u32 dll_state = sdrc_read_reg(SDRC_DLLA_CTRL);
+
+ if ((dll_state & (1 << 2)) == (1 << 2))
+ return 1;
+ else
+ return 0;
+}
+
+/*
+ * 'level' is the value to store to CM_CLKSEL2_PLL.CORE_CLK_SRC.
+ * Practical values are CORE_CLK_SRC_DPLL (for CORE_CLK = DPLL_CLK) or
+ * CORE_CLK_SRC_DPLL_X2 (for CORE_CLK = * DPLL_CLK * 2)
+ */
+u32 omap2_reprogram_sdrc(u32 level, u32 force)
+{
+ u32 dll_ctrl, m_type;
+ u32 prev = curr_perf_level;
+ unsigned long flags;
+
+ if ((curr_perf_level == level) && !force)
+ return prev;
+
+ if (level == CORE_CLK_SRC_DPLL) {
+ dll_ctrl = omap2_memory_get_slow_dll_ctrl();
+ } else if (level == CORE_CLK_SRC_DPLL_X2) {
+ dll_ctrl = omap2_memory_get_fast_dll_ctrl();
+ } else {
+ return prev;
+ }
+
+ m_type = omap2_memory_get_type();
+
+ local_irq_save(flags);
+ __raw_writel(0xffff, OMAP24XX_PRCM_VOLTSETUP);
+ omap2_sram_reprogram_sdrc(level, dll_ctrl, m_type);
+ curr_perf_level = level;
+ local_irq_restore(flags);
+
+ return prev;
+}
+
void omap2_init_memory_params(u32 force_lock_to_unlock_mode)
{
unsigned long dll_cnt;