msm: camera: Port msm-4.4 camera kernel on msm-4.9 kernel
This snapshot is taken from msm-4.4 branch as of:
'commit ee294a60356a ("msm: jpegdma: Fix for ASAN issues in jpegdma module")'
Change-Id: I3aba3098a986a5dec84b4bb4144dda19d1db5790
Signed-off-by: Pratap Nirujogi <pratapn@codeaurora.org>
Signed-off-by: Trishansh Bhardwaj <tbhardwa@codeaurora.org>
diff --git a/include/media/msm_cam_sensor.h b/include/media/msm_cam_sensor.h
new file mode 100644
index 0000000..2c8b651
--- /dev/null
+++ b/include/media/msm_cam_sensor.h
@@ -0,0 +1,294 @@
+#ifndef __LINUX_MSM_CAM_SENSOR_H
+#define __LINUX_MSM_CAM_SENSOR_H
+
+#include <uapi/media/msm_cam_sensor.h>
+#include <uapi/media/msm_camsensor_sdk.h>
+
+#include <linux/compat.h>
+
+#ifdef CONFIG_COMPAT
+
+struct msm_sensor_power_setting32 {
+ enum msm_sensor_power_seq_type_t seq_type;
+ uint16_t seq_val;
+ compat_uint_t config_val;
+ uint16_t delay;
+ compat_uptr_t data[10];
+};
+
+struct msm_sensor_power_setting_array32 {
+ struct msm_sensor_power_setting32 power_setting_a[MAX_POWER_CONFIG];
+ compat_uptr_t power_setting;
+ uint16_t size;
+ struct msm_sensor_power_setting32
+ power_down_setting_a[MAX_POWER_CONFIG];
+ compat_uptr_t power_down_setting;
+ uint16_t size_down;
+};
+
+struct msm_camera_sensor_slave_info32 {
+ char sensor_name[32];
+ char eeprom_name[32];
+ char actuator_name[32];
+ char ois_name[32];
+ char flash_name[32];
+ enum msm_sensor_camera_id_t camera_id;
+ uint16_t slave_addr;
+ enum i2c_freq_mode_t i2c_freq_mode;
+ enum msm_camera_i2c_reg_addr_type addr_type;
+ struct msm_sensor_id_info_t sensor_id_info;
+ struct msm_sensor_power_setting_array32 power_setting_array;
+ uint8_t is_init_params_valid;
+ struct msm_sensor_init_params sensor_init_params;
+ enum msm_sensor_output_format_t output_format;
+ uint8_t bypass_video_node_creation;
+};
+
+struct msm_camera_csid_lut_params32 {
+ uint8_t num_cid;
+ struct msm_camera_csid_vc_cfg vc_cfg_a[MAX_CID];
+ compat_uptr_t vc_cfg[MAX_CID];
+};
+
+struct msm_camera_csid_params32 {
+ uint8_t lane_cnt;
+ uint16_t lane_assign;
+ uint8_t phy_sel;
+ uint32_t csi_clk;
+ struct msm_camera_csid_lut_params32 lut_params;
+ uint8_t csi_3p_sel;
+};
+
+struct msm_camera_csi2_params32 {
+ struct msm_camera_csid_params32 csid_params;
+ struct msm_camera_csiphy_params csiphy_params;
+ uint8_t csi_clk_scale_enable;
+};
+
+struct csid_cfg_data32 {
+ enum csid_cfg_type_t cfgtype;
+ union {
+ uint32_t csid_version;
+ compat_uptr_t csid_params;
+ compat_uptr_t csid_testmode_params;
+ } cfg;
+};
+
+struct msm_ir_led_cfg_data_t32 {
+ enum msm_ir_led_cfg_type_t cfg_type;
+ int32_t pwm_duty_on_ns;
+ int32_t pwm_period_ns;
+};
+
+struct msm_ir_cut_cfg_data_t32 {
+ enum msm_ir_cut_cfg_type_t cfg_type;
+};
+
+struct msm_laser_led_cfg_data_t32 {
+ enum msm_laser_led_cfg_type_t cfg_type;
+ compat_uptr_t setting;
+ compat_uptr_t debug_reg;
+ uint32_t debug_reg_size;
+ uint16_t i2c_addr;
+ enum i2c_freq_mode_t i2c_freq_mode;
+};
+
+struct eeprom_read_t32 {
+ compat_uptr_t dbuffer;
+ uint32_t num_bytes;
+};
+
+struct eeprom_write_t32 {
+ compat_uptr_t dbuffer;
+ uint32_t num_bytes;
+};
+
+struct msm_eeprom_info_t32 {
+ compat_uptr_t power_setting_array;
+ enum i2c_freq_mode_t i2c_freq_mode;
+ compat_uptr_t mem_map_array;
+};
+
+struct msm_eeprom_cfg_data32 {
+ enum eeprom_cfg_type_t cfgtype;
+ uint8_t is_supported;
+ union {
+ char eeprom_name[MAX_SENSOR_NAME];
+ struct eeprom_get_t get_data;
+ struct eeprom_read_t32 read_data;
+ struct eeprom_write_t32 write_data;
+ struct msm_eeprom_info_t32 eeprom_info;
+ } cfg;
+};
+
+struct msm_camera_i2c_seq_reg_setting32 {
+ compat_uptr_t reg_setting;
+ uint16_t size;
+ enum msm_camera_i2c_reg_addr_type addr_type;
+ uint16_t delay;
+};
+
+struct msm_camera_i2c_reg_setting32 {
+ compat_uptr_t reg_setting;
+ uint16_t size;
+ enum msm_camera_i2c_reg_addr_type addr_type;
+ enum msm_camera_i2c_data_type data_type;
+ uint16_t delay;
+};
+
+struct msm_camera_i2c_array_write_config32 {
+ struct msm_camera_i2c_reg_setting32 conf_array;
+ uint16_t slave_addr;
+};
+
+struct msm_actuator_tuning_params_t32 {
+ int16_t initial_code;
+ uint16_t pwd_step;
+ uint16_t region_size;
+ uint32_t total_steps;
+ compat_uptr_t region_params;
+};
+
+struct msm_actuator_params_t32 {
+ enum actuator_type act_type;
+ uint8_t reg_tbl_size;
+ uint16_t data_size;
+ uint16_t init_setting_size;
+ uint32_t i2c_addr;
+ enum i2c_freq_mode_t i2c_freq_mode;
+ enum msm_camera_i2c_reg_addr_type i2c_addr_type;
+ enum msm_camera_i2c_data_type i2c_data_type;
+ compat_uptr_t reg_tbl_params;
+ compat_uptr_t init_settings;
+ struct park_lens_data_t park_lens;
+};
+
+struct msm_actuator_set_info_t32 {
+ struct msm_actuator_params_t32 actuator_params;
+ struct msm_actuator_tuning_params_t32 af_tuning_params;
+};
+
+struct sensor_init_cfg_data32 {
+ enum msm_sensor_init_cfg_type_t cfgtype;
+ struct msm_sensor_info_t probed_info;
+ char entity_name[MAX_SENSOR_NAME];
+ union {
+ compat_uptr_t setting;
+ } cfg;
+};
+
+struct msm_actuator_move_params_t32 {
+ int8_t dir;
+ int8_t sign_dir;
+ int16_t dest_step_pos;
+ int32_t num_steps;
+ uint16_t curr_lens_pos;
+ compat_uptr_t ringing_params;
+};
+
+struct msm_actuator_cfg_data32 {
+ int cfgtype;
+ uint8_t is_af_supported;
+ union {
+ struct msm_actuator_move_params_t32 move;
+ struct msm_actuator_set_info_t32 set_info;
+ struct msm_actuator_get_info_t get_info;
+ struct msm_actuator_set_position_t setpos;
+ enum af_camera_name cam_name;
+ } cfg;
+};
+
+struct csiphy_cfg_data32 {
+ enum csiphy_cfg_type_t cfgtype;
+ union {
+ compat_uptr_t csiphy_params;
+ compat_uptr_t csi_lane_params;
+ } cfg;
+};
+
+struct sensorb_cfg_data32 {
+ int cfgtype;
+ union {
+ struct msm_sensor_info_t sensor_info;
+ struct msm_sensor_init_params sensor_init_params;
+ compat_uptr_t setting;
+ struct msm_sensor_i2c_sync_params sensor_i2c_sync_params;
+ } cfg;
+};
+
+struct msm_ois_params_t32 {
+ uint16_t data_size;
+ uint16_t setting_size;
+ uint32_t i2c_addr;
+ enum i2c_freq_mode_t i2c_freq_mode;
+ enum msm_camera_i2c_reg_addr_type i2c_addr_type;
+ enum msm_camera_i2c_data_type i2c_data_type;
+ compat_uptr_t settings;
+};
+
+struct msm_ois_set_info_t32 {
+ struct msm_ois_params_t32 ois_params;
+};
+
+struct msm_ois_cfg_data32 {
+ int cfgtype;
+ union {
+ struct msm_ois_set_info_t32 set_info;
+ compat_uptr_t settings;
+ } cfg;
+};
+
+struct msm_flash_init_info_t32 {
+ enum msm_flash_driver_type flash_driver_type;
+ uint32_t slave_addr;
+ enum i2c_freq_mode_t i2c_freq_mode;
+ compat_uptr_t power_setting_array;
+ compat_uptr_t settings;
+};
+
+struct msm_flash_cfg_data_t32 {
+ enum msm_flash_cfg_type_t cfg_type;
+ int32_t flash_current[MAX_LED_TRIGGERS];
+ int32_t flash_duration[MAX_LED_TRIGGERS];
+ union {
+ compat_uptr_t flash_init_info;
+ compat_uptr_t settings;
+ } cfg;
+};
+
+#define VIDIOC_MSM_ACTUATOR_CFG32 \
+ _IOWR('V', BASE_VIDIOC_PRIVATE + 6, struct msm_actuator_cfg_data32)
+
+#define VIDIOC_MSM_SENSOR_INIT_CFG32 \
+ _IOWR('V', BASE_VIDIOC_PRIVATE + 10, struct sensor_init_cfg_data32)
+
+#define VIDIOC_MSM_CSIPHY_IO_CFG32 \
+ _IOWR('V', BASE_VIDIOC_PRIVATE + 4, struct csiphy_cfg_data32)
+
+#define VIDIOC_MSM_SENSOR_CFG32 \
+ _IOWR('V', BASE_VIDIOC_PRIVATE + 1, struct sensorb_cfg_data32)
+
+#define VIDIOC_MSM_EEPROM_CFG32 \
+ _IOWR('V', BASE_VIDIOC_PRIVATE + 8, struct msm_eeprom_cfg_data32)
+
+#define VIDIOC_MSM_OIS_CFG32 \
+ _IOWR('V', BASE_VIDIOC_PRIVATE + 11, struct msm_ois_cfg_data32)
+
+#define VIDIOC_MSM_CSID_IO_CFG32 \
+ _IOWR('V', BASE_VIDIOC_PRIVATE + 5, struct csid_cfg_data32)
+
+#define VIDIOC_MSM_FLASH_CFG32 \
+ _IOWR('V', BASE_VIDIOC_PRIVATE + 13, struct msm_flash_cfg_data_t32)
+
+#define VIDIOC_MSM_IR_LED_CFG32 \
+ _IOWR('V', BASE_VIDIOC_PRIVATE + 14, struct msm_ir_led_cfg_data_t32)
+
+#define VIDIOC_MSM_IR_CUT_CFG32 \
+ _IOWR('V', BASE_VIDIOC_PRIVATE + 15, struct msm_ir_cut_cfg_data_t32)
+
+#define VIDIOC_MSM_LASER_LED_CFG32 \
+ _IOWR('V', BASE_VIDIOC_PRIVATE + 16, struct msm_laser_led_cfg_data_t32)
+
+#endif
+
+#endif
diff --git a/include/media/msm_fd.h b/include/media/msm_fd.h
new file mode 100644
index 0000000..81eaee1
--- /dev/null
+++ b/include/media/msm_fd.h
@@ -0,0 +1,37 @@
+/* Copyright (c) 2014-2018, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#ifndef __MSM_FD__
+#define __MSM_FD__
+
+#include <uapi/media/msm_fd.h>
+#include <linux/compat.h>
+
+#ifdef CONFIG_COMPAT
+/*
+ * struct msm_fd_result32 - Compat structure contain detected faces result.
+ * @frame_id: Frame id of requested result.
+ * @face_cnt: Number of result faces, driver can modify this value (to smaller)
+ * @face_data: Pointer to array of face data structures.
+ * Array size should not be smaller then face_cnt.
+ */
+struct msm_fd_result32 {
+ __u32 frame_id;
+ __u32 face_cnt;
+ compat_uptr_t face_data;
+};
+
+/* MSM FD compat private ioctl ID */
+#define VIDIOC_MSM_FD_GET_RESULT32 \
+ _IOWR('V', BASE_VIDIOC_PRIVATE, struct msm_fd_result32)
+#endif
+
+#endif /* __MSM_FD__ */
diff --git a/include/media/msmb_camera.h b/include/media/msmb_camera.h
new file mode 100644
index 0000000..eae2d01
--- /dev/null
+++ b/include/media/msmb_camera.h
@@ -0,0 +1,25 @@
+#ifndef __LINUX_MSMB_CAMERA_H
+#define __LINUX_MSMB_CAMERA_H
+
+#include <uapi/media/msmb_camera.h>
+
+#ifdef CONFIG_COMPAT
+#define MSM_CAM_V4L2_IOCTL_NOTIFY32 \
+ _IOW('V', BASE_VIDIOC_PRIVATE + 30, struct v4l2_event32)
+
+#define MSM_CAM_V4L2_IOCTL_NOTIFY_META32 \
+ _IOW('V', BASE_VIDIOC_PRIVATE + 31, struct v4l2_event32)
+
+#define MSM_CAM_V4L2_IOCTL_CMD_ACK32 \
+ _IOW('V', BASE_VIDIOC_PRIVATE + 32, struct v4l2_event32)
+
+#define MSM_CAM_V4L2_IOCTL_NOTIFY_ERROR32 \
+ _IOW('V', BASE_VIDIOC_PRIVATE + 33, struct v4l2_event32)
+
+#define MSM_CAM_V4L2_IOCTL_NOTIFY_DEBUG32 \
+ _IOW('V', BASE_VIDIOC_PRIVATE + 34, struct v4l2_event32)
+
+#endif
+
+#endif
+
diff --git a/include/media/msmb_generic_buf_mgr.h b/include/media/msmb_generic_buf_mgr.h
new file mode 100644
index 0000000..b3e1a02
--- /dev/null
+++ b/include/media/msmb_generic_buf_mgr.h
@@ -0,0 +1,49 @@
+/* Copyright (c) 2013-2016, 2018, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __MEDIA_MSMB_GENERIC_BUF_MGR_H__
+#define __MEDIA_MSMB_GENERIC_BUF_MGR_H__
+
+#include <uapi/media/msmb_generic_buf_mgr.h>
+#include <linux/compat.h>
+
+struct v4l2_subdev *msm_buf_mngr_get_subdev(void);
+
+#ifdef CONFIG_COMPAT
+
+struct msm_buf_mngr_info32_t {
+ uint32_t session_id;
+ uint32_t stream_id;
+ uint32_t frame_id;
+ struct compat_timeval timestamp;
+ uint32_t index;
+ uint32_t reserved;
+ enum msm_camera_buf_mngr_buf_type type;
+ struct msm_camera_user_buf_cont_t user_buf;
+};
+
+#define VIDIOC_MSM_BUF_MNGR_GET_BUF32 \
+ _IOWR('V', BASE_VIDIOC_PRIVATE + 33, struct msm_buf_mngr_info32_t)
+
+#define VIDIOC_MSM_BUF_MNGR_PUT_BUF32 \
+ _IOWR('V', BASE_VIDIOC_PRIVATE + 34, struct msm_buf_mngr_info32_t)
+
+#define VIDIOC_MSM_BUF_MNGR_BUF_DONE32 \
+ _IOWR('V', BASE_VIDIOC_PRIVATE + 35, struct msm_buf_mngr_info32_t)
+
+#define VIDIOC_MSM_BUF_MNGR_FLUSH32 \
+ _IOWR('V', BASE_VIDIOC_PRIVATE + 39, struct msm_buf_mngr_info32_t)
+
+#endif
+
+#endif
+
diff --git a/include/media/msmb_isp.h b/include/media/msmb_isp.h
new file mode 100644
index 0000000..6f5da29
--- /dev/null
+++ b/include/media/msmb_isp.h
@@ -0,0 +1,34 @@
+/* Copyright (c) 2014-2016, 2018, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#ifndef __MSMB_ISP__
+#define __MSMB_ISP__
+
+#include <uapi/media/msmb_isp.h>
+
+#ifdef CONFIG_COMPAT
+struct msm_isp_event_data32 {
+ struct compat_timeval timestamp;
+ struct compat_timeval mono_timestamp;
+ uint32_t frame_id;
+ union {
+ struct msm_isp_stats_event stats;
+ struct msm_isp_buf_event buf_done;
+ struct msm_isp_fetch_eng_event fetch_done;
+ struct msm_isp_error_info error_info;
+ struct msm_isp_output_info output_info;
+ struct msm_isp_sof_info sof_info;
+ } u;
+};
+#endif
+
+#endif
+
diff --git a/include/media/msmb_pproc.h b/include/media/msmb_pproc.h
new file mode 100644
index 0000000..1e677f9
--- /dev/null
+++ b/include/media/msmb_pproc.h
@@ -0,0 +1,155 @@
+#ifndef __MSMB_PPROC_H
+#define __MSMB_PPROC_H
+
+#include <uapi/media/msmb_pproc.h>
+
+#include <linux/compat.h>
+
+#define MSM_OUTPUT_BUF_CNT 8
+
+#ifdef CONFIG_COMPAT
+struct msm_cpp_frame_info32_t {
+ int32_t frame_id;
+ struct compat_timeval timestamp;
+ uint32_t inst_id;
+ uint32_t identity;
+ uint32_t client_id;
+ enum msm_cpp_frame_type frame_type;
+ uint32_t num_strips;
+ uint32_t msg_len;
+ compat_uint_t cpp_cmd_msg;
+ int src_fd;
+ int dst_fd;
+ struct compat_timeval in_time, out_time;
+ compat_caddr_t cookie;
+ compat_int_t status;
+ int32_t duplicate_output;
+ uint32_t duplicate_identity;
+ uint32_t feature_mask;
+ uint8_t we_disable;
+ struct msm_cpp_buffer_info_t input_buffer_info;
+ struct msm_cpp_buffer_info_t output_buffer_info[MSM_OUTPUT_BUF_CNT];
+ struct msm_cpp_buffer_info_t duplicate_buffer_info;
+ struct msm_cpp_buffer_info_t tnr_scratch_buffer_info[2];
+ uint32_t reserved;
+ uint8_t partial_frame_indicator;
+ /* the followings are used only for partial_frame type
+ * and is only used for offline frame processing and
+ * only if payload big enough and need to be split into partial_frame
+ * if first_payload, kernel acquires output buffer
+ * first payload must have the last stripe
+ * buffer addresses from 0 to last_stripe_index are updated.
+ * kernel updates payload with msg_len and stripe_info
+ * kernel sends top level, plane level, then only stripes
+ * starting with first_stripe_index and
+ * ends with last_stripe_index
+ * kernel then sends trailing flag at frame done,
+ * if last payload, kernel queues the output buffer to HAL
+ */
+ uint8_t first_payload;
+ uint8_t last_payload;
+ uint32_t first_stripe_index;
+ uint32_t last_stripe_index;
+ uint32_t stripe_info_offset;
+ uint32_t stripe_info;
+ struct msm_cpp_batch_info_t batch_info;
+};
+
+struct msm_cpp_clock_settings32_t {
+ compat_long_t clock_rate;
+ uint64_t avg;
+ uint64_t inst;
+};
+
+struct msm_cpp_stream_buff_info32_t {
+ uint32_t identity;
+ uint32_t num_buffs;
+ compat_caddr_t buffer_info;
+};
+
+struct msm_pproc_queue_buf_info32_t {
+ struct msm_buf_mngr_info32_t buff_mgr_info;
+ uint8_t is_buf_dirty;
+};
+
+struct cpp_hw_info_32_t {
+ uint32_t cpp_hw_version;
+ uint32_t cpp_hw_caps;
+ compat_long_t freq_tbl[MAX_FREQ_TBL];
+ uint32_t freq_tbl_count;
+};
+
+
+#define VIDIOC_MSM_CPP_CFG32 \
+ _IOWR('V', BASE_VIDIOC_PRIVATE, struct msm_camera_v4l2_ioctl32_t)
+
+#define VIDIOC_MSM_CPP_GET_EVENTPAYLOAD32 \
+ _IOWR('V', BASE_VIDIOC_PRIVATE + 1, struct msm_camera_v4l2_ioctl32_t)
+
+#define VIDIOC_MSM_CPP_GET_INST_INFO32 \
+ _IOWR('V', BASE_VIDIOC_PRIVATE + 2, struct msm_camera_v4l2_ioctl32_t)
+
+#define VIDIOC_MSM_CPP_LOAD_FIRMWARE32 \
+ _IOWR('V', BASE_VIDIOC_PRIVATE + 3, struct msm_camera_v4l2_ioctl32_t)
+
+#define VIDIOC_MSM_CPP_GET_HW_INFO32 \
+ _IOWR('V', BASE_VIDIOC_PRIVATE + 4, struct msm_camera_v4l2_ioctl32_t)
+
+#define VIDIOC_MSM_CPP_FLUSH_QUEUE32 \
+ _IOWR('V', BASE_VIDIOC_PRIVATE + 5, struct msm_camera_v4l2_ioctl32_t)
+
+#define VIDIOC_MSM_CPP_ENQUEUE_STREAM_BUFF_INFO32 \
+ _IOWR('V', BASE_VIDIOC_PRIVATE + 6, struct msm_camera_v4l2_ioctl32_t)
+
+#define VIDIOC_MSM_CPP_DEQUEUE_STREAM_BUFF_INFO32 \
+ _IOWR('V', BASE_VIDIOC_PRIVATE + 7, struct msm_camera_v4l2_ioctl32_t)
+
+#define VIDIOC_MSM_VPE_CFG32 \
+ _IOWR('V', BASE_VIDIOC_PRIVATE + 8, struct msm_camera_v4l2_ioctl32_t)
+
+#define VIDIOC_MSM_VPE_TRANSACTION_SETUP32 \
+ _IOWR('V', BASE_VIDIOC_PRIVATE + 9, struct msm_camera_v4l2_ioctl32_t)
+
+#define VIDIOC_MSM_VPE_GET_EVENTPAYLOAD32 \
+ _IOWR('V', BASE_VIDIOC_PRIVATE + 10, struct msm_camera_v4l2_ioctl32_t)
+
+#define VIDIOC_MSM_VPE_GET_INST_INFO32 \
+ _IOWR('V', BASE_VIDIOC_PRIVATE + 11, struct msm_camera_v4l2_ioctl32_t)
+
+#define VIDIOC_MSM_VPE_ENQUEUE_STREAM_BUFF_INFO32 \
+ _IOWR('V', BASE_VIDIOC_PRIVATE + 12, struct msm_camera_v4l2_ioctl32_t)
+
+#define VIDIOC_MSM_VPE_DEQUEUE_STREAM_BUFF_INFO32 \
+ _IOWR('V', BASE_VIDIOC_PRIVATE + 13, struct msm_camera_v4l2_ioctl32_t)
+
+#define VIDIOC_MSM_CPP_QUEUE_BUF32 \
+ _IOWR('V', BASE_VIDIOC_PRIVATE + 14, struct msm_camera_v4l2_ioctl32_t)
+
+#define VIDIOC_MSM_CPP_APPEND_STREAM_BUFF_INFO32 \
+ _IOWR('V', BASE_VIDIOC_PRIVATE + 15, struct msm_camera_v4l2_ioctl32_t)
+
+#define VIDIOC_MSM_CPP_SET_CLOCK32 \
+ _IOWR('V', BASE_VIDIOC_PRIVATE + 16, struct msm_camera_v4l2_ioctl32_t)
+
+#define VIDIOC_MSM_CPP_POP_STREAM_BUFFER32 \
+ _IOWR('V', BASE_VIDIOC_PRIVATE + 17, struct msm_camera_v4l2_ioctl32_t)
+
+#define VIDIOC_MSM_CPP_IOMMU_ATTACH32 \
+ _IOWR('V', BASE_VIDIOC_PRIVATE + 18, struct msm_camera_v4l2_ioctl32_t)
+
+#define VIDIOC_MSM_CPP_IOMMU_DETACH32 \
+ _IOWR('V', BASE_VIDIOC_PRIVATE + 19, struct msm_camera_v4l2_ioctl32_t)
+
+#define VIDIOC_MSM_CPP_DELETE_STREAM_BUFF32\
+ _IOWR('V', BASE_VIDIOC_PRIVATE + 20, struct msm_camera_v4l2_ioctl32_t)
+
+struct msm_camera_v4l2_ioctl32_t {
+ uint32_t id;
+ uint32_t len;
+ int32_t trans_code;
+ compat_caddr_t ioctl_ptr;
+};
+#endif
+
+#endif
+
diff --git a/include/soc/qcom/camera2.h b/include/soc/qcom/camera2.h
new file mode 100644
index 0000000..c529aff
--- /dev/null
+++ b/include/soc/qcom/camera2.h
@@ -0,0 +1,227 @@
+/* Copyright (c) 2011-2016, 2018, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __CAMERA2_H__
+#define __CAMERA2_H__
+
+#include <media/msm_cam_sensor.h>
+#include <linux/interrupt.h>
+#include <linux/of_platform.h>
+#include <linux/of_device.h>
+#include <linux/of.h>
+
+#define MAX_SPECIAL_SUPPORT_SIZE 10
+
+enum msm_camera_device_type_t {
+ MSM_CAMERA_I2C_DEVICE,
+ MSM_CAMERA_PLATFORM_DEVICE,
+ MSM_CAMERA_SPI_DEVICE,
+};
+
+enum msm_bus_perf_setting {
+ S_INIT,
+ S_PREVIEW,
+ S_VIDEO,
+ S_CAPTURE,
+ S_ZSL,
+ S_STEREO_VIDEO,
+ S_STEREO_CAPTURE,
+ S_DEFAULT,
+ S_LIVESHOT,
+ S_DUAL,
+ S_EXIT
+};
+
+struct msm_camera_slave_info {
+ uint16_t sensor_slave_addr;
+ uint16_t sensor_id_reg_addr;
+ uint16_t sensor_id;
+ uint16_t sensor_id_mask;
+};
+
+struct msm_cam_clk_info {
+ const char *clk_name;
+ long clk_rate;
+ uint32_t delay;
+};
+
+struct msm_pinctrl_info {
+ struct pinctrl *pinctrl;
+ struct pinctrl_state *gpio_state_active;
+ struct pinctrl_state *gpio_state_suspend;
+ bool use_pinctrl;
+};
+
+struct msm_cam_clk_setting {
+ struct msm_cam_clk_info *clk_info;
+ uint16_t num_clk_info;
+ uint8_t enable;
+};
+
+struct v4l2_subdev_info {
+ uint32_t code;
+ enum v4l2_colorspace colorspace;
+ uint16_t fmt;
+ uint16_t order;
+};
+
+struct msm_camera_gpio_num_info {
+ uint16_t gpio_num[SENSOR_GPIO_MAX];
+ uint8_t valid[SENSOR_GPIO_MAX];
+};
+
+struct msm_camera_gpio_conf {
+ void *cam_gpiomux_conf_tbl;
+ uint8_t cam_gpiomux_conf_tbl_size;
+ struct gpio *cam_gpio_common_tbl;
+ uint8_t cam_gpio_common_tbl_size;
+ struct gpio *cam_gpio_req_tbl;
+ uint8_t cam_gpio_req_tbl_size;
+ uint32_t gpio_no_mux;
+ uint32_t *camera_off_table;
+ uint8_t camera_off_table_size;
+ uint32_t *camera_on_table;
+ uint8_t camera_on_table_size;
+ struct msm_camera_gpio_num_info *gpio_num_info;
+};
+
+struct msm_camera_power_ctrl_t {
+ struct device *dev;
+ struct msm_sensor_power_setting *power_setting;
+ uint16_t power_setting_size;
+ struct msm_sensor_power_setting *power_down_setting;
+ uint16_t power_down_setting_size;
+ struct msm_camera_gpio_conf *gpio_conf;
+ struct camera_vreg_t *cam_vreg;
+ int num_vreg;
+ struct msm_camera_i2c_conf *i2c_conf;
+ struct clk **clk_ptr;
+ struct msm_cam_clk_info *clk_info;
+ struct msm_pinctrl_info pinctrl_info;
+ uint8_t cam_pinctrl_status;
+ size_t clk_info_size;
+};
+
+enum msm_camera_actuator_name {
+ MSM_ACTUATOR_MAIN_CAM_0,
+ MSM_ACTUATOR_MAIN_CAM_1,
+ MSM_ACTUATOR_MAIN_CAM_2,
+ MSM_ACTUATOR_MAIN_CAM_3,
+ MSM_ACTUATOR_MAIN_CAM_4,
+ MSM_ACTUATOR_MAIN_CAM_5,
+ MSM_ACTUATOR_WEB_CAM_0,
+ MSM_ACTUATOR_WEB_CAM_1,
+ MSM_ACTUATOR_WEB_CAM_2,
+};
+
+struct msm_actuator_info {
+ struct i2c_board_info const *board_info;
+ enum msm_camera_actuator_name cam_name;
+ int bus_id;
+ int vcm_pwd;
+ int vcm_enable;
+};
+enum msm_camera_i2c_mux_mode {
+ MODE_R,
+ MODE_L,
+ MODE_DUAL
+};
+
+struct msm_camera_i2c_conf {
+ uint8_t use_i2c_mux;
+ struct platform_device *mux_dev;
+ enum msm_camera_i2c_mux_mode i2c_mux_mode;
+};
+
+struct msm_camera_sensor_board_info {
+ const char *sensor_name;
+ const char *eeprom_name;
+ const char *actuator_name;
+ const char *ois_name;
+ const char *flash_name;
+ const char *special_support_sensors[MAX_SPECIAL_SUPPORT_SIZE];
+ int32_t special_support_size;
+ struct msm_camera_slave_info *slave_info;
+ struct msm_camera_csi_lane_params *csi_lane_params;
+ struct msm_camera_sensor_strobe_flash_data *strobe_flash_data;
+ struct msm_actuator_info *actuator_info;
+ struct msm_sensor_info_t *sensor_info;
+ const char *misc_regulator;
+ struct msm_camera_power_ctrl_t power_info;
+ struct msm_camera_sensor_slave_info *cam_slave_info;
+};
+
+enum msm_camera_i2c_cmd_type {
+ MSM_CAMERA_I2C_CMD_WRITE,
+ MSM_CAMERA_I2C_CMD_POLL,
+};
+
+struct msm_camera_i2c_reg_conf {
+ uint16_t reg_addr;
+ uint16_t reg_data;
+ enum msm_camera_i2c_data_type dt;
+ enum msm_camera_i2c_cmd_type cmd_type;
+ int16_t mask;
+};
+
+struct msm_camera_i2c_conf_array {
+ struct msm_camera_i2c_reg_conf *conf;
+ uint16_t size;
+ uint16_t delay;
+ enum msm_camera_i2c_data_type data_type;
+};
+
+struct eeprom_map_t {
+ uint32_t valid_size;
+ uint32_t addr;
+ uint32_t addr_t;
+ uint32_t data;
+ uint32_t data_t;
+ uint32_t delay;
+};
+
+struct eeprom_slave_add_t {
+ uint32_t addr;
+};
+
+struct msm_eeprom_memory_map_t {
+ struct eeprom_map_t page;
+ struct eeprom_map_t pageen;
+ struct eeprom_map_t poll;
+ struct eeprom_map_t mem;
+ struct eeprom_slave_add_t saddr;
+};
+
+struct msm_eeprom_memory_block_t {
+ struct msm_eeprom_memory_map_t *map;
+ uint32_t num_map; /* number of map blocks */
+ uint8_t *mapdata;
+ uint32_t num_data; /* size of total mapdata */
+};
+
+struct msm_eeprom_cmm_t {
+ uint32_t cmm_support;
+ uint32_t cmm_compression;
+ uint32_t cmm_offset;
+ uint32_t cmm_size;
+};
+
+struct msm_eeprom_board_info {
+ const char *eeprom_name;
+ uint16_t i2c_slaveaddr;
+ struct msm_camera_power_ctrl_t power_info;
+ struct msm_eeprom_cmm_t cmm_data;
+ enum i2c_freq_mode_t i2c_freq_mode;
+};
+
+#endif
diff --git a/include/soc/qcom/cx_ipeak.h b/include/soc/qcom/cx_ipeak.h
new file mode 100644
index 0000000..01fdcb4
--- /dev/null
+++ b/include/soc/qcom/cx_ipeak.h
@@ -0,0 +1,46 @@
+/* Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __SOC_COM_CX_IPEAK_H
+#define __SOC_COM_CX_IPEAK_H
+
+struct device_node;
+struct cx_ipeak_client;
+
+#ifndef CONFIG_QCOM_CX_IPEAK
+
+static inline struct cx_ipeak_client *cx_ipeak_register(
+ struct device_node *dev_node,
+ const char *client_name)
+{
+ return NULL;
+}
+
+static inline void cx_ipeak_unregister(struct cx_ipeak_client *client)
+{
+}
+
+static inline int cx_ipeak_update(struct cx_ipeak_client *ipeak_client,
+ bool vote)
+{
+ return 0;
+}
+#else
+
+struct cx_ipeak_client *cx_ipeak_register(struct device_node *dev_node,
+ const char *client_name);
+void cx_ipeak_unregister(struct cx_ipeak_client *client);
+int cx_ipeak_update(struct cx_ipeak_client *ipeak_client, bool vote);
+
+#endif
+
+#endif /*__SOC_COM_CX_IPEAK_H*/
diff --git a/include/trace/events/msm_cam.h b/include/trace/events/msm_cam.h
new file mode 100644
index 0000000..3fc1a29
--- /dev/null
+++ b/include/trace/events/msm_cam.h
@@ -0,0 +1,136 @@
+/* Copyright (c) 2016, 2018, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+#undef TRACE_SYSTEM
+#define TRACE_SYSTEM msm_cam
+
+#if !defined(_TRACE_MSM_VFE_H) || defined(TRACE_HEADER_MULTI_READ)
+#define _TRACE_MSM_VFE_H
+
+#include "msm_isp.h"
+#include <linux/types.h>
+#include <linux/tracepoint.h>
+
+#define STRING_LEN 80
+
+
+TRACE_EVENT(msm_cam_string,
+ TP_PROTO(const char *str),
+ TP_ARGS(str),
+ TP_STRUCT__entry(
+ __array(char, str, STRING_LEN)
+ ),
+ TP_fast_assign(
+ strlcpy(__entry->str, str, STRING_LEN);
+ ),
+ TP_printk("msm_cam: %s", __entry->str)
+);
+
+TRACE_EVENT(msm_cam_tasklet_debug_dump,
+ TP_PROTO(struct msm_vfe_irq_debug_info tasklet_state),
+ TP_ARGS(tasklet_state),
+ TP_STRUCT__entry(
+ __field(unsigned int, vfe_id)
+ __field(unsigned int, core_id)
+ __field(unsigned int, irq_status0)
+ __field(unsigned int, irq_status1)
+ __field(unsigned int, ping_pong_status)
+ __field(long, tv_sec)
+ __field(long, tv_usec)
+ ),
+ TP_fast_assign(
+ __entry->vfe_id = tasklet_state.vfe_id;
+ __entry->irq_status0 =
+ tasklet_state.irq_status0[tasklet_state.vfe_id];
+ __entry->irq_status1 =
+ tasklet_state.irq_status1[tasklet_state.vfe_id];
+ __entry->core_id = tasklet_state.core_id;
+ __entry->ping_pong_status =
+ tasklet_state.ping_pong_status[tasklet_state.vfe_id];
+ __entry->tv_sec =
+ tasklet_state.ts.buf_time.tv_sec;
+ __entry->tv_usec =
+ tasklet_state.ts.buf_time.tv_usec;
+ ),
+ TP_printk("vfe_id %d, core %d, irq_st0 0x%x, irq_st1 0x%x\n"
+ "pi_po_st 0x%x, time %ld:%ld",
+ __entry->vfe_id,
+ __entry->core_id,
+ __entry->irq_status0,
+ __entry->irq_status1,
+ __entry->ping_pong_status,
+ __entry->tv_sec,
+ __entry->tv_usec
+ )
+);
+
+TRACE_EVENT(msm_cam_ping_pong_debug_dump,
+ TP_PROTO(struct msm_vfe_irq_debug_info ping_pong_state),
+ TP_ARGS(ping_pong_state),
+ TP_STRUCT__entry(
+ __field(unsigned int, curr_vfe_id)
+ __field(unsigned int, curr_irq_status0)
+ __field(unsigned int, curr_irq_status1)
+ __field(unsigned int, curr_ping_pong_status)
+ __field(unsigned int, othr_vfe_id)
+ __field(unsigned int, othr_irq_status0)
+ __field(unsigned int, othr_irq_status1)
+ __field(unsigned int, othr_ping_pong_status)
+ __field(long, othr_tv_sec)
+ __field(long, othr_tv_usec)
+ __field(unsigned int, core_id)
+ ),
+ TP_fast_assign(
+ __entry->curr_vfe_id =
+ ping_pong_state.vfe_id;
+ __entry->curr_irq_status0 =
+ ping_pong_state.irq_status0[ping_pong_state.vfe_id];
+ __entry->curr_irq_status1 =
+ ping_pong_state.irq_status1[ping_pong_state.vfe_id];
+ __entry->curr_ping_pong_status =
+ ping_pong_state.
+ ping_pong_status[ping_pong_state.vfe_id];
+ __entry->othr_vfe_id =
+ !ping_pong_state.vfe_id;
+ __entry->othr_irq_status0 =
+ ping_pong_state.irq_status0[!ping_pong_state.vfe_id];
+ __entry->othr_irq_status1 =
+ ping_pong_state.irq_status1[!ping_pong_state.vfe_id];
+ __entry->othr_ping_pong_status =
+ ping_pong_state.
+ ping_pong_status[!ping_pong_state.vfe_id];
+ __entry->othr_tv_sec =
+ ping_pong_state.ts.buf_time.tv_sec;
+ __entry->othr_tv_usec =
+ ping_pong_state.ts.buf_time.tv_usec;
+ __entry->core_id = ping_pong_state.core_id;
+ ),
+ TP_printk("vfe_id %d, irq_st0 0x%x, irq_st1 0x%x, pi_po_st 0x%x\n"
+ "other vfe_id %d, irq_st0 0x%x, irq_st1 0x%x\n"
+ "pi_po_st 0x%x, time %ld:%ld core %d",
+ __entry->curr_vfe_id,
+ __entry->curr_irq_status0,
+ __entry->curr_irq_status1,
+ __entry->curr_ping_pong_status,
+ __entry->othr_vfe_id,
+ __entry->othr_irq_status0,
+ __entry->othr_irq_status1,
+ __entry->othr_ping_pong_status,
+ __entry->othr_tv_sec,
+ __entry->othr_tv_usec,
+ __entry->core_id
+ )
+);
+
+#endif /* _MSM_CAM_TRACE_H */
+/* This part must be outside protection */
+#include <trace/define_trace.h>
diff --git a/include/uapi/linux/videodev2.h b/include/uapi/linux/videodev2.h
index d8a954e..8a2a315 100644
--- a/include/uapi/linux/videodev2.h
+++ b/include/uapi/linux/videodev2.h
@@ -2,7 +2,7 @@
* Video for Linux Two header file
*
* Copyright (C) 1999-2012 the contributors
- * Copyright (c) 2016-2018 The Linux Foundation. All rights reserved.
+ * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -594,6 +594,14 @@
#define V4L2_PIX_FMT_SGRBG12 v4l2_fourcc('B', 'A', '1', '2') /* 12 GRGR.. BGBG.. */
#define V4L2_PIX_FMT_SRGGB12 v4l2_fourcc('R', 'G', '1', '2') /* 12 RGRG.. GBGB.. */
#define V4L2_PIX_FMT_SBGGR16 v4l2_fourcc('B', 'Y', 'R', '2') /* 16 BGBG.. GRGR.. */
+#define V4L2_PIX_FMT_SBGGR10DPCM6 v4l2_fourcc('b', 'B', 'A', '6')
+#define V4L2_PIX_FMT_SGBRG10DPCM6 v4l2_fourcc('b', 'G', 'A', '6')
+#define V4L2_PIX_FMT_SGRBG10DPCM6 v4l2_fourcc('B', 'D', '1', '6')
+#define V4L2_PIX_FMT_SRGGB10DPCM6 v4l2_fourcc('b', 'R', 'A', '6')
+#define V4L2_PIX_FMT_SBGGRPLAIN16 v4l2_fourcc('B', 'G', '1', '6')
+#define V4L2_PIX_FMT_SGBRGPLAIN16 v4l2_fourcc('G', 'B', '1', '6')
+#define V4L2_PIX_FMT_SGRBGPLAIN16 v4l2_fourcc('G', 'R', '1', '6')
+#define V4L2_PIX_FMT_SRGGBPLAIN16 v4l2_fourcc('R', 'G', '1', '6')
/* compressed formats */
#define V4L2_PIX_FMT_MJPEG v4l2_fourcc('M', 'J', 'P', 'G') /* Motion-JPEG */
diff --git a/include/uapi/media/Kbuild b/include/uapi/media/Kbuild
index 1e087a1..1aa2a19 100644
--- a/include/uapi/media/Kbuild
+++ b/include/uapi/media/Kbuild
@@ -15,3 +15,16 @@
header-y += radio-iris.h
header-y += radio-iris-commands.h
header-y += cam_lrme.h
+header-y += msm_cam_sensor.h
+header-y += msm_camera.h
+header-y += msm_camsensor_sdk.h
+header-y += msm_fd.h
+header-y += msm_isp.h
+header-y += msm_jpeg.h
+header-y += msm_jpeg_dma.h
+header-y += msm_media_info.h
+header-y += msmb_camera.h
+header-y += msmb_generic_buf_mgr.h
+header-y += msmb_isp.h
+header-y += msmb_ispif.h
+header-y += msmb_pproc.h
\ No newline at end of file
diff --git a/include/uapi/media/msm_cam_sensor.h b/include/uapi/media/msm_cam_sensor.h
new file mode 100644
index 0000000..bd5b906
--- /dev/null
+++ b/include/uapi/media/msm_cam_sensor.h
@@ -0,0 +1,635 @@
+#ifndef __UAPI_LINUX_MSM_CAM_SENSOR_H
+#define __UAPI_LINUX_MSM_CAM_SENSOR_H
+
+#include <linux/v4l2-mediabus.h>
+#include <media/msm_camsensor_sdk.h>
+
+#include <linux/types.h>
+#include <linux/i2c.h>
+
+#define I2C_SEQ_REG_SETTING_MAX 5
+
+#define MSM_SENSOR_MCLK_8HZ 8000000
+#define MSM_SENSOR_MCLK_16HZ 16000000
+#define MSM_SENSOR_MCLK_24HZ 24000000
+
+#define MAX_SENSOR_NAME 32
+#define MAX_ACTUATOR_AF_TOTAL_STEPS 1024
+
+#define MAX_OIS_MOD_NAME_SIZE 32
+#define MAX_OIS_NAME_SIZE 32
+#define MAX_OIS_REG_SETTINGS 800
+
+#define MOVE_NEAR 0
+#define MOVE_FAR 1
+
+#define MSM_ACTUATOR_MOVE_SIGNED_FAR -1
+#define MSM_ACTUATOR_MOVE_SIGNED_NEAR 1
+
+#define MAX_ACTUATOR_REGION 5
+
+#define MAX_EEPROM_NAME 32
+
+#define MAX_AF_ITERATIONS 3
+#define MAX_NUMBER_OF_STEPS 47
+#define MAX_REGULATOR 5
+
+/*msm_flash_query_data_t query types*/
+#define FLASH_QUERY_CURRENT 1
+
+#define MSM_V4L2_PIX_FMT_META v4l2_fourcc('M', 'E', 'T', 'A') /* META */
+#define MSM_V4L2_PIX_FMT_META10 v4l2_fourcc('M', 'E', '1', '0') /* META10 */
+#define MSM_V4L2_PIX_FMT_SBGGR14 v4l2_fourcc('B', 'G', '1', '4')
+ /* 14 BGBG.. GRGR.. */
+#define MSM_V4L2_PIX_FMT_SGBRG14 v4l2_fourcc('G', 'B', '1', '4')
+ /* 14 GBGB.. RGRG.. */
+#define MSM_V4L2_PIX_FMT_SGRBG14 v4l2_fourcc('B', 'A', '1', '4')
+ /* 14 GRGR.. BGBG.. */
+#define MSM_V4L2_PIX_FMT_SRGGB14 v4l2_fourcc('R', 'G', '1', '4')
+ /* 14 RGRG.. GBGB.. */
+
+enum flash_type {
+ LED_FLASH = 1,
+ STROBE_FLASH,
+ GPIO_FLASH
+};
+
+enum msm_sensor_resolution_t {
+ MSM_SENSOR_RES_FULL,
+ MSM_SENSOR_RES_QTR,
+ MSM_SENSOR_RES_2,
+ MSM_SENSOR_RES_3,
+ MSM_SENSOR_RES_4,
+ MSM_SENSOR_RES_5,
+ MSM_SENSOR_RES_6,
+ MSM_SENSOR_RES_7,
+ MSM_SENSOR_INVALID_RES,
+};
+
+enum msm_camera_stream_type_t {
+ MSM_CAMERA_STREAM_PREVIEW,
+ MSM_CAMERA_STREAM_SNAPSHOT,
+ MSM_CAMERA_STREAM_VIDEO,
+ MSM_CAMERA_STREAM_INVALID,
+};
+
+enum sensor_sub_module_t {
+ SUB_MODULE_SENSOR,
+ SUB_MODULE_CHROMATIX,
+ SUB_MODULE_ACTUATOR,
+ SUB_MODULE_EEPROM,
+ SUB_MODULE_LED_FLASH,
+ SUB_MODULE_STROBE_FLASH,
+ SUB_MODULE_CSID,
+ SUB_MODULE_CSID_3D,
+ SUB_MODULE_CSIPHY,
+ SUB_MODULE_CSIPHY_3D,
+ SUB_MODULE_OIS,
+ SUB_MODULE_EXT,
+ SUB_MODULE_IR_LED,
+ SUB_MODULE_IR_CUT,
+ SUB_MODULE_LASER_LED,
+ SUB_MODULE_MAX,
+};
+
+enum {
+ MSM_CAMERA_EFFECT_MODE_OFF,
+ MSM_CAMERA_EFFECT_MODE_MONO,
+ MSM_CAMERA_EFFECT_MODE_NEGATIVE,
+ MSM_CAMERA_EFFECT_MODE_SOLARIZE,
+ MSM_CAMERA_EFFECT_MODE_SEPIA,
+ MSM_CAMERA_EFFECT_MODE_POSTERIZE,
+ MSM_CAMERA_EFFECT_MODE_WHITEBOARD,
+ MSM_CAMERA_EFFECT_MODE_BLACKBOARD,
+ MSM_CAMERA_EFFECT_MODE_AQUA,
+ MSM_CAMERA_EFFECT_MODE_EMBOSS,
+ MSM_CAMERA_EFFECT_MODE_SKETCH,
+ MSM_CAMERA_EFFECT_MODE_NEON,
+ MSM_CAMERA_EFFECT_MODE_MAX
+};
+
+enum {
+ MSM_CAMERA_WB_MODE_AUTO,
+ MSM_CAMERA_WB_MODE_CUSTOM,
+ MSM_CAMERA_WB_MODE_INCANDESCENT,
+ MSM_CAMERA_WB_MODE_FLUORESCENT,
+ MSM_CAMERA_WB_MODE_WARM_FLUORESCENT,
+ MSM_CAMERA_WB_MODE_DAYLIGHT,
+ MSM_CAMERA_WB_MODE_CLOUDY_DAYLIGHT,
+ MSM_CAMERA_WB_MODE_TWILIGHT,
+ MSM_CAMERA_WB_MODE_SHADE,
+ MSM_CAMERA_WB_MODE_OFF,
+ MSM_CAMERA_WB_MODE_MAX
+};
+
+enum {
+ MSM_CAMERA_SCENE_MODE_OFF,
+ MSM_CAMERA_SCENE_MODE_AUTO,
+ MSM_CAMERA_SCENE_MODE_LANDSCAPE,
+ MSM_CAMERA_SCENE_MODE_SNOW,
+ MSM_CAMERA_SCENE_MODE_BEACH,
+ MSM_CAMERA_SCENE_MODE_SUNSET,
+ MSM_CAMERA_SCENE_MODE_NIGHT,
+ MSM_CAMERA_SCENE_MODE_PORTRAIT,
+ MSM_CAMERA_SCENE_MODE_BACKLIGHT,
+ MSM_CAMERA_SCENE_MODE_SPORTS,
+ MSM_CAMERA_SCENE_MODE_ANTISHAKE,
+ MSM_CAMERA_SCENE_MODE_FLOWERS,
+ MSM_CAMERA_SCENE_MODE_CANDLELIGHT,
+ MSM_CAMERA_SCENE_MODE_FIREWORKS,
+ MSM_CAMERA_SCENE_MODE_PARTY,
+ MSM_CAMERA_SCENE_MODE_NIGHT_PORTRAIT,
+ MSM_CAMERA_SCENE_MODE_THEATRE,
+ MSM_CAMERA_SCENE_MODE_ACTION,
+ MSM_CAMERA_SCENE_MODE_AR,
+ MSM_CAMERA_SCENE_MODE_FACE_PRIORITY,
+ MSM_CAMERA_SCENE_MODE_BARCODE,
+ MSM_CAMERA_SCENE_MODE_HDR,
+ MSM_CAMERA_SCENE_MODE_MAX
+};
+
+enum csid_cfg_type_t {
+ CSID_INIT,
+ CSID_CFG,
+ CSID_TESTMODE_CFG,
+ CSID_RELEASE,
+};
+
+enum csiphy_cfg_type_t {
+ CSIPHY_INIT,
+ CSIPHY_CFG,
+ CSIPHY_RELEASE,
+};
+
+enum camera_vreg_type {
+ VREG_TYPE_DEFAULT,
+ VREG_TYPE_CUSTOM,
+};
+
+enum sensor_af_t {
+ SENSOR_AF_FOCUSSED,
+ SENSOR_AF_NOT_FOCUSSED,
+};
+
+enum cci_i2c_master_t {
+ MASTER_0,
+ MASTER_1,
+ MASTER_MAX,
+};
+
+struct msm_camera_i2c_array_write_config {
+ struct msm_camera_i2c_reg_setting conf_array;
+ uint16_t slave_addr;
+};
+
+struct msm_camera_i2c_read_config {
+ uint16_t slave_addr;
+ uint16_t reg_addr;
+ enum msm_camera_i2c_reg_addr_type addr_type;
+ enum msm_camera_i2c_data_type data_type;
+ uint16_t data;
+};
+
+struct msm_camera_csi2_params {
+ struct msm_camera_csid_params csid_params;
+ struct msm_camera_csiphy_params csiphy_params;
+ uint8_t csi_clk_scale_enable;
+};
+
+struct msm_camera_csi_lane_params {
+ uint16_t csi_lane_assign;
+ uint16_t csi_lane_mask;
+};
+
+struct csi_lane_params_t {
+ uint16_t csi_lane_assign;
+ uint8_t csi_lane_mask;
+ uint8_t csi_if;
+ int8_t csid_core[2];
+ uint8_t csi_phy_sel;
+};
+
+struct msm_sensor_info_t {
+ char sensor_name[MAX_SENSOR_NAME];
+ uint32_t session_id;
+ int32_t subdev_id[SUB_MODULE_MAX];
+ int32_t subdev_intf[SUB_MODULE_MAX];
+ uint8_t is_mount_angle_valid;
+ uint32_t sensor_mount_angle;
+ int modes_supported;
+ enum camb_position_t position;
+};
+
+struct camera_vreg_t {
+ const char *reg_name;
+ int min_voltage;
+ int max_voltage;
+ int op_mode;
+ uint32_t delay;
+ const char *custom_vreg_name;
+ enum camera_vreg_type type;
+};
+
+struct sensorb_cfg_data {
+ int cfgtype;
+ union {
+ struct msm_sensor_info_t sensor_info;
+ struct msm_sensor_init_params sensor_init_params;
+ void *setting;
+ struct msm_sensor_i2c_sync_params sensor_i2c_sync_params;
+ } cfg;
+};
+
+struct csid_cfg_data {
+ enum csid_cfg_type_t cfgtype;
+ union {
+ uint32_t csid_version;
+ struct msm_camera_csid_params *csid_params;
+ struct msm_camera_csid_testmode_parms *csid_testmode_params;
+ } cfg;
+};
+
+struct csiphy_cfg_data {
+ enum csiphy_cfg_type_t cfgtype;
+ union {
+ struct msm_camera_csiphy_params __user *csiphy_params;
+ struct msm_camera_csi_lane_params *csi_lane_params;
+ } cfg;
+};
+
+enum eeprom_cfg_type_t {
+ CFG_EEPROM_GET_INFO,
+ CFG_EEPROM_GET_CAL_DATA,
+ CFG_EEPROM_READ_CAL_DATA,
+ CFG_EEPROM_WRITE_DATA,
+ CFG_EEPROM_GET_MM_INFO,
+ CFG_EEPROM_INIT,
+};
+
+struct eeprom_get_t {
+ uint32_t num_bytes;
+};
+
+struct eeprom_read_t {
+ uint8_t *dbuffer;
+ uint32_t num_bytes;
+};
+
+struct eeprom_write_t {
+ uint8_t *dbuffer;
+ uint32_t num_bytes;
+};
+
+struct eeprom_get_cmm_t {
+ uint32_t cmm_support;
+ uint32_t cmm_compression;
+ uint32_t cmm_size;
+};
+
+struct msm_eeprom_info_t {
+ struct msm_sensor_power_setting_array *power_setting_array;
+ enum i2c_freq_mode_t i2c_freq_mode;
+ struct msm_eeprom_memory_map_array *mem_map_array;
+};
+
+struct msm_ir_led_cfg_data_t {
+ enum msm_ir_led_cfg_type_t cfg_type;
+ int32_t pwm_duty_on_ns;
+ int32_t pwm_period_ns;
+};
+
+struct msm_ir_cut_cfg_data_t {
+ enum msm_ir_cut_cfg_type_t cfg_type;
+};
+
+struct msm_laser_led_cfg_data_t {
+ enum msm_laser_led_cfg_type_t cfg_type;
+ void __user *setting;
+ void __user *debug_reg;
+ uint32_t debug_reg_size;
+ uint16_t i2c_addr;
+ enum i2c_freq_mode_t i2c_freq_mode;
+};
+
+struct msm_eeprom_cfg_data {
+ enum eeprom_cfg_type_t cfgtype;
+ uint8_t is_supported;
+ union {
+ char eeprom_name[MAX_EEPROM_NAME];
+ struct eeprom_get_t get_data;
+ struct eeprom_read_t read_data;
+ struct eeprom_write_t write_data;
+ struct eeprom_get_cmm_t get_cmm_data;
+ struct msm_eeprom_info_t eeprom_info;
+ } cfg;
+};
+
+enum msm_sensor_cfg_type_t {
+ CFG_SET_SLAVE_INFO,
+ CFG_SLAVE_READ_I2C,
+ CFG_WRITE_I2C_ARRAY,
+ CFG_SLAVE_WRITE_I2C_ARRAY,
+ CFG_WRITE_I2C_SEQ_ARRAY,
+ CFG_POWER_UP,
+ CFG_POWER_DOWN,
+ CFG_SET_STOP_STREAM_SETTING,
+ CFG_GET_SENSOR_INFO,
+ CFG_GET_SENSOR_INIT_PARAMS,
+ CFG_SET_INIT_SETTING,
+ CFG_SET_RESOLUTION,
+ CFG_SET_STOP_STREAM,
+ CFG_SET_START_STREAM,
+ CFG_SET_SATURATION,
+ CFG_SET_CONTRAST,
+ CFG_SET_SHARPNESS,
+ CFG_SET_ISO,
+ CFG_SET_EXPOSURE_COMPENSATION,
+ CFG_SET_ANTIBANDING,
+ CFG_SET_BESTSHOT_MODE,
+ CFG_SET_EFFECT,
+ CFG_SET_WHITE_BALANCE,
+ CFG_SET_AUTOFOCUS,
+ CFG_CANCEL_AUTOFOCUS,
+ CFG_SET_STREAM_TYPE,
+ CFG_SET_I2C_SYNC_PARAM,
+ CFG_WRITE_I2C_ARRAY_ASYNC,
+ CFG_WRITE_I2C_ARRAY_SYNC,
+ CFG_WRITE_I2C_ARRAY_SYNC_BLOCK,
+};
+
+enum msm_actuator_cfg_type_t {
+ CFG_GET_ACTUATOR_INFO,
+ CFG_SET_ACTUATOR_INFO,
+ CFG_SET_DEFAULT_FOCUS,
+ CFG_MOVE_FOCUS,
+ CFG_SET_POSITION,
+ CFG_ACTUATOR_POWERDOWN,
+ CFG_ACTUATOR_POWERUP,
+ CFG_ACTUATOR_INIT,
+};
+
+struct msm_ois_opcode {
+ uint32_t prog;
+ uint32_t coeff;
+ uint32_t pheripheral;
+ uint32_t memory;
+};
+
+enum msm_ois_cfg_type_t {
+ CFG_OIS_INIT,
+ CFG_OIS_POWERDOWN,
+ CFG_OIS_POWERUP,
+ CFG_OIS_CONTROL,
+ CFG_OIS_I2C_WRITE_SEQ_TABLE,
+};
+
+enum msm_ois_cfg_download_type_t {
+ CFG_OIS_DOWNLOAD,
+ CFG_OIS_DATA_CONFIG,
+};
+
+enum msm_ois_i2c_operation {
+ MSM_OIS_WRITE = 0,
+ MSM_OIS_POLL,
+ MSM_OIS_READ,
+};
+#define MSM_OIS_READ MSM_OIS_READ
+
+struct reg_settings_ois_t {
+ uint16_t reg_addr;
+ enum msm_camera_i2c_reg_addr_type addr_type;
+ uint32_t reg_data;
+ enum msm_camera_i2c_data_type data_type;
+ enum msm_ois_i2c_operation i2c_operation;
+ uint32_t delay;
+};
+
+struct msm_ois_params_t {
+ uint16_t data_size;
+ uint16_t setting_size;
+ uint32_t i2c_addr;
+ enum i2c_freq_mode_t i2c_freq_mode;
+ enum msm_camera_i2c_reg_addr_type i2c_addr_type;
+ enum msm_camera_i2c_data_type i2c_data_type;
+ struct reg_settings_ois_t __user *settings;
+};
+
+struct msm_ois_set_info_t {
+ struct msm_ois_params_t ois_params;
+};
+
+struct msm_actuator_move_params_t {
+ int8_t dir;
+ int8_t sign_dir;
+ int16_t dest_step_pos;
+ int32_t num_steps;
+ uint16_t curr_lens_pos;
+ struct damping_params_t __user *ringing_params;
+};
+
+struct msm_actuator_tuning_params_t {
+ int16_t initial_code;
+ uint16_t pwd_step;
+ uint16_t region_size;
+ uint32_t total_steps;
+ struct region_params_t __user *region_params;
+};
+
+struct park_lens_data_t {
+ uint32_t damping_step;
+ uint32_t damping_delay;
+ uint32_t hw_params;
+ uint32_t max_step;
+};
+
+struct msm_actuator_params_t {
+ enum actuator_type act_type;
+ uint8_t reg_tbl_size;
+ uint16_t data_size;
+ uint16_t init_setting_size;
+ uint32_t i2c_addr;
+ enum i2c_freq_mode_t i2c_freq_mode;
+ enum msm_camera_i2c_reg_addr_type i2c_addr_type;
+ enum msm_camera_i2c_data_type i2c_data_type;
+ struct msm_actuator_reg_params_t __user *reg_tbl_params;
+ struct reg_settings_t __user *init_settings;
+ struct park_lens_data_t park_lens;
+};
+
+struct msm_actuator_set_info_t {
+ struct msm_actuator_params_t actuator_params;
+ struct msm_actuator_tuning_params_t af_tuning_params;
+};
+
+struct msm_actuator_get_info_t {
+ uint32_t focal_length_num;
+ uint32_t focal_length_den;
+ uint32_t f_number_num;
+ uint32_t f_number_den;
+ uint32_t f_pix_num;
+ uint32_t f_pix_den;
+ uint32_t total_f_dist_num;
+ uint32_t total_f_dist_den;
+ uint32_t hor_view_angle_num;
+ uint32_t hor_view_angle_den;
+ uint32_t ver_view_angle_num;
+ uint32_t ver_view_angle_den;
+};
+
+enum af_camera_name {
+ ACTUATOR_MAIN_CAM_0,
+ ACTUATOR_MAIN_CAM_1,
+ ACTUATOR_MAIN_CAM_2,
+ ACTUATOR_MAIN_CAM_3,
+ ACTUATOR_MAIN_CAM_4,
+ ACTUATOR_MAIN_CAM_5,
+ ACTUATOR_WEB_CAM_0,
+ ACTUATOR_WEB_CAM_1,
+ ACTUATOR_WEB_CAM_2,
+};
+
+struct msm_ois_slave_info {
+ char ois_name[MAX_OIS_NAME_SIZE];
+ uint32_t i2c_addr;
+ struct msm_ois_opcode opcode;
+};
+struct msm_ois_cfg_data {
+ int cfgtype;
+ union {
+ struct msm_ois_set_info_t set_info;
+ struct msm_camera_i2c_seq_reg_setting *settings;
+ } cfg;
+};
+
+struct msm_ois_cfg_download_data {
+ int cfgtype;
+ struct msm_ois_slave_info slave_info;
+};
+
+struct msm_actuator_set_position_t {
+ uint16_t number_of_steps;
+ uint32_t hw_params;
+ uint16_t pos[MAX_NUMBER_OF_STEPS];
+ uint16_t delay[MAX_NUMBER_OF_STEPS];
+};
+
+struct msm_actuator_cfg_data {
+ int cfgtype;
+ uint8_t is_af_supported;
+ union {
+ struct msm_actuator_move_params_t move;
+ struct msm_actuator_set_info_t set_info;
+ struct msm_actuator_get_info_t get_info;
+ struct msm_actuator_set_position_t setpos;
+ enum af_camera_name cam_name;
+ } cfg;
+};
+
+enum msm_camera_led_config_t {
+ MSM_CAMERA_LED_OFF,
+ MSM_CAMERA_LED_LOW,
+ MSM_CAMERA_LED_HIGH,
+ MSM_CAMERA_LED_INIT,
+ MSM_CAMERA_LED_RELEASE,
+};
+
+struct msm_camera_led_cfg_t {
+ enum msm_camera_led_config_t cfgtype;
+ int32_t torch_current[MAX_LED_TRIGGERS];
+ int32_t flash_current[MAX_LED_TRIGGERS];
+ int32_t flash_duration[MAX_LED_TRIGGERS];
+};
+
+struct msm_flash_init_info_t {
+ enum msm_flash_driver_type flash_driver_type;
+ uint32_t slave_addr;
+ enum i2c_freq_mode_t i2c_freq_mode;
+ struct msm_sensor_power_setting_array __user *power_setting_array;
+ struct msm_camera_i2c_reg_setting_array __user *settings;
+};
+
+struct msm_flash_cfg_data_t {
+ enum msm_flash_cfg_type_t cfg_type;
+ int32_t flash_current[MAX_LED_TRIGGERS];
+ int32_t flash_duration[MAX_LED_TRIGGERS];
+ union {
+ struct msm_flash_init_info_t *flash_init_info;
+ struct msm_camera_i2c_reg_setting_array __user *settings;
+ } cfg;
+};
+
+struct msm_flash_query_data_t {
+ int32_t flags;
+ int32_t query_type;
+ int32_t max_avail_curr;
+};
+
+/* sensor init structures and enums */
+enum msm_sensor_init_cfg_type_t {
+ CFG_SINIT_PROBE,
+ CFG_SINIT_PROBE_DONE,
+ CFG_SINIT_PROBE_WAIT_DONE,
+};
+
+struct sensor_init_cfg_data {
+ enum msm_sensor_init_cfg_type_t cfgtype;
+ struct msm_sensor_info_t probed_info;
+ char entity_name[MAX_SENSOR_NAME];
+ union {
+ void *setting;
+ } cfg;
+};
+
+#define VIDIOC_MSM_SENSOR_CFG \
+ _IOWR('V', BASE_VIDIOC_PRIVATE + 1, struct sensorb_cfg_data)
+
+#define VIDIOC_MSM_SENSOR_RELEASE \
+ _IO('V', BASE_VIDIOC_PRIVATE + 2)
+
+#define VIDIOC_MSM_SENSOR_GET_SUBDEV_ID \
+ _IOWR('V', BASE_VIDIOC_PRIVATE + 3, uint32_t)
+
+#define VIDIOC_MSM_CSIPHY_IO_CFG \
+ _IOWR('V', BASE_VIDIOC_PRIVATE + 4, struct csiphy_cfg_data)
+
+#define VIDIOC_MSM_CSID_IO_CFG \
+ _IOWR('V', BASE_VIDIOC_PRIVATE + 5, struct csid_cfg_data)
+
+#define VIDIOC_MSM_ACTUATOR_CFG \
+ _IOWR('V', BASE_VIDIOC_PRIVATE + 6, struct msm_actuator_cfg_data)
+
+#define VIDIOC_MSM_FLASH_LED_DATA_CFG \
+ _IOWR('V', BASE_VIDIOC_PRIVATE + 7, struct msm_camera_led_cfg_t)
+
+#define VIDIOC_MSM_EEPROM_CFG \
+ _IOWR('V', BASE_VIDIOC_PRIVATE + 8, struct msm_eeprom_cfg_data)
+
+#define VIDIOC_MSM_SENSOR_GET_AF_STATUS \
+ _IOWR('V', BASE_VIDIOC_PRIVATE + 9, uint32_t)
+
+#define VIDIOC_MSM_SENSOR_INIT_CFG \
+ _IOWR('V', BASE_VIDIOC_PRIVATE + 10, struct sensor_init_cfg_data)
+
+#define VIDIOC_MSM_OIS_CFG \
+ _IOWR('V', BASE_VIDIOC_PRIVATE + 11, struct msm_ois_cfg_data)
+
+#define VIDIOC_MSM_FLASH_CFG \
+ _IOWR('V', BASE_VIDIOC_PRIVATE + 13, struct msm_flash_cfg_data_t)
+
+#define VIDIOC_MSM_OIS_CFG_DOWNLOAD \
+ _IOWR('V', BASE_VIDIOC_PRIVATE + 14, struct msm_ois_cfg_download_data)
+
+#define VIDIOC_MSM_FLASH_QUERY_DATA \
+ _IOWR('V', BASE_VIDIOC_PRIVATE + 15, struct msm_flash_query_data_t)
+
+#define VIDIOC_MSM_IR_LED_CFG \
+ _IOWR('V', BASE_VIDIOC_PRIVATE + 15, struct msm_ir_led_cfg_data_t)
+
+#define VIDIOC_MSM_IR_CUT_CFG \
+ _IOWR('V', BASE_VIDIOC_PRIVATE + 15, struct msm_ir_cut_cfg_data_t)
+
+#define VIDIOC_MSM_LASER_LED_CFG \
+ _IOWR('V', BASE_VIDIOC_PRIVATE + 16, struct msm_laser_led_cfg_data_t)
+
+#endif
+
diff --git a/include/uapi/media/msm_camera.h b/include/uapi/media/msm_camera.h
new file mode 100644
index 0000000..d282586
--- /dev/null
+++ b/include/uapi/media/msm_camera.h
@@ -0,0 +1,2229 @@
+/* Copyright (c) 2009-2012, 2014-2016, 2018, The Linux Foundation.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+#ifndef __UAPI_MSM_CAMERA_H
+#define __UAPI_MSM_CAMERA_H
+
+#include <linux/videodev2.h>
+#include <linux/types.h>
+#include <linux/ioctl.h>
+
+#include <linux/msm_ion.h>
+
+#define BIT(nr) (1UL << (nr))
+
+#define MSM_CAM_IOCTL_MAGIC 'm'
+
+#define MAX_SERVER_PAYLOAD_LENGTH 8192
+
+#define MSM_CAM_IOCTL_GET_SENSOR_INFO \
+ _IOR(MSM_CAM_IOCTL_MAGIC, 1, struct msm_camsensor_info *)
+
+#define MSM_CAM_IOCTL_REGISTER_PMEM \
+ _IOW(MSM_CAM_IOCTL_MAGIC, 2, struct msm_pmem_info *)
+
+#define MSM_CAM_IOCTL_UNREGISTER_PMEM \
+ _IOW(MSM_CAM_IOCTL_MAGIC, 3, unsigned int)
+
+#define MSM_CAM_IOCTL_CTRL_COMMAND \
+ _IOW(MSM_CAM_IOCTL_MAGIC, 4, struct msm_ctrl_cmd *)
+
+#define MSM_CAM_IOCTL_CONFIG_VFE \
+ _IOW(MSM_CAM_IOCTL_MAGIC, 5, struct msm_camera_vfe_cfg_cmd *)
+
+#define MSM_CAM_IOCTL_GET_STATS \
+ _IOR(MSM_CAM_IOCTL_MAGIC, 6, struct msm_camera_stats_event_ctrl *)
+
+#define MSM_CAM_IOCTL_GETFRAME \
+ _IOR(MSM_CAM_IOCTL_MAGIC, 7, struct msm_camera_get_frame *)
+
+#define MSM_CAM_IOCTL_ENABLE_VFE \
+ _IOW(MSM_CAM_IOCTL_MAGIC, 8, struct camera_enable_cmd *)
+
+#define MSM_CAM_IOCTL_CTRL_CMD_DONE \
+ _IOW(MSM_CAM_IOCTL_MAGIC, 9, struct camera_cmd *)
+
+#define MSM_CAM_IOCTL_CONFIG_CMD \
+ _IOW(MSM_CAM_IOCTL_MAGIC, 10, struct camera_cmd *)
+
+#define MSM_CAM_IOCTL_DISABLE_VFE \
+ _IOW(MSM_CAM_IOCTL_MAGIC, 11, struct camera_enable_cmd *)
+
+#define MSM_CAM_IOCTL_PAD_REG_RESET2 \
+ _IOW(MSM_CAM_IOCTL_MAGIC, 12, struct camera_enable_cmd *)
+
+#define MSM_CAM_IOCTL_VFE_APPS_RESET \
+ _IOW(MSM_CAM_IOCTL_MAGIC, 13, struct camera_enable_cmd *)
+
+#define MSM_CAM_IOCTL_RELEASE_FRAME_BUFFER \
+ _IOW(MSM_CAM_IOCTL_MAGIC, 14, struct camera_enable_cmd *)
+
+#define MSM_CAM_IOCTL_RELEASE_STATS_BUFFER \
+ _IOW(MSM_CAM_IOCTL_MAGIC, 15, struct msm_stats_buf *)
+
+#define MSM_CAM_IOCTL_AXI_CONFIG \
+ _IOW(MSM_CAM_IOCTL_MAGIC, 16, struct msm_camera_vfe_cfg_cmd *)
+
+#define MSM_CAM_IOCTL_GET_PICTURE \
+ _IOW(MSM_CAM_IOCTL_MAGIC, 17, struct msm_frame *)
+
+#define MSM_CAM_IOCTL_SET_CROP \
+ _IOW(MSM_CAM_IOCTL_MAGIC, 18, struct crop_info *)
+
+#define MSM_CAM_IOCTL_PICT_PP \
+ _IOW(MSM_CAM_IOCTL_MAGIC, 19, uint8_t *)
+
+#define MSM_CAM_IOCTL_PICT_PP_DONE \
+ _IOW(MSM_CAM_IOCTL_MAGIC, 20, struct msm_snapshot_pp_status *)
+
+#define MSM_CAM_IOCTL_SENSOR_IO_CFG \
+ _IOW(MSM_CAM_IOCTL_MAGIC, 21, struct sensor_cfg_data *)
+
+#define MSM_CAM_IOCTL_FLASH_LED_CFG \
+ _IOW(MSM_CAM_IOCTL_MAGIC, 22, unsigned int *)
+
+#define MSM_CAM_IOCTL_UNBLOCK_POLL_FRAME \
+ _IO(MSM_CAM_IOCTL_MAGIC, 23)
+
+#define MSM_CAM_IOCTL_CTRL_COMMAND_2 \
+ _IOW(MSM_CAM_IOCTL_MAGIC, 24, struct msm_ctrl_cmd *)
+
+#define MSM_CAM_IOCTL_AF_CTRL \
+ _IOR(MSM_CAM_IOCTL_MAGIC, 25, struct msm_ctrl_cmt_t *)
+
+#define MSM_CAM_IOCTL_AF_CTRL_DONE \
+ _IOW(MSM_CAM_IOCTL_MAGIC, 26, struct msm_ctrl_cmt_t *)
+
+#define MSM_CAM_IOCTL_CONFIG_VPE \
+ _IOW(MSM_CAM_IOCTL_MAGIC, 27, struct msm_camera_vpe_cfg_cmd *)
+
+#define MSM_CAM_IOCTL_AXI_VPE_CONFIG \
+ _IOW(MSM_CAM_IOCTL_MAGIC, 28, struct msm_camera_vpe_cfg_cmd *)
+
+#define MSM_CAM_IOCTL_STROBE_FLASH_CFG \
+ _IOW(MSM_CAM_IOCTL_MAGIC, 29, uint32_t *)
+
+#define MSM_CAM_IOCTL_STROBE_FLASH_CHARGE \
+ _IOW(MSM_CAM_IOCTL_MAGIC, 30, uint32_t *)
+
+#define MSM_CAM_IOCTL_STROBE_FLASH_RELEASE \
+ _IO(MSM_CAM_IOCTL_MAGIC, 31)
+
+#define MSM_CAM_IOCTL_FLASH_CTRL \
+ _IOW(MSM_CAM_IOCTL_MAGIC, 32, struct flash_ctrl_data *)
+
+#define MSM_CAM_IOCTL_ERROR_CONFIG \
+ _IOW(MSM_CAM_IOCTL_MAGIC, 33, uint32_t *)
+
+#define MSM_CAM_IOCTL_ABORT_CAPTURE \
+ _IO(MSM_CAM_IOCTL_MAGIC, 34)
+
+#define MSM_CAM_IOCTL_SET_FD_ROI \
+ _IOW(MSM_CAM_IOCTL_MAGIC, 35, struct fd_roi_info *)
+
+#define MSM_CAM_IOCTL_GET_CAMERA_INFO \
+ _IOR(MSM_CAM_IOCTL_MAGIC, 36, struct msm_camera_info *)
+
+#define MSM_CAM_IOCTL_UNBLOCK_POLL_PIC_FRAME \
+ _IO(MSM_CAM_IOCTL_MAGIC, 37)
+
+#define MSM_CAM_IOCTL_RELEASE_PIC_BUFFER \
+ _IOW(MSM_CAM_IOCTL_MAGIC, 38, struct camera_enable_cmd *)
+
+#define MSM_CAM_IOCTL_PUT_ST_FRAME \
+ _IOW(MSM_CAM_IOCTL_MAGIC, 39, struct msm_camera_st_frame *)
+
+#define MSM_CAM_IOCTL_V4L2_EVT_NOTIFY \
+ _IOW(MSM_CAM_IOCTL_MAGIC, 40, struct v4l2_event_and_payload)
+
+#define MSM_CAM_IOCTL_SET_MEM_MAP_INFO \
+ _IOR(MSM_CAM_IOCTL_MAGIC, 41, struct msm_mem_map_info *)
+
+#define MSM_CAM_IOCTL_ACTUATOR_IO_CFG \
+ _IOW(MSM_CAM_IOCTL_MAGIC, 42, struct msm_actuator_cfg_data *)
+
+#define MSM_CAM_IOCTL_MCTL_POST_PROC \
+ _IOW(MSM_CAM_IOCTL_MAGIC, 43, struct msm_mctl_post_proc_cmd *)
+
+#define MSM_CAM_IOCTL_RESERVE_FREE_FRAME \
+ _IOW(MSM_CAM_IOCTL_MAGIC, 44, struct msm_cam_evt_divert_frame *)
+
+#define MSM_CAM_IOCTL_RELEASE_FREE_FRAME \
+ _IOR(MSM_CAM_IOCTL_MAGIC, 45, struct msm_cam_evt_divert_frame *)
+
+#define MSM_CAM_IOCTL_PICT_PP_DIVERT_DONE \
+ _IOR(MSM_CAM_IOCTL_MAGIC, 46, struct msm_pp_frame *)
+
+#define MSM_CAM_IOCTL_SENSOR_V4l2_S_CTRL \
+ _IOR(MSM_CAM_IOCTL_MAGIC, 47, struct v4l2_control)
+
+#define MSM_CAM_IOCTL_SENSOR_V4l2_QUERY_CTRL \
+ _IOR(MSM_CAM_IOCTL_MAGIC, 48, struct v4l2_queryctrl)
+
+#define MSM_CAM_IOCTL_GET_KERNEL_SYSTEM_TIME \
+ _IOW(MSM_CAM_IOCTL_MAGIC, 49, struct timeval *)
+
+#define MSM_CAM_IOCTL_SET_VFE_OUTPUT_TYPE \
+ _IOW(MSM_CAM_IOCTL_MAGIC, 50, uint32_t *)
+
+#define MSM_CAM_IOCTL_MCTL_DIVERT_DONE \
+ _IOR(MSM_CAM_IOCTL_MAGIC, 51, struct msm_cam_evt_divert_frame *)
+
+#define MSM_CAM_IOCTL_GET_ACTUATOR_INFO \
+ _IOW(MSM_CAM_IOCTL_MAGIC, 52, struct msm_actuator_cfg_data *)
+
+#define MSM_CAM_IOCTL_EEPROM_IO_CFG \
+ _IOW(MSM_CAM_IOCTL_MAGIC, 53, struct msm_eeprom_cfg_data *)
+
+#define MSM_CAM_IOCTL_ISPIF_IO_CFG \
+ _IOR(MSM_CAM_IOCTL_MAGIC, 54, struct ispif_cfg_data *)
+
+#define MSM_CAM_IOCTL_STATS_REQBUF \
+ _IOR(MSM_CAM_IOCTL_MAGIC, 55, struct msm_stats_reqbuf *)
+
+#define MSM_CAM_IOCTL_STATS_ENQUEUEBUF \
+ _IOR(MSM_CAM_IOCTL_MAGIC, 56, struct msm_stats_buf_info *)
+
+#define MSM_CAM_IOCTL_STATS_FLUSH_BUFQ \
+ _IOR(MSM_CAM_IOCTL_MAGIC, 57, struct msm_stats_flush_bufq *)
+
+#define MSM_CAM_IOCTL_SET_MCTL_SDEV \
+ _IOW(MSM_CAM_IOCTL_MAGIC, 58, struct msm_mctl_set_sdev_data *)
+
+#define MSM_CAM_IOCTL_UNSET_MCTL_SDEV \
+ _IOW(MSM_CAM_IOCTL_MAGIC, 59, struct msm_mctl_set_sdev_data *)
+
+#define MSM_CAM_IOCTL_GET_INST_HANDLE \
+ _IOR(MSM_CAM_IOCTL_MAGIC, 60, uint32_t *)
+
+#define MSM_CAM_IOCTL_STATS_UNREG_BUF \
+ _IOR(MSM_CAM_IOCTL_MAGIC, 61, struct msm_stats_flush_bufq *)
+
+#define MSM_CAM_IOCTL_CSIC_IO_CFG \
+ _IOWR(MSM_CAM_IOCTL_MAGIC, 62, struct csic_cfg_data *)
+
+#define MSM_CAM_IOCTL_CSID_IO_CFG \
+ _IOWR(MSM_CAM_IOCTL_MAGIC, 63, struct csid_cfg_data *)
+
+#define MSM_CAM_IOCTL_CSIPHY_IO_CFG \
+ _IOR(MSM_CAM_IOCTL_MAGIC, 64, struct csiphy_cfg_data *)
+
+#define MSM_CAM_IOCTL_OEM \
+ _IOW(MSM_CAM_IOCTL_MAGIC, 65, struct sensor_cfg_data *)
+
+#define MSM_CAM_IOCTL_AXI_INIT \
+ _IOWR(MSM_CAM_IOCTL_MAGIC, 66, uint8_t *)
+
+#define MSM_CAM_IOCTL_AXI_RELEASE \
+ _IO(MSM_CAM_IOCTL_MAGIC, 67)
+
+struct v4l2_event_and_payload {
+ struct v4l2_event evt;
+ uint32_t payload_length;
+ uint32_t transaction_id;
+ void *payload;
+};
+
+struct msm_stats_reqbuf {
+ int num_buf; /* how many buffers requested */
+ int stats_type; /* stats type */
+};
+
+struct msm_stats_flush_bufq {
+ int stats_type; /* enum msm_stats_enum_type */
+};
+
+struct msm_mctl_pp_cmd {
+ int32_t id;
+ uint16_t length;
+ void *value;
+};
+
+struct msm_mctl_post_proc_cmd {
+ int32_t type;
+ struct msm_mctl_pp_cmd cmd;
+};
+
+#define MSM_CAMERA_LED_OFF 0
+#define MSM_CAMERA_LED_LOW 1
+#define MSM_CAMERA_LED_HIGH 2
+#define MSM_CAMERA_LED_INIT 3
+#define MSM_CAMERA_LED_RELEASE 4
+
+#define MSM_CAMERA_STROBE_FLASH_NONE 0
+#define MSM_CAMERA_STROBE_FLASH_XENON 1
+
+#define MSM_MAX_CAMERA_SENSORS 5
+#define MAX_SENSOR_NAME 32
+#define MAX_CAM_NAME_SIZE 32
+#define MAX_ACT_MOD_NAME_SIZE 32
+#define MAX_ACT_NAME_SIZE 32
+#define NUM_ACTUATOR_DIR 2
+#define MAX_ACTUATOR_SCENARIO 8
+#define MAX_ACTUATOR_REGION 5
+#define MAX_ACTUATOR_INIT_SET 12
+#define MAX_ACTUATOR_TYPE_SIZE 32
+#define MAX_ACTUATOR_REG_TBL_SIZE 8
+
+
+#define MSM_MAX_CAMERA_CONFIGS 2
+
+#define PP_SNAP 0x01
+#define PP_RAW_SNAP ((0x01)<<1)
+#define PP_PREV ((0x01)<<2)
+#define PP_THUMB ((0x01)<<3)
+#define PP_MASK (PP_SNAP|PP_RAW_SNAP|PP_PREV|PP_THUMB)
+
+#define MSM_CAM_CTRL_CMD_DONE 0
+#define MSM_CAM_SENSOR_VFE_CMD 1
+
+/* Should be same as VIDEO_MAX_PLANES in videodev2.h */
+#define MAX_PLANES 8
+
+/*****************************************************
+ * structure
+ *****************************************************/
+
+/* define five type of structures for userspace <==> kernel
+ * space communication:
+ * command 1 - 2 are from userspace ==> kernel
+ * command 3 - 4 are from kernel ==> userspace
+ *
+ * 1. control command: control command(from control thread),
+ * control status (from config thread);
+ */
+struct msm_ctrl_cmd {
+ uint16_t type;
+ uint16_t length;
+ void *value;
+ uint16_t status;
+ uint32_t timeout_ms;
+ int resp_fd; /* FIXME: to be used by the kernel, pass-through for now */
+ int vnode_id; /* video dev id. Can we overload resp_fd? */
+ int queue_idx;
+ uint32_t evt_id;
+ uint32_t stream_type; /* used to pass value to qcamera server */
+ int config_ident; /*used as identifier for config node*/
+};
+
+struct msm_cam_evt_msg {
+ unsigned short type; /* 1 == event (RPC), 0 == message (adsp) */
+ unsigned short msg_id;
+ unsigned int len; /* size in, number of bytes out */
+ uint32_t frame_id;
+ void *data;
+ struct timespec timestamp;
+};
+
+struct msm_pp_frame_sp {
+ /* phy addr of the buffer */
+ unsigned long phy_addr;
+ uint32_t y_off;
+ uint32_t cbcr_off;
+ /* buffer length */
+ uint32_t length;
+ int32_t fd;
+ uint32_t addr_offset;
+ /* mapped addr */
+ unsigned long vaddr;
+};
+
+struct msm_pp_frame_mp {
+ /* phy addr of the plane */
+ unsigned long phy_addr;
+ /* offset of plane data */
+ uint32_t data_offset;
+ /* plane length */
+ uint32_t length;
+ int32_t fd;
+ uint32_t addr_offset;
+ /* mapped addr */
+ unsigned long vaddr;
+};
+
+struct msm_pp_frame {
+ uint32_t handle; /* stores vb cookie */
+ uint32_t frame_id;
+ unsigned short buf_idx;
+ int path;
+ unsigned short image_type;
+ unsigned short num_planes; /* 1 for sp */
+ struct timeval timestamp;
+ union {
+ struct msm_pp_frame_sp sp;
+ struct msm_pp_frame_mp mp[MAX_PLANES];
+ };
+ int node_type;
+ uint32_t inst_handle;
+};
+
+struct msm_pp_crop {
+ uint32_t src_x;
+ uint32_t src_y;
+ uint32_t src_w;
+ uint32_t src_h;
+ uint32_t dst_x;
+ uint32_t dst_y;
+ uint32_t dst_w;
+ uint32_t dst_h;
+ uint8_t update_flag;
+};
+
+struct msm_mctl_pp_frame_cmd {
+ uint32_t cookie;
+ uint8_t vpe_output_action;
+ struct msm_pp_frame src_frame;
+ struct msm_pp_frame dest_frame;
+ struct msm_pp_crop crop;
+ int path;
+};
+
+struct msm_cam_evt_divert_frame {
+ unsigned short image_mode;
+ unsigned short op_mode;
+ unsigned short inst_idx;
+ unsigned short node_idx;
+ struct msm_pp_frame frame;
+ int do_pp;
+};
+
+struct msm_mctl_pp_cmd_ack_event {
+ uint32_t cmd; /* VPE_CMD_ZOOM? */
+ int status; /* 0 done, < 0 err */
+ uint32_t cookie; /* daemon's cookie */
+};
+
+struct msm_mctl_pp_event_info {
+ int32_t event;
+ union {
+ struct msm_mctl_pp_cmd_ack_event ack;
+ };
+};
+
+struct msm_isp_event_ctrl {
+ unsigned short resptype;
+ union {
+ struct msm_cam_evt_msg isp_msg;
+ struct msm_ctrl_cmd ctrl;
+ struct msm_cam_evt_divert_frame div_frame;
+ struct msm_mctl_pp_event_info pp_event_info;
+ } isp_data;
+};
+
+#define MSM_CAM_RESP_CTRL 0
+#define MSM_CAM_RESP_STAT_EVT_MSG 1
+#define MSM_CAM_RESP_STEREO_OP_1 2
+#define MSM_CAM_RESP_STEREO_OP_2 3
+#define MSM_CAM_RESP_V4L2 4
+#define MSM_CAM_RESP_DIV_FRAME_EVT_MSG 5
+#define MSM_CAM_RESP_DONE_EVENT 6
+#define MSM_CAM_RESP_MCTL_PP_EVENT 7
+#define MSM_CAM_RESP_MAX 8
+
+#define MSM_CAM_APP_NOTIFY_EVENT 0
+#define MSM_CAM_APP_NOTIFY_ERROR_EVENT 1
+
+/* this one is used to send ctrl/status up to config thread */
+
+struct msm_stats_event_ctrl {
+ /* 0 - ctrl_cmd from control thread,
+ * 1 - stats/event kernel,
+ * 2 - V4L control or read request
+ */
+ int resptype;
+ int timeout_ms;
+ struct msm_ctrl_cmd ctrl_cmd;
+ /* struct vfe_event_t stats_event; */
+ struct msm_cam_evt_msg stats_event;
+};
+
+/* 2. config command: config command(from config thread); */
+struct msm_camera_cfg_cmd {
+ /* what to config:
+ * 1 - sensor config, 2 - vfe config
+ */
+ uint16_t cfg_type;
+
+ /* sensor config type */
+ uint16_t cmd_type;
+ uint16_t queue;
+ uint16_t length;
+ void *value;
+};
+
+#define CMD_GENERAL 0
+#define CMD_AXI_CFG_OUT1 1
+#define CMD_AXI_CFG_SNAP_O1_AND_O2 2
+#define CMD_AXI_CFG_OUT2 3
+#define CMD_PICT_T_AXI_CFG 4
+#define CMD_PICT_M_AXI_CFG 5
+#define CMD_RAW_PICT_AXI_CFG 6
+
+#define CMD_FRAME_BUF_RELEASE 7
+#define CMD_PREV_BUF_CFG 8
+#define CMD_SNAP_BUF_RELEASE 9
+#define CMD_SNAP_BUF_CFG 10
+#define CMD_STATS_DISABLE 11
+#define CMD_STATS_AEC_AWB_ENABLE 12
+#define CMD_STATS_AF_ENABLE 13
+#define CMD_STATS_AEC_ENABLE 14
+#define CMD_STATS_AWB_ENABLE 15
+#define CMD_STATS_ENABLE 16
+
+#define CMD_STATS_AXI_CFG 17
+#define CMD_STATS_AEC_AXI_CFG 18
+#define CMD_STATS_AF_AXI_CFG 19
+#define CMD_STATS_AWB_AXI_CFG 20
+#define CMD_STATS_RS_AXI_CFG 21
+#define CMD_STATS_CS_AXI_CFG 22
+#define CMD_STATS_IHIST_AXI_CFG 23
+#define CMD_STATS_SKIN_AXI_CFG 24
+
+#define CMD_STATS_BUF_RELEASE 25
+#define CMD_STATS_AEC_BUF_RELEASE 26
+#define CMD_STATS_AF_BUF_RELEASE 27
+#define CMD_STATS_AWB_BUF_RELEASE 28
+#define CMD_STATS_RS_BUF_RELEASE 29
+#define CMD_STATS_CS_BUF_RELEASE 30
+#define CMD_STATS_IHIST_BUF_RELEASE 31
+#define CMD_STATS_SKIN_BUF_RELEASE 32
+
+#define UPDATE_STATS_INVALID 33
+#define CMD_AXI_CFG_SNAP_GEMINI 34
+#define CMD_AXI_CFG_SNAP 35
+#define CMD_AXI_CFG_PREVIEW 36
+#define CMD_AXI_CFG_VIDEO 37
+
+#define CMD_STATS_IHIST_ENABLE 38
+#define CMD_STATS_RS_ENABLE 39
+#define CMD_STATS_CS_ENABLE 40
+#define CMD_VPE 41
+#define CMD_AXI_CFG_VPE 42
+#define CMD_AXI_CFG_ZSL 43
+#define CMD_AXI_CFG_SNAP_VPE 44
+#define CMD_AXI_CFG_SNAP_THUMB_VPE 45
+
+#define CMD_CONFIG_PING_ADDR 46
+#define CMD_CONFIG_PONG_ADDR 47
+#define CMD_CONFIG_FREE_BUF_ADDR 48
+#define CMD_AXI_CFG_ZSL_ALL_CHNLS 49
+#define CMD_AXI_CFG_VIDEO_ALL_CHNLS 50
+#define CMD_VFE_BUFFER_RELEASE 51
+#define CMD_VFE_PROCESS_IRQ 52
+#define CMD_STATS_BG_ENABLE 53
+#define CMD_STATS_BF_ENABLE 54
+#define CMD_STATS_BHIST_ENABLE 55
+#define CMD_STATS_BG_BUF_RELEASE 56
+#define CMD_STATS_BF_BUF_RELEASE 57
+#define CMD_STATS_BHIST_BUF_RELEASE 58
+#define CMD_VFE_PIX_SOF_COUNT_UPDATE 59
+#define CMD_VFE_COUNT_PIX_SOF_ENABLE 60
+#define CMD_STATS_BE_ENABLE 61
+#define CMD_STATS_BE_BUF_RELEASE 62
+
+#define CMD_AXI_CFG_PRIM BIT(8)
+#define CMD_AXI_CFG_PRIM_ALL_CHNLS BIT(9)
+#define CMD_AXI_CFG_SEC BIT(10)
+#define CMD_AXI_CFG_SEC_ALL_CHNLS BIT(11)
+#define CMD_AXI_CFG_TERT1 BIT(12)
+#define CMD_AXI_CFG_TERT2 BIT(13)
+
+#define CMD_AXI_START 0xE1
+#define CMD_AXI_STOP 0xE2
+#define CMD_AXI_RESET 0xE3
+#define CMD_AXI_ABORT 0xE4
+
+
+
+#define AXI_CMD_PREVIEW BIT(0)
+#define AXI_CMD_CAPTURE BIT(1)
+#define AXI_CMD_RECORD BIT(2)
+#define AXI_CMD_ZSL BIT(3)
+#define AXI_CMD_RAW_CAPTURE BIT(4)
+#define AXI_CMD_LIVESHOT BIT(5)
+
+/* vfe config command: config command(from config thread)*/
+struct msm_vfe_cfg_cmd {
+ int cmd_type;
+ uint16_t length;
+ void *value;
+};
+
+struct msm_vpe_cfg_cmd {
+ int cmd_type;
+ uint16_t length;
+ void *value;
+};
+
+#define MAX_CAMERA_ENABLE_NAME_LEN 32
+struct camera_enable_cmd {
+ char name[MAX_CAMERA_ENABLE_NAME_LEN];
+};
+
+#define MSM_PMEM_OUTPUT1 0
+#define MSM_PMEM_OUTPUT2 1
+#define MSM_PMEM_OUTPUT1_OUTPUT2 2
+#define MSM_PMEM_THUMBNAIL 3
+#define MSM_PMEM_MAINIMG 4
+#define MSM_PMEM_RAW_MAINIMG 5
+#define MSM_PMEM_AEC_AWB 6
+#define MSM_PMEM_AF 7
+#define MSM_PMEM_AEC 8
+#define MSM_PMEM_AWB 9
+#define MSM_PMEM_RS 10
+#define MSM_PMEM_CS 11
+#define MSM_PMEM_IHIST 12
+#define MSM_PMEM_SKIN 13
+#define MSM_PMEM_VIDEO 14
+#define MSM_PMEM_PREVIEW 15
+#define MSM_PMEM_VIDEO_VPE 16
+#define MSM_PMEM_C2D 17
+#define MSM_PMEM_MAINIMG_VPE 18
+#define MSM_PMEM_THUMBNAIL_VPE 19
+#define MSM_PMEM_BAYER_GRID 20
+#define MSM_PMEM_BAYER_FOCUS 21
+#define MSM_PMEM_BAYER_HIST 22
+#define MSM_PMEM_BAYER_EXPOSURE 23
+#define MSM_PMEM_MAX 24
+
+#define STAT_AEAW 0
+#define STAT_AEC 1
+#define STAT_AF 2
+#define STAT_AWB 3
+#define STAT_RS 4
+#define STAT_CS 5
+#define STAT_IHIST 6
+#define STAT_SKIN 7
+#define STAT_BG 8
+#define STAT_BF 9
+#define STAT_BE 10
+#define STAT_BHIST 11
+#define STAT_MAX 12
+
+#define FRAME_PREVIEW_OUTPUT1 0
+#define FRAME_PREVIEW_OUTPUT2 1
+#define FRAME_SNAPSHOT 2
+#define FRAME_THUMBNAIL 3
+#define FRAME_RAW_SNAPSHOT 4
+#define FRAME_MAX 5
+
+enum msm_stats_enum_type {
+ MSM_STATS_TYPE_AEC, /* legacy based AEC */
+ MSM_STATS_TYPE_AF, /* legacy based AF */
+ MSM_STATS_TYPE_AWB, /* legacy based AWB */
+ MSM_STATS_TYPE_RS, /* legacy based RS */
+ MSM_STATS_TYPE_CS, /* legacy based CS */
+ MSM_STATS_TYPE_IHIST, /* legacy based HIST */
+ MSM_STATS_TYPE_SKIN, /* legacy based SKIN */
+ MSM_STATS_TYPE_BG, /* Bayer Grids */
+ MSM_STATS_TYPE_BF, /* Bayer Focus */
+ MSM_STATS_TYPE_BE, /* Bayer Exposure*/
+ MSM_STATS_TYPE_BHIST, /* Bayer Hist */
+ MSM_STATS_TYPE_AE_AW, /* legacy stats for vfe 2.x*/
+ MSM_STATS_TYPE_COMP, /* Composite stats */
+ MSM_STATS_TYPE_MAX /* MAX */
+};
+
+struct msm_stats_buf_info {
+ int type; /* msm_stats_enum_type */
+ int fd;
+ void *vaddr;
+ uint32_t offset;
+ uint32_t len;
+ uint32_t y_off;
+ uint32_t cbcr_off;
+ uint32_t planar0_off;
+ uint32_t planar1_off;
+ uint32_t planar2_off;
+ uint8_t active;
+ int buf_idx;
+};
+
+struct msm_pmem_info {
+ int type;
+ int fd;
+ void *vaddr;
+ uint32_t offset;
+ uint32_t len;
+ uint32_t y_off;
+ uint32_t cbcr_off;
+ uint32_t planar0_off;
+ uint32_t planar1_off;
+ uint32_t planar2_off;
+ uint8_t active;
+};
+
+struct outputCfg {
+ uint32_t height;
+ uint32_t width;
+
+ uint32_t window_height_firstline;
+ uint32_t window_height_lastline;
+};
+
+#define VIDEO_NODE 0
+#define MCTL_NODE 1
+
+#define OUTPUT_1 0
+#define OUTPUT_2 1
+#define OUTPUT_1_AND_2 2 /* snapshot only */
+#define OUTPUT_1_AND_3 3 /* video */
+#define CAMIF_TO_AXI_VIA_OUTPUT_2 4
+#define OUTPUT_1_AND_CAMIF_TO_AXI_VIA_OUTPUT_2 5
+#define OUTPUT_2_AND_CAMIF_TO_AXI_VIA_OUTPUT_1 6
+#define OUTPUT_1_2_AND_3 7
+#define OUTPUT_ALL_CHNLS 8
+#define OUTPUT_VIDEO_ALL_CHNLS 9
+#define OUTPUT_ZSL_ALL_CHNLS 10
+#define LAST_AXI_OUTPUT_MODE_ENUM OUTPUT_ZSL_ALL_CHNLS
+
+#define OUTPUT_PRIM BIT(8)
+#define OUTPUT_PRIM_ALL_CHNLS BIT(9)
+#define OUTPUT_SEC BIT(10)
+#define OUTPUT_SEC_ALL_CHNLS BIT(11)
+#define OUTPUT_TERT1 BIT(12)
+#define OUTPUT_TERT2 BIT(13)
+
+
+
+#define MSM_FRAME_PREV_1 0
+#define MSM_FRAME_PREV_2 1
+#define MSM_FRAME_ENC 2
+
+#define OUTPUT_TYPE_P BIT(0)
+#define OUTPUT_TYPE_T BIT(1)
+#define OUTPUT_TYPE_S BIT(2)
+#define OUTPUT_TYPE_V BIT(3)
+#define OUTPUT_TYPE_L BIT(4)
+#define OUTPUT_TYPE_ST_L BIT(5)
+#define OUTPUT_TYPE_ST_R BIT(6)
+#define OUTPUT_TYPE_ST_D BIT(7)
+#define OUTPUT_TYPE_R BIT(8)
+#define OUTPUT_TYPE_R1 BIT(9)
+#define OUTPUT_TYPE_SAEC BIT(10)
+#define OUTPUT_TYPE_SAFC BIT(11)
+#define OUTPUT_TYPE_SAWB BIT(12)
+#define OUTPUT_TYPE_IHST BIT(13)
+#define OUTPUT_TYPE_CSTA BIT(14)
+
+struct fd_roi_info {
+ void *info;
+ int info_len;
+};
+
+struct msm_mem_map_info {
+ uint32_t cookie;
+ uint32_t length;
+ uint32_t mem_type;
+};
+
+#define MSM_MEM_MMAP 0
+#define MSM_MEM_USERPTR 1
+#define MSM_PLANE_MAX 8
+#define MSM_PLANE_Y 0
+#define MSM_PLANE_UV 1
+
+struct msm_frame {
+ struct timespec ts;
+ int path;
+ int type;
+ unsigned long buffer;
+ uint32_t phy_offset;
+ uint32_t y_off;
+ uint32_t cbcr_off;
+ uint32_t planar0_off;
+ uint32_t planar1_off;
+ uint32_t planar2_off;
+ int fd;
+
+ void *cropinfo;
+ int croplen;
+ uint32_t error_code;
+ struct fd_roi_info roi_info;
+ uint32_t frame_id;
+ int stcam_quality_ind;
+ uint32_t stcam_conv_value;
+
+ struct ion_allocation_data ion_alloc;
+ struct ion_fd_data fd_data;
+ int ion_dev_fd;
+};
+
+enum msm_st_frame_packing {
+ SIDE_BY_SIDE_HALF,
+ SIDE_BY_SIDE_FULL,
+ TOP_DOWN_HALF,
+ TOP_DOWN_FULL,
+};
+
+struct msm_st_crop {
+ uint32_t in_w;
+ uint32_t in_h;
+ uint32_t out_w;
+ uint32_t out_h;
+};
+
+struct msm_st_half {
+ uint32_t buf_p0_off;
+ uint32_t buf_p1_off;
+ uint32_t buf_p0_stride;
+ uint32_t buf_p1_stride;
+ uint32_t pix_x_off;
+ uint32_t pix_y_off;
+ struct msm_st_crop stCropInfo;
+};
+
+struct msm_st_frame {
+ struct msm_frame buf_info;
+ int type;
+ enum msm_st_frame_packing packing;
+ struct msm_st_half L;
+ struct msm_st_half R;
+ int frame_id;
+};
+
+#define MSM_CAMERA_ERR_MASK (0xFFFFFFFF & 1)
+
+struct stats_buff {
+ unsigned long buff;
+ int fd;
+};
+
+struct msm_stats_buf {
+ uint8_t awb_ymin;
+ struct stats_buff aec;
+ struct stats_buff awb;
+ struct stats_buff af;
+ struct stats_buff be;
+ struct stats_buff ihist;
+ struct stats_buff rs;
+ struct stats_buff cs;
+ struct stats_buff skin;
+ int type;
+ uint32_t status_bits;
+ unsigned long buffer;
+ int fd;
+ int length;
+ struct ion_handle *handle;
+ uint32_t frame_id;
+ int buf_idx;
+};
+#define MSM_V4L2_EXT_CAPTURE_MODE_DEFAULT 0
+/* video capture mode in VIDIOC_S_PARM */
+#define MSM_V4L2_EXT_CAPTURE_MODE_PREVIEW \
+ (MSM_V4L2_EXT_CAPTURE_MODE_DEFAULT+1)
+/* extendedmode for video recording in VIDIOC_S_PARM */
+#define MSM_V4L2_EXT_CAPTURE_MODE_VIDEO \
+ (MSM_V4L2_EXT_CAPTURE_MODE_DEFAULT+2)
+/* extendedmode for the full size main image in VIDIOC_S_PARM */
+#define MSM_V4L2_EXT_CAPTURE_MODE_MAIN (MSM_V4L2_EXT_CAPTURE_MODE_DEFAULT+3)
+/* extendedmode for the thumb nail image in VIDIOC_S_PARM */
+#define MSM_V4L2_EXT_CAPTURE_MODE_THUMBNAIL \
+ (MSM_V4L2_EXT_CAPTURE_MODE_DEFAULT+4)
+/* ISP_PIX_OUTPUT1: no pp, directly send output1 buf to user */
+#define MSM_V4L2_EXT_CAPTURE_MODE_ISP_PIX_OUTPUT1 \
+ (MSM_V4L2_EXT_CAPTURE_MODE_DEFAULT+5)
+/* ISP_PIX_OUTPUT2: no pp, directly send output2 buf to user */
+#define MSM_V4L2_EXT_CAPTURE_MODE_ISP_PIX_OUTPUT2 \
+ (MSM_V4L2_EXT_CAPTURE_MODE_DEFAULT+6)
+/* raw image type */
+#define MSM_V4L2_EXT_CAPTURE_MODE_RAW \
+ (MSM_V4L2_EXT_CAPTURE_MODE_DEFAULT+7)
+/* RDI dump */
+#define MSM_V4L2_EXT_CAPTURE_MODE_RDI \
+ (MSM_V4L2_EXT_CAPTURE_MODE_DEFAULT+8)
+/* RDI dump 1 */
+#define MSM_V4L2_EXT_CAPTURE_MODE_RDI1 \
+ (MSM_V4L2_EXT_CAPTURE_MODE_DEFAULT+9)
+/* RDI dump 2 */
+#define MSM_V4L2_EXT_CAPTURE_MODE_RDI2 \
+ (MSM_V4L2_EXT_CAPTURE_MODE_DEFAULT+10)
+#define MSM_V4L2_EXT_CAPTURE_MODE_AEC \
+ (MSM_V4L2_EXT_CAPTURE_MODE_DEFAULT+11)
+#define MSM_V4L2_EXT_CAPTURE_MODE_AWB \
+ (MSM_V4L2_EXT_CAPTURE_MODE_DEFAULT+12)
+#define MSM_V4L2_EXT_CAPTURE_MODE_AF \
+ (MSM_V4L2_EXT_CAPTURE_MODE_DEFAULT+13)
+#define MSM_V4L2_EXT_CAPTURE_MODE_IHIST \
+ (MSM_V4L2_EXT_CAPTURE_MODE_DEFAULT+14)
+#define MSM_V4L2_EXT_CAPTURE_MODE_CS \
+ (MSM_V4L2_EXT_CAPTURE_MODE_DEFAULT+15)
+#define MSM_V4L2_EXT_CAPTURE_MODE_RS \
+ (MSM_V4L2_EXT_CAPTURE_MODE_DEFAULT+16)
+#define MSM_V4L2_EXT_CAPTURE_MODE_CSTA \
+ (MSM_V4L2_EXT_CAPTURE_MODE_DEFAULT+17)
+#define MSM_V4L2_EXT_CAPTURE_MODE_V2X_LIVESHOT \
+ (MSM_V4L2_EXT_CAPTURE_MODE_DEFAULT+18)
+#define MSM_V4L2_EXT_CAPTURE_MODE_MAX (MSM_V4L2_EXT_CAPTURE_MODE_DEFAULT+19)
+
+
+#define MSM_V4L2_PID_MOTION_ISO V4L2_CID_PRIVATE_BASE
+#define MSM_V4L2_PID_EFFECT (V4L2_CID_PRIVATE_BASE+1)
+#define MSM_V4L2_PID_HJR (V4L2_CID_PRIVATE_BASE+2)
+#define MSM_V4L2_PID_LED_MODE (V4L2_CID_PRIVATE_BASE+3)
+#define MSM_V4L2_PID_PREP_SNAPSHOT (V4L2_CID_PRIVATE_BASE+4)
+#define MSM_V4L2_PID_EXP_METERING (V4L2_CID_PRIVATE_BASE+5)
+#define MSM_V4L2_PID_ISO (V4L2_CID_PRIVATE_BASE+6)
+#define MSM_V4L2_PID_CAM_MODE (V4L2_CID_PRIVATE_BASE+7)
+#define MSM_V4L2_PID_LUMA_ADAPTATION (V4L2_CID_PRIVATE_BASE+8)
+#define MSM_V4L2_PID_BEST_SHOT (V4L2_CID_PRIVATE_BASE+9)
+#define MSM_V4L2_PID_FOCUS_MODE (V4L2_CID_PRIVATE_BASE+10)
+#define MSM_V4L2_PID_BL_DETECTION (V4L2_CID_PRIVATE_BASE+11)
+#define MSM_V4L2_PID_SNOW_DETECTION (V4L2_CID_PRIVATE_BASE+12)
+#define MSM_V4L2_PID_CTRL_CMD (V4L2_CID_PRIVATE_BASE+13)
+#define MSM_V4L2_PID_EVT_SUB_INFO (V4L2_CID_PRIVATE_BASE+14)
+#define MSM_V4L2_PID_STROBE_FLASH (V4L2_CID_PRIVATE_BASE+15)
+#define MSM_V4L2_PID_INST_HANDLE (V4L2_CID_PRIVATE_BASE+16)
+#define MSM_V4L2_PID_MMAP_INST (V4L2_CID_PRIVATE_BASE+17)
+#define MSM_V4L2_PID_PP_PLANE_INFO (V4L2_CID_PRIVATE_BASE+18)
+#define MSM_V4L2_PID_MAX MSM_V4L2_PID_PP_PLANE_INFO
+
+/* camera operation mode for video recording - two frame output queues */
+#define MSM_V4L2_CAM_OP_DEFAULT 0
+/* camera operation mode for video recording - two frame output queues */
+#define MSM_V4L2_CAM_OP_PREVIEW (MSM_V4L2_CAM_OP_DEFAULT+1)
+/* camera operation mode for video recording - two frame output queues */
+#define MSM_V4L2_CAM_OP_VIDEO (MSM_V4L2_CAM_OP_DEFAULT+2)
+/* camera operation mode for standard shapshot - two frame output queues */
+#define MSM_V4L2_CAM_OP_CAPTURE (MSM_V4L2_CAM_OP_DEFAULT+3)
+/* camera operation mode for zsl shapshot - three output queues */
+#define MSM_V4L2_CAM_OP_ZSL (MSM_V4L2_CAM_OP_DEFAULT+4)
+/* camera operation mode for raw snapshot - one frame output queue */
+#define MSM_V4L2_CAM_OP_RAW (MSM_V4L2_CAM_OP_DEFAULT+5)
+/* camera operation mode for jpeg snapshot - one frame output queue */
+#define MSM_V4L2_CAM_OP_JPEG_CAPTURE (MSM_V4L2_CAM_OP_DEFAULT+6)
+
+
+#define MSM_V4L2_VID_CAP_TYPE 0
+#define MSM_V4L2_STREAM_ON 1
+#define MSM_V4L2_STREAM_OFF 2
+#define MSM_V4L2_SNAPSHOT 3
+#define MSM_V4L2_QUERY_CTRL 4
+#define MSM_V4L2_GET_CTRL 5
+#define MSM_V4L2_SET_CTRL 6
+#define MSM_V4L2_QUERY 7
+#define MSM_V4L2_GET_CROP 8
+#define MSM_V4L2_SET_CROP 9
+#define MSM_V4L2_OPEN 10
+#define MSM_V4L2_CLOSE 11
+#define MSM_V4L2_SET_CTRL_CMD 12
+#define MSM_V4L2_EVT_SUB_MASK 13
+#define MSM_V4L2_PRIVATE_CMD 14
+#define MSM_V4L2_MAX 15
+#define V4L2_CAMERA_EXIT 43
+
+struct crop_info {
+ void *info;
+ int len;
+};
+
+struct msm_postproc {
+ int ftnum;
+ struct msm_frame fthumnail;
+ int fmnum;
+ struct msm_frame fmain;
+};
+
+struct msm_snapshot_pp_status {
+ void *status;
+};
+
+#define CFG_SET_MODE 0
+#define CFG_SET_EFFECT 1
+#define CFG_START 2
+#define CFG_PWR_UP 3
+#define CFG_PWR_DOWN 4
+#define CFG_WRITE_EXPOSURE_GAIN 5
+#define CFG_SET_DEFAULT_FOCUS 6
+#define CFG_MOVE_FOCUS 7
+#define CFG_REGISTER_TO_REAL_GAIN 8
+#define CFG_REAL_TO_REGISTER_GAIN 9
+#define CFG_SET_FPS 10
+#define CFG_SET_PICT_FPS 11
+#define CFG_SET_BRIGHTNESS 12
+#define CFG_SET_CONTRAST 13
+#define CFG_SET_ZOOM 14
+#define CFG_SET_EXPOSURE_MODE 15
+#define CFG_SET_WB 16
+#define CFG_SET_ANTIBANDING 17
+#define CFG_SET_EXP_GAIN 18
+#define CFG_SET_PICT_EXP_GAIN 19
+#define CFG_SET_LENS_SHADING 20
+#define CFG_GET_PICT_FPS 21
+#define CFG_GET_PREV_L_PF 22
+#define CFG_GET_PREV_P_PL 23
+#define CFG_GET_PICT_L_PF 24
+#define CFG_GET_PICT_P_PL 25
+#define CFG_GET_AF_MAX_STEPS 26
+#define CFG_GET_PICT_MAX_EXP_LC 27
+#define CFG_SEND_WB_INFO 28
+#define CFG_SENSOR_INIT 29
+#define CFG_GET_3D_CALI_DATA 30
+#define CFG_GET_CALIB_DATA 31
+#define CFG_GET_OUTPUT_INFO 32
+#define CFG_GET_EEPROM_INFO 33
+#define CFG_GET_EEPROM_DATA 34
+#define CFG_SET_ACTUATOR_INFO 35
+#define CFG_GET_ACTUATOR_INFO 36
+/* TBD: QRD */
+#define CFG_SET_SATURATION 37
+#define CFG_SET_SHARPNESS 38
+#define CFG_SET_TOUCHAEC 39
+#define CFG_SET_AUTO_FOCUS 40
+#define CFG_SET_AUTOFLASH 41
+#define CFG_SET_EXPOSURE_COMPENSATION 42
+#define CFG_SET_ISO 43
+#define CFG_START_STREAM 44
+#define CFG_STOP_STREAM 45
+#define CFG_GET_CSI_PARAMS 46
+#define CFG_POWER_UP 47
+#define CFG_POWER_DOWN 48
+#define CFG_WRITE_I2C_ARRAY 49
+#define CFG_READ_I2C_ARRAY 50
+#define CFG_PCLK_CHANGE 51
+#define CFG_CONFIG_VREG_ARRAY 52
+#define CFG_CONFIG_CLK_ARRAY 53
+#define CFG_GPIO_OP 54
+#define CFG_MAX 55
+
+
+#define MOVE_NEAR 0
+#define MOVE_FAR 1
+
+#define SENSOR_PREVIEW_MODE 0
+#define SENSOR_SNAPSHOT_MODE 1
+#define SENSOR_RAW_SNAPSHOT_MODE 2
+#define SENSOR_HFR_60FPS_MODE 3
+#define SENSOR_HFR_90FPS_MODE 4
+#define SENSOR_HFR_120FPS_MODE 5
+
+#define SENSOR_QTR_SIZE 0
+#define SENSOR_FULL_SIZE 1
+#define SENSOR_QVGA_SIZE 2
+#define SENSOR_INVALID_SIZE 3
+
+#define CAMERA_EFFECT_OFF 0
+#define CAMERA_EFFECT_MONO 1
+#define CAMERA_EFFECT_NEGATIVE 2
+#define CAMERA_EFFECT_SOLARIZE 3
+#define CAMERA_EFFECT_SEPIA 4
+#define CAMERA_EFFECT_POSTERIZE 5
+#define CAMERA_EFFECT_WHITEBOARD 6
+#define CAMERA_EFFECT_BLACKBOARD 7
+#define CAMERA_EFFECT_AQUA 8
+#define CAMERA_EFFECT_EMBOSS 9
+#define CAMERA_EFFECT_SKETCH 10
+#define CAMERA_EFFECT_NEON 11
+#define CAMERA_EFFECT_FADED 12
+#define CAMERA_EFFECT_VINTAGECOOL 13
+#define CAMERA_EFFECT_VINTAGEWARM 14
+#define CAMERA_EFFECT_ACCENT_BLUE 15
+#define CAMERA_EFFECT_ACCENT_GREEN 16
+#define CAMERA_EFFECT_ACCENT_ORANGE 17
+#define CAMERA_EFFECT_MAX 18
+
+/* QRD */
+#define CAMERA_EFFECT_BW 10
+#define CAMERA_EFFECT_BLUISH 12
+#define CAMERA_EFFECT_REDDISH 13
+#define CAMERA_EFFECT_GREENISH 14
+
+/* QRD */
+#define CAMERA_ANTIBANDING_OFF 0
+#define CAMERA_ANTIBANDING_50HZ 2
+#define CAMERA_ANTIBANDING_60HZ 1
+#define CAMERA_ANTIBANDING_AUTO 3
+
+#define CAMERA_CONTRAST_LV0 0
+#define CAMERA_CONTRAST_LV1 1
+#define CAMERA_CONTRAST_LV2 2
+#define CAMERA_CONTRAST_LV3 3
+#define CAMERA_CONTRAST_LV4 4
+#define CAMERA_CONTRAST_LV5 5
+#define CAMERA_CONTRAST_LV6 6
+#define CAMERA_CONTRAST_LV7 7
+#define CAMERA_CONTRAST_LV8 8
+#define CAMERA_CONTRAST_LV9 9
+
+#define CAMERA_BRIGHTNESS_LV0 0
+#define CAMERA_BRIGHTNESS_LV1 1
+#define CAMERA_BRIGHTNESS_LV2 2
+#define CAMERA_BRIGHTNESS_LV3 3
+#define CAMERA_BRIGHTNESS_LV4 4
+#define CAMERA_BRIGHTNESS_LV5 5
+#define CAMERA_BRIGHTNESS_LV6 6
+#define CAMERA_BRIGHTNESS_LV7 7
+#define CAMERA_BRIGHTNESS_LV8 8
+
+
+#define CAMERA_SATURATION_LV0 0
+#define CAMERA_SATURATION_LV1 1
+#define CAMERA_SATURATION_LV2 2
+#define CAMERA_SATURATION_LV3 3
+#define CAMERA_SATURATION_LV4 4
+#define CAMERA_SATURATION_LV5 5
+#define CAMERA_SATURATION_LV6 6
+#define CAMERA_SATURATION_LV7 7
+#define CAMERA_SATURATION_LV8 8
+
+#define CAMERA_SHARPNESS_LV0 0
+#define CAMERA_SHARPNESS_LV1 3
+#define CAMERA_SHARPNESS_LV2 6
+#define CAMERA_SHARPNESS_LV3 9
+#define CAMERA_SHARPNESS_LV4 12
+#define CAMERA_SHARPNESS_LV5 15
+#define CAMERA_SHARPNESS_LV6 18
+#define CAMERA_SHARPNESS_LV7 21
+#define CAMERA_SHARPNESS_LV8 24
+#define CAMERA_SHARPNESS_LV9 27
+#define CAMERA_SHARPNESS_LV10 30
+
+#define CAMERA_SETAE_AVERAGE 0
+#define CAMERA_SETAE_CENWEIGHT 1
+
+#define CAMERA_WB_AUTO 1 /* This list must match aeecamera.h */
+#define CAMERA_WB_CUSTOM 2
+#define CAMERA_WB_INCANDESCENT 3
+#define CAMERA_WB_FLUORESCENT 4
+#define CAMERA_WB_DAYLIGHT 5
+#define CAMERA_WB_CLOUDY_DAYLIGHT 6
+#define CAMERA_WB_TWILIGHT 7
+#define CAMERA_WB_SHADE 8
+
+#define CAMERA_EXPOSURE_COMPENSATION_LV0 12
+#define CAMERA_EXPOSURE_COMPENSATION_LV1 6
+#define CAMERA_EXPOSURE_COMPENSATION_LV2 0
+#define CAMERA_EXPOSURE_COMPENSATION_LV3 -6
+#define CAMERA_EXPOSURE_COMPENSATION_LV4 -12
+
+enum msm_v4l2_saturation_level {
+ MSM_V4L2_SATURATION_L0,
+ MSM_V4L2_SATURATION_L1,
+ MSM_V4L2_SATURATION_L2,
+ MSM_V4L2_SATURATION_L3,
+ MSM_V4L2_SATURATION_L4,
+ MSM_V4L2_SATURATION_L5,
+ MSM_V4L2_SATURATION_L6,
+ MSM_V4L2_SATURATION_L7,
+ MSM_V4L2_SATURATION_L8,
+ MSM_V4L2_SATURATION_L9,
+ MSM_V4L2_SATURATION_L10,
+};
+
+enum msm_v4l2_contrast_level {
+ MSM_V4L2_CONTRAST_L0,
+ MSM_V4L2_CONTRAST_L1,
+ MSM_V4L2_CONTRAST_L2,
+ MSM_V4L2_CONTRAST_L3,
+ MSM_V4L2_CONTRAST_L4,
+ MSM_V4L2_CONTRAST_L5,
+ MSM_V4L2_CONTRAST_L6,
+ MSM_V4L2_CONTRAST_L7,
+ MSM_V4L2_CONTRAST_L8,
+ MSM_V4L2_CONTRAST_L9,
+ MSM_V4L2_CONTRAST_L10,
+};
+
+
+enum msm_v4l2_exposure_level {
+ MSM_V4L2_EXPOSURE_N2,
+ MSM_V4L2_EXPOSURE_N1,
+ MSM_V4L2_EXPOSURE_D,
+ MSM_V4L2_EXPOSURE_P1,
+ MSM_V4L2_EXPOSURE_P2,
+};
+
+enum msm_v4l2_sharpness_level {
+ MSM_V4L2_SHARPNESS_L0,
+ MSM_V4L2_SHARPNESS_L1,
+ MSM_V4L2_SHARPNESS_L2,
+ MSM_V4L2_SHARPNESS_L3,
+ MSM_V4L2_SHARPNESS_L4,
+ MSM_V4L2_SHARPNESS_L5,
+ MSM_V4L2_SHARPNESS_L6,
+};
+
+enum msm_v4l2_expo_metering_mode {
+ MSM_V4L2_EXP_FRAME_AVERAGE,
+ MSM_V4L2_EXP_CENTER_WEIGHTED,
+ MSM_V4L2_EXP_SPOT_METERING,
+};
+
+enum msm_v4l2_iso_mode {
+ MSM_V4L2_ISO_AUTO = 0,
+ MSM_V4L2_ISO_DEBLUR,
+ MSM_V4L2_ISO_100,
+ MSM_V4L2_ISO_200,
+ MSM_V4L2_ISO_400,
+ MSM_V4L2_ISO_800,
+ MSM_V4L2_ISO_1600,
+};
+
+enum msm_v4l2_wb_mode {
+ MSM_V4L2_WB_OFF,
+ MSM_V4L2_WB_AUTO,
+ MSM_V4L2_WB_CUSTOM,
+ MSM_V4L2_WB_INCANDESCENT,
+ MSM_V4L2_WB_FLUORESCENT,
+ MSM_V4L2_WB_DAYLIGHT,
+ MSM_V4L2_WB_CLOUDY_DAYLIGHT,
+};
+
+enum msm_v4l2_special_effect {
+ MSM_V4L2_EFFECT_OFF,
+ MSM_V4L2_EFFECT_MONO,
+ MSM_V4L2_EFFECT_NEGATIVE,
+ MSM_V4L2_EFFECT_SOLARIZE,
+ MSM_V4L2_EFFECT_SEPIA,
+ MSM_V4L2_EFFECT_POSTERAIZE,
+ MSM_V4L2_EFFECT_WHITEBOARD,
+ MSM_V4L2_EFFECT_BLACKBOARD,
+ MSM_V4L2_EFFECT_AQUA,
+ MSM_V4L2_EFFECT_EMBOSS,
+ MSM_V4L2_EFFECT_SKETCH,
+ MSM_V4L2_EFFECT_NEON,
+ MSM_V4L2_EFFECT_MAX,
+};
+
+enum msm_v4l2_power_line_frequency {
+ MSM_V4L2_POWER_LINE_OFF,
+ MSM_V4L2_POWER_LINE_60HZ,
+ MSM_V4L2_POWER_LINE_50HZ,
+ MSM_V4L2_POWER_LINE_AUTO,
+};
+
+#define CAMERA_ISO_TYPE_AUTO 0
+#define CAMEAR_ISO_TYPE_HJR 1
+#define CAMEAR_ISO_TYPE_100 2
+#define CAMERA_ISO_TYPE_200 3
+#define CAMERA_ISO_TYPE_400 4
+#define CAMEAR_ISO_TYPE_800 5
+#define CAMERA_ISO_TYPE_1600 6
+
+struct sensor_pict_fps {
+ uint16_t prevfps;
+ uint16_t pictfps;
+};
+
+struct exp_gain_cfg {
+ uint16_t gain;
+ uint32_t line;
+};
+
+struct focus_cfg {
+ int32_t steps;
+ int dir;
+};
+
+struct fps_cfg {
+ uint16_t f_mult;
+ uint16_t fps_div;
+ uint32_t pict_fps_div;
+};
+struct wb_info_cfg {
+ uint16_t red_gain;
+ uint16_t green_gain;
+ uint16_t blue_gain;
+};
+struct sensor_3d_exp_cfg {
+ uint16_t gain;
+ uint32_t line;
+ uint16_t r_gain;
+ uint16_t b_gain;
+ uint16_t gr_gain;
+ uint16_t gb_gain;
+ uint16_t gain_adjust;
+};
+struct sensor_3d_cali_data_t {
+ unsigned char left_p_matrix[3][4][8];
+ unsigned char right_p_matrix[3][4][8];
+ unsigned char square_len[8];
+ unsigned char focal_len[8];
+ unsigned char pixel_pitch[8];
+ uint16_t left_r;
+ uint16_t left_b;
+ uint16_t left_gb;
+ uint16_t left_af_far;
+ uint16_t left_af_mid;
+ uint16_t left_af_short;
+ uint16_t left_af_5um;
+ uint16_t left_af_50up;
+ uint16_t left_af_50down;
+ uint16_t right_r;
+ uint16_t right_b;
+ uint16_t right_gb;
+ uint16_t right_af_far;
+ uint16_t right_af_mid;
+ uint16_t right_af_short;
+ uint16_t right_af_5um;
+ uint16_t right_af_50up;
+ uint16_t right_af_50down;
+};
+struct sensor_init_cfg {
+ uint8_t prev_res;
+ uint8_t pict_res;
+};
+
+struct sensor_calib_data {
+ /* Color Related Measurements */
+ uint16_t r_over_g;
+ uint16_t b_over_g;
+ uint16_t gr_over_gb;
+
+ /* Lens Related Measurements */
+ uint16_t macro_2_inf;
+ uint16_t inf_2_macro;
+ uint16_t stroke_amt;
+ uint16_t af_pos_1m;
+ uint16_t af_pos_inf;
+};
+
+enum msm_sensor_resolution_t {
+ MSM_SENSOR_RES_FULL,
+ MSM_SENSOR_RES_QTR,
+ MSM_SENSOR_RES_2,
+ MSM_SENSOR_RES_3,
+ MSM_SENSOR_RES_4,
+ MSM_SENSOR_RES_5,
+ MSM_SENSOR_RES_6,
+ MSM_SENSOR_RES_7,
+ MSM_SENSOR_INVALID_RES,
+};
+
+struct msm_sensor_output_info_t {
+ uint16_t x_output;
+ uint16_t y_output;
+ uint16_t line_length_pclk;
+ uint16_t frame_length_lines;
+ uint32_t vt_pixel_clk;
+ uint32_t op_pixel_clk;
+ uint16_t binning_factor;
+};
+
+struct sensor_output_info_t {
+ struct msm_sensor_output_info_t *output_info;
+ uint16_t num_info;
+};
+
+struct msm_sensor_exp_gain_info_t {
+ uint16_t coarse_int_time_addr;
+ uint16_t global_gain_addr;
+ uint16_t vert_offset;
+};
+
+struct msm_sensor_output_reg_addr_t {
+ uint16_t x_output;
+ uint16_t y_output;
+ uint16_t line_length_pclk;
+ uint16_t frame_length_lines;
+};
+
+struct sensor_driver_params_type {
+ struct msm_camera_i2c_reg_setting *init_settings;
+ uint16_t init_settings_size;
+ struct msm_camera_i2c_reg_setting *mode_settings;
+ uint16_t mode_settings_size;
+ struct msm_sensor_output_reg_addr_t *sensor_output_reg_addr;
+ struct msm_camera_i2c_reg_setting *start_settings;
+ struct msm_camera_i2c_reg_setting *stop_settings;
+ struct msm_camera_i2c_reg_setting *groupon_settings;
+ struct msm_camera_i2c_reg_setting *groupoff_settings;
+ struct msm_sensor_exp_gain_info_t *sensor_exp_gain_info;
+ struct msm_sensor_output_info_t *output_info;
+};
+
+struct mirror_flip {
+ int32_t x_mirror;
+ int32_t y_flip;
+};
+
+struct cord {
+ uint32_t x;
+ uint32_t y;
+};
+
+struct msm_eeprom_data_t {
+ void *eeprom_data;
+ uint16_t index;
+};
+
+struct msm_camera_csid_vc_cfg {
+ uint8_t cid;
+ uint8_t dt;
+ uint8_t decode_format;
+};
+
+struct csi_lane_params_t {
+ uint16_t csi_lane_assign;
+ uint8_t csi_lane_mask;
+ uint8_t csi_if;
+ uint8_t csid_core[2];
+ uint8_t csi_phy_sel;
+};
+
+struct msm_camera_csid_lut_params {
+ uint8_t num_cid;
+ struct msm_camera_csid_vc_cfg *vc_cfg;
+};
+
+struct msm_camera_csid_params {
+ uint8_t lane_cnt;
+ uint16_t lane_assign;
+ uint8_t phy_sel;
+ struct msm_camera_csid_lut_params lut_params;
+};
+
+struct msm_camera_csiphy_params {
+ uint8_t lane_cnt;
+ uint8_t settle_cnt;
+ uint16_t lane_mask;
+ uint8_t combo_mode;
+ uint8_t csid_core;
+};
+
+struct msm_camera_csi2_params {
+ struct msm_camera_csid_params csid_params;
+ struct msm_camera_csiphy_params csiphy_params;
+};
+
+enum msm_camera_csi_data_format {
+ CSI_8BIT,
+ CSI_10BIT,
+ CSI_12BIT,
+};
+
+struct msm_camera_csi_params {
+ enum msm_camera_csi_data_format data_format;
+ uint8_t lane_cnt;
+ uint8_t lane_assign;
+ uint8_t settle_cnt;
+ uint8_t dpcm_scheme;
+};
+
+enum csic_cfg_type_t {
+ CSIC_INIT,
+ CSIC_CFG,
+};
+
+struct csic_cfg_data {
+ enum csic_cfg_type_t cfgtype;
+ struct msm_camera_csi_params *csic_params;
+};
+
+enum csid_cfg_type_t {
+ CSID_INIT,
+ CSID_CFG,
+};
+
+struct csid_cfg_data {
+ enum csid_cfg_type_t cfgtype;
+ union {
+ uint32_t csid_version;
+ struct msm_camera_csid_params *csid_params;
+ } cfg;
+};
+
+enum csiphy_cfg_type_t {
+ CSIPHY_INIT,
+ CSIPHY_CFG,
+};
+
+struct csiphy_cfg_data {
+ enum csiphy_cfg_type_t cfgtype;
+ struct msm_camera_csiphy_params *csiphy_params;
+};
+
+#define CSI_EMBED_DATA 0x12
+#define CSI_RESERVED_DATA_0 0x13
+#define CSI_YUV422_8 0x1E
+#define CSI_RAW8 0x2A
+#define CSI_RAW10 0x2B
+#define CSI_RAW12 0x2C
+
+#define CSI_DECODE_6BIT 0
+#define CSI_DECODE_8BIT 1
+#define CSI_DECODE_10BIT 2
+#define CSI_DECODE_DPCM_10_8_10 5
+
+#define ISPIF_STREAM(intf, action, vfe) (((intf)<<ISPIF_S_STREAM_SHIFT)+\
+ (action)+((vfe)<<ISPIF_VFE_INTF_SHIFT))
+#define ISPIF_ON_FRAME_BOUNDARY (0x01 << 0)
+#define ISPIF_OFF_FRAME_BOUNDARY (0x01 << 1)
+#define ISPIF_OFF_IMMEDIATELY (0x01 << 2)
+#define ISPIF_S_STREAM_SHIFT 4
+#define ISPIF_VFE_INTF_SHIFT 12
+
+#define PIX_0 (0x01 << 0)
+#define RDI_0 (0x01 << 1)
+#define PIX_1 (0x01 << 2)
+#define RDI_1 (0x01 << 3)
+#define RDI_2 (0x01 << 4)
+
+enum msm_ispif_vfe_intf {
+ VFE0,
+ VFE1,
+ VFE_MAX,
+};
+
+enum msm_ispif_intftype {
+ PIX0,
+ RDI0,
+ PIX1,
+ RDI1,
+ RDI2,
+ INTF_MAX,
+};
+
+enum msm_ispif_vc {
+ VC0,
+ VC1,
+ VC2,
+ VC3,
+};
+
+enum msm_ispif_cid {
+ CID0,
+ CID1,
+ CID2,
+ CID3,
+ CID4,
+ CID5,
+ CID6,
+ CID7,
+ CID8,
+ CID9,
+ CID10,
+ CID11,
+ CID12,
+ CID13,
+ CID14,
+ CID15,
+};
+
+struct msm_ispif_params {
+ uint8_t intftype;
+ uint16_t cid_mask;
+ uint8_t csid;
+ uint8_t vfe_intf;
+};
+
+struct msm_ispif_params_list {
+ uint32_t len;
+ struct msm_ispif_params params[4];
+};
+
+enum ispif_cfg_type_t {
+ ISPIF_INIT,
+ ISPIF_SET_CFG,
+ ISPIF_SET_ON_FRAME_BOUNDARY,
+ ISPIF_SET_OFF_FRAME_BOUNDARY,
+ ISPIF_SET_OFF_IMMEDIATELY,
+ ISPIF_RELEASE,
+};
+
+struct ispif_cfg_data {
+ enum ispif_cfg_type_t cfgtype;
+ union {
+ uint32_t csid_version;
+ int cmd;
+ struct msm_ispif_params_list ispif_params;
+ } cfg;
+};
+
+enum msm_camera_i2c_reg_addr_type {
+ MSM_CAMERA_I2C_BYTE_ADDR = 1,
+ MSM_CAMERA_I2C_WORD_ADDR,
+ MSM_CAMERA_I2C_3B_ADDR,
+ MSM_CAMERA_I2C_DWORD_ADDR,
+};
+#define MSM_CAMERA_I2C_DWORD_ADDR MSM_CAMERA_I2C_DWORD_ADDR
+
+struct msm_camera_i2c_reg_array {
+ uint16_t reg_addr;
+ uint16_t reg_data;
+};
+
+enum msm_camera_i2c_data_type {
+ MSM_CAMERA_I2C_BYTE_DATA = 1,
+ MSM_CAMERA_I2C_WORD_DATA,
+ MSM_CAMERA_I2C_SET_BYTE_MASK,
+ MSM_CAMERA_I2C_UNSET_BYTE_MASK,
+ MSM_CAMERA_I2C_SET_WORD_MASK,
+ MSM_CAMERA_I2C_UNSET_WORD_MASK,
+ MSM_CAMERA_I2C_SET_BYTE_WRITE_MASK_DATA,
+};
+
+struct msm_camera_i2c_reg_setting {
+ struct msm_camera_i2c_reg_array *reg_setting;
+ uint16_t size;
+ enum msm_camera_i2c_reg_addr_type addr_type;
+ enum msm_camera_i2c_data_type data_type;
+ uint16_t delay;
+};
+
+enum oem_setting_type {
+ I2C_READ = 1,
+ I2C_WRITE,
+ GPIO_OP,
+ EEPROM_READ,
+ VREG_SET,
+ CLK_SET,
+};
+
+struct sensor_oem_setting {
+ enum oem_setting_type type;
+ void *data;
+};
+
+enum camera_vreg_type {
+ REG_LDO,
+ REG_VS,
+ REG_GPIO,
+};
+
+enum msm_camera_vreg_name_t {
+ CAM_VDIG,
+ CAM_VIO,
+ CAM_VANA,
+ CAM_VAF,
+ CAM_VREG_MAX,
+};
+
+struct msm_camera_csi_lane_params {
+ uint16_t csi_lane_assign;
+ uint16_t csi_lane_mask;
+};
+
+struct camera_vreg_t {
+ const char *reg_name;
+ int min_voltage;
+ int max_voltage;
+ int op_mode;
+ uint32_t delay;
+};
+
+struct msm_camera_vreg_setting {
+ struct camera_vreg_t *cam_vreg;
+ uint16_t num_vreg;
+ uint8_t enable;
+};
+
+struct msm_cam_clk_info {
+ const char *clk_name;
+ long clk_rate;
+ uint32_t delay;
+};
+
+struct msm_cam_clk_setting {
+ struct msm_cam_clk_info *clk_info;
+ uint16_t num_clk_info;
+ uint8_t enable;
+};
+
+struct sensor_cfg_data {
+ int cfgtype;
+ int mode;
+ int rs;
+ uint8_t max_steps;
+
+ union {
+ int8_t effect;
+ uint8_t lens_shading;
+ uint16_t prevl_pf;
+ uint16_t prevp_pl;
+ uint16_t pictl_pf;
+ uint16_t pictp_pl;
+ uint32_t pict_max_exp_lc;
+ uint16_t p_fps;
+ uint8_t iso_type;
+ struct sensor_init_cfg init_info;
+ struct sensor_pict_fps gfps;
+ struct exp_gain_cfg exp_gain;
+ struct focus_cfg focus;
+ struct fps_cfg fps;
+ struct wb_info_cfg wb_info;
+ struct sensor_3d_exp_cfg sensor_3d_exp;
+ struct sensor_calib_data calib_info;
+ struct sensor_output_info_t output_info;
+ struct msm_eeprom_data_t eeprom_data;
+ struct csi_lane_params_t csi_lane_params;
+ /* QRD */
+ uint16_t antibanding;
+ uint8_t contrast;
+ uint8_t saturation;
+ uint8_t sharpness;
+ int8_t brightness;
+ int ae_mode;
+ uint8_t wb_val;
+ int8_t exp_compensation;
+ uint32_t pclk;
+ struct cord aec_cord;
+ int is_autoflash;
+ struct mirror_flip mirror_flip;
+ void *setting;
+ } cfg;
+};
+
+enum gpio_operation_type {
+ GPIO_REQUEST,
+ GPIO_FREE,
+ GPIO_SET_DIRECTION_OUTPUT,
+ GPIO_SET_DIRECTION_INPUT,
+ GPIO_GET_VALUE,
+ GPIO_SET_VALUE,
+};
+
+struct msm_cam_gpio_operation {
+ enum gpio_operation_type op_type;
+ unsigned int address;
+ int value;
+ const char *tag;
+};
+
+struct damping_params_t {
+ uint32_t damping_step;
+ uint32_t damping_delay;
+ uint32_t hw_params;
+};
+
+enum actuator_type {
+ ACTUATOR_VCM,
+ ACTUATOR_PIEZO,
+ ACTUATOR_HVCM,
+ ACTUATOR_BIVCM,
+};
+
+enum msm_actuator_data_type {
+ MSM_ACTUATOR_BYTE_DATA = 1,
+ MSM_ACTUATOR_WORD_DATA,
+};
+
+enum msm_actuator_addr_type {
+ MSM_ACTUATOR_BYTE_ADDR = 1,
+ MSM_ACTUATOR_WORD_ADDR,
+};
+
+enum msm_actuator_write_type {
+ MSM_ACTUATOR_WRITE_HW_DAMP,
+ MSM_ACTUATOR_WRITE_DAC,
+ MSM_ACTUATOR_WRITE,
+ MSM_ACTUATOR_WRITE_DIR_REG,
+ MSM_ACTUATOR_POLL,
+ MSM_ACTUATOR_READ_WRITE,
+};
+
+struct msm_actuator_reg_params_t {
+ enum msm_actuator_write_type reg_write_type;
+ uint32_t hw_mask;
+ uint16_t reg_addr;
+ uint16_t hw_shift;
+ uint16_t data_type;
+ uint16_t addr_type;
+ uint16_t reg_data;
+ uint16_t delay;
+};
+
+struct reg_settings_t {
+ uint16_t reg_addr;
+ uint16_t reg_data;
+};
+
+struct region_params_t {
+ /* [0] = ForwardDirection Macro boundary
+ * [1] = ReverseDirection Inf boundary
+ */
+ uint16_t step_bound[2];
+ uint16_t code_per_step;
+};
+
+struct msm_actuator_move_params_t {
+ int8_t dir;
+ int8_t sign_dir;
+ int16_t dest_step_pos;
+ int32_t num_steps;
+ struct damping_params_t __user *ringing_params;
+};
+
+struct msm_actuator_tuning_params_t {
+ int16_t initial_code;
+ uint16_t pwd_step;
+ uint16_t region_size;
+ uint32_t total_steps;
+ struct region_params_t __user *region_params;
+};
+
+struct msm_actuator_params_t {
+ enum actuator_type act_type;
+ uint8_t reg_tbl_size;
+ uint16_t data_size;
+ uint16_t init_setting_size;
+ uint32_t i2c_addr;
+ enum msm_actuator_addr_type i2c_addr_type;
+ enum msm_actuator_data_type i2c_data_type;
+ struct msm_actuator_reg_params_t __user *reg_tbl_params;
+ struct reg_settings_t __user *init_settings;
+};
+
+struct msm_actuator_set_info_t {
+ struct msm_actuator_params_t actuator_params;
+ struct msm_actuator_tuning_params_t af_tuning_params;
+};
+
+struct msm_actuator_get_info_t {
+ uint32_t focal_length_num;
+ uint32_t focal_length_den;
+ uint32_t f_number_num;
+ uint32_t f_number_den;
+ uint32_t f_pix_num;
+ uint32_t f_pix_den;
+ uint32_t total_f_dist_num;
+ uint32_t total_f_dist_den;
+ uint32_t hor_view_angle_num;
+ uint32_t hor_view_angle_den;
+ uint32_t ver_view_angle_num;
+ uint32_t ver_view_angle_den;
+};
+
+enum af_camera_name {
+ ACTUATOR_MAIN_CAM_0,
+ ACTUATOR_MAIN_CAM_1,
+ ACTUATOR_MAIN_CAM_2,
+ ACTUATOR_MAIN_CAM_3,
+ ACTUATOR_MAIN_CAM_4,
+ ACTUATOR_MAIN_CAM_5,
+ ACTUATOR_WEB_CAM_0,
+ ACTUATOR_WEB_CAM_1,
+ ACTUATOR_WEB_CAM_2,
+};
+
+struct msm_actuator_cfg_data {
+ int cfgtype;
+ uint8_t is_af_supported;
+ union {
+ struct msm_actuator_move_params_t move;
+ struct msm_actuator_set_info_t set_info;
+ struct msm_actuator_get_info_t get_info;
+ enum af_camera_name cam_name;
+ } cfg;
+};
+
+struct msm_eeprom_support {
+ uint16_t is_supported;
+ uint16_t size;
+ uint16_t index;
+ uint16_t qvalue;
+};
+
+struct msm_calib_wb {
+ uint16_t r_over_g;
+ uint16_t b_over_g;
+ uint16_t gr_over_gb;
+};
+
+struct msm_calib_af {
+ uint16_t macro_dac;
+ uint16_t inf_dac;
+ uint16_t start_dac;
+};
+
+struct msm_calib_lsc {
+ uint16_t r_gain[221];
+ uint16_t b_gain[221];
+ uint16_t gr_gain[221];
+ uint16_t gb_gain[221];
+};
+
+struct pixel_t {
+ int x;
+ int y;
+};
+
+struct msm_calib_dpc {
+ uint16_t validcount;
+ struct pixel_t snapshot_coord[128];
+ struct pixel_t preview_coord[128];
+ struct pixel_t video_coord[128];
+};
+
+struct msm_calib_raw {
+ uint8_t *data;
+ uint32_t size;
+};
+
+struct msm_camera_eeprom_info_t {
+ struct msm_eeprom_support af;
+ struct msm_eeprom_support wb;
+ struct msm_eeprom_support lsc;
+ struct msm_eeprom_support dpc;
+ struct msm_eeprom_support raw;
+};
+
+struct msm_eeprom_cfg_data {
+ int cfgtype;
+ uint8_t is_eeprom_supported;
+ union {
+ struct msm_eeprom_data_t get_data;
+ struct msm_camera_eeprom_info_t get_info;
+ } cfg;
+};
+
+struct sensor_large_data {
+ int cfgtype;
+ union {
+ struct sensor_3d_cali_data_t sensor_3d_cali_data;
+ } data;
+};
+
+enum sensor_type_t {
+ BAYER,
+ YUV,
+ JPEG_SOC,
+};
+
+enum flash_type {
+ LED_FLASH,
+ STROBE_FLASH,
+};
+
+enum strobe_flash_ctrl_type {
+ STROBE_FLASH_CTRL_INIT,
+ STROBE_FLASH_CTRL_CHARGE,
+ STROBE_FLASH_CTRL_RELEASE
+};
+
+struct strobe_flash_ctrl_data {
+ enum strobe_flash_ctrl_type type;
+ int charge_en;
+};
+
+struct msm_camera_info {
+ int num_cameras;
+ uint8_t has_3d_support[MSM_MAX_CAMERA_SENSORS];
+ uint8_t is_internal_cam[MSM_MAX_CAMERA_SENSORS];
+ uint32_t s_mount_angle[MSM_MAX_CAMERA_SENSORS];
+ const char *video_dev_name[MSM_MAX_CAMERA_SENSORS];
+ enum sensor_type_t sensor_type[MSM_MAX_CAMERA_SENSORS];
+};
+
+struct msm_cam_config_dev_info {
+ int num_config_nodes;
+ const char *config_dev_name[MSM_MAX_CAMERA_CONFIGS];
+ int config_dev_id[MSM_MAX_CAMERA_CONFIGS];
+};
+
+struct msm_mctl_node_info {
+ int num_mctl_nodes;
+ const char *mctl_node_name[MSM_MAX_CAMERA_SENSORS];
+};
+
+struct flash_ctrl_data {
+ int flashtype;
+ union {
+ int led_state;
+ struct strobe_flash_ctrl_data strobe_ctrl;
+ } ctrl_data;
+};
+
+#define GET_NAME 0
+#define GET_PREVIEW_LINE_PER_FRAME 1
+#define GET_PREVIEW_PIXELS_PER_LINE 2
+#define GET_SNAPSHOT_LINE_PER_FRAME 3
+#define GET_SNAPSHOT_PIXELS_PER_LINE 4
+#define GET_SNAPSHOT_FPS 5
+#define GET_SNAPSHOT_MAX_EP_LINE_CNT 6
+
+struct msm_camsensor_info {
+ char name[MAX_SENSOR_NAME];
+ uint8_t flash_enabled;
+ uint8_t strobe_flash_enabled;
+ uint8_t actuator_enabled;
+ uint8_t ispif_supported;
+ int8_t total_steps;
+ uint8_t support_3d;
+ enum flash_type flashtype;
+ enum sensor_type_t sensor_type;
+ uint32_t pxlcode; /* enum v4l2_mbus_pixelcode */
+ uint32_t camera_type; /* msm_camera_type */
+ int mount_angle;
+ uint32_t max_width;
+ uint32_t max_height;
+};
+
+#define V4L2_SINGLE_PLANE 0
+#define V4L2_MULTI_PLANE_Y 0
+#define V4L2_MULTI_PLANE_CBCR 1
+#define V4L2_MULTI_PLANE_CB 1
+#define V4L2_MULTI_PLANE_CR 2
+
+struct plane_data {
+ int plane_id;
+ uint32_t offset;
+ unsigned long size;
+};
+
+struct img_plane_info {
+ uint32_t width;
+ uint32_t height;
+ uint32_t pixelformat;
+ uint8_t buffer_type; /*Single/Multi planar*/
+ uint8_t output_port;
+ uint32_t ext_mode;
+ uint8_t num_planes;
+ struct plane_data plane[MAX_PLANES];
+ uint32_t sp_y_offset;
+ uint32_t inst_handle;
+};
+
+#define QCAMERA_NAME "qcamera"
+#define QCAMERA_SERVER_NAME "qcamera_server"
+#define QCAMERA_DEVICE_GROUP_ID 1
+#define QCAMERA_VNODE_GROUP_ID 2
+
+enum msm_cam_subdev_type {
+ CSIPHY_DEV,
+ CSID_DEV,
+ CSIC_DEV,
+ ISPIF_DEV,
+ VFE_DEV,
+ AXI_DEV,
+ VPE_DEV,
+ SENSOR_DEV,
+ ACTUATOR_DEV,
+ EEPROM_DEV,
+ GESTURE_DEV,
+ IRQ_ROUTER_DEV,
+ CPP_DEV,
+ CCI_DEV,
+ FLASH_DEV,
+};
+
+struct msm_mctl_set_sdev_data {
+ uint32_t revision;
+ enum msm_cam_subdev_type sdev_type;
+};
+
+#define MSM_CAM_V4L2_IOCTL_GET_CAMERA_INFO \
+ _IOWR('V', BASE_VIDIOC_PRIVATE + 1, struct msm_camera_v4l2_ioctl_t)
+
+#define MSM_CAM_V4L2_IOCTL_GET_CONFIG_INFO \
+ _IOWR('V', BASE_VIDIOC_PRIVATE + 2, struct msm_camera_v4l2_ioctl_t)
+
+#define MSM_CAM_V4L2_IOCTL_GET_MCTL_INFO \
+ _IOWR('V', BASE_VIDIOC_PRIVATE + 3, struct msm_camera_v4l2_ioctl_t)
+
+#define MSM_CAM_V4L2_IOCTL_CTRL_CMD_DONE \
+ _IOWR('V', BASE_VIDIOC_PRIVATE + 4, struct msm_camera_v4l2_ioctl_t)
+
+#define MSM_CAM_V4L2_IOCTL_GET_EVENT_PAYLOAD \
+ _IOWR('V', BASE_VIDIOC_PRIVATE + 5, struct msm_camera_v4l2_ioctl_t)
+
+#define MSM_CAM_IOCTL_SEND_EVENT \
+ _IOWR('V', BASE_VIDIOC_PRIVATE + 6, struct v4l2_event)
+
+#define MSM_CAM_V4L2_IOCTL_CFG_VPE \
+ _IOWR('V', BASE_VIDIOC_PRIVATE + 7, struct msm_vpe_cfg_cmd)
+
+#define MSM_CAM_V4L2_IOCTL_PRIVATE_S_CTRL \
+ _IOWR('V', BASE_VIDIOC_PRIVATE + 8, struct msm_camera_v4l2_ioctl_t)
+
+#define MSM_CAM_V4L2_IOCTL_PRIVATE_G_CTRL \
+ _IOWR('V', BASE_VIDIOC_PRIVATE + 9, struct msm_camera_v4l2_ioctl_t)
+
+#define MSM_CAM_V4L2_IOCTL_PRIVATE_GENERAL \
+ _IOW('V', BASE_VIDIOC_PRIVATE + 10, struct msm_camera_v4l2_ioctl_t)
+
+#define VIDIOC_MSM_VPE_INIT \
+ _IO('V', BASE_VIDIOC_PRIVATE + 15)
+
+#define VIDIOC_MSM_VPE_RELEASE \
+ _IO('V', BASE_VIDIOC_PRIVATE + 16)
+
+#define VIDIOC_MSM_VPE_CFG \
+ _IOWR('V', BASE_VIDIOC_PRIVATE + 17, struct msm_mctl_pp_params *)
+
+#define VIDIOC_MSM_AXI_INIT \
+ _IOWR('V', BASE_VIDIOC_PRIVATE + 18, uint8_t *)
+
+#define VIDIOC_MSM_AXI_RELEASE \
+ _IO('V', BASE_VIDIOC_PRIVATE + 19)
+
+#define VIDIOC_MSM_AXI_CFG \
+ _IOWR('V', BASE_VIDIOC_PRIVATE + 20, void *)
+
+#define VIDIOC_MSM_AXI_IRQ \
+ _IOWR('V', BASE_VIDIOC_PRIVATE + 21, void *)
+
+#define VIDIOC_MSM_AXI_BUF_CFG \
+ _IOWR('V', BASE_VIDIOC_PRIVATE + 22, void *)
+
+#define VIDIOC_MSM_AXI_RDI_COUNT_UPDATE \
+ _IOWR('V', BASE_VIDIOC_PRIVATE + 23, void *)
+
+#define VIDIOC_MSM_VFE_INIT \
+ _IO('V', BASE_VIDIOC_PRIVATE + 24)
+
+#define VIDIOC_MSM_VFE_RELEASE \
+ _IO('V', BASE_VIDIOC_PRIVATE + 25)
+
+struct msm_camera_v4l2_ioctl_t {
+ uint32_t id;
+ uint32_t len;
+ uint32_t trans_code;
+ void __user *ioctl_ptr;
+};
+
+struct msm_camera_vfe_params_t {
+ uint32_t operation_mode;
+ uint32_t capture_count;
+ uint8_t skip_reset;
+ uint8_t stop_immediately;
+ uint16_t port_info;
+ uint32_t inst_handle;
+ uint16_t cmd_type;
+};
+
+enum msm_camss_irq_idx {
+ CAMERA_SS_IRQ_0,
+ CAMERA_SS_IRQ_1,
+ CAMERA_SS_IRQ_2,
+ CAMERA_SS_IRQ_3,
+ CAMERA_SS_IRQ_4,
+ CAMERA_SS_IRQ_5,
+ CAMERA_SS_IRQ_6,
+ CAMERA_SS_IRQ_7,
+ CAMERA_SS_IRQ_8,
+ CAMERA_SS_IRQ_9,
+ CAMERA_SS_IRQ_10,
+ CAMERA_SS_IRQ_11,
+ CAMERA_SS_IRQ_12,
+ CAMERA_SS_IRQ_MAX
+};
+
+enum msm_cam_hw_idx {
+ MSM_CAM_HW_MICRO,
+ MSM_CAM_HW_CCI,
+ MSM_CAM_HW_CSI0,
+ MSM_CAM_HW_CSI1,
+ MSM_CAM_HW_CSI2,
+ MSM_CAM_HW_CSI3,
+ MSM_CAM_HW_ISPIF,
+ MSM_CAM_HW_CPP,
+ MSM_CAM_HW_VFE0,
+ MSM_CAM_HW_VFE1,
+ MSM_CAM_HW_JPEG0,
+ MSM_CAM_HW_JPEG1,
+ MSM_CAM_HW_JPEG2,
+ MSM_CAM_HW_MAX
+};
+
+struct msm_camera_irq_cfg {
+ /* Bit mask of all the camera hardwares that needs to
+ * be composited into a single IRQ to the MSM.
+ * Current usage: (may be updated based on hw changes)
+ * Bits 31:13 - Reserved.
+ * Bits 12:0
+ * 12 - MSM_CAM_HW_JPEG2
+ * 11 - MSM_CAM_HW_JPEG1
+ * 10 - MSM_CAM_HW_JPEG0
+ * 9 - MSM_CAM_HW_VFE1
+ * 8 - MSM_CAM_HW_VFE0
+ * 7 - MSM_CAM_HW_CPP
+ * 6 - MSM_CAM_HW_ISPIF
+ * 5 - MSM_CAM_HW_CSI3
+ * 4 - MSM_CAM_HW_CSI2
+ * 3 - MSM_CAM_HW_CSI1
+ * 2 - MSM_CAM_HW_CSI0
+ * 1 - MSM_CAM_HW_CCI
+ * 0 - MSM_CAM_HW_MICRO
+ */
+ uint32_t cam_hw_mask;
+ uint8_t irq_idx;
+ uint8_t num_hwcore;
+};
+
+#define MSM_IRQROUTER_CFG_COMPIRQ \
+ _IOWR('V', BASE_VIDIOC_PRIVATE, void __user *)
+
+#define MAX_NUM_CPP_STRIPS 8
+
+enum msm_cpp_frame_type {
+ MSM_CPP_OFFLINE_FRAME,
+ MSM_CPP_REALTIME_FRAME,
+};
+
+struct msm_cpp_frame_info_t {
+ int32_t frame_id;
+ uint32_t inst_id;
+ uint32_t client_id;
+ enum msm_cpp_frame_type frame_type;
+ uint32_t num_strips;
+};
+
+struct msm_ver_num_info {
+ uint32_t main;
+ uint32_t minor;
+ uint32_t rev;
+};
+
+#define VIDIOC_MSM_CPP_CFG \
+ _IOWR('V', BASE_VIDIOC_PRIVATE, struct msm_camera_v4l2_ioctl_t)
+
+#define VIDIOC_MSM_CPP_GET_EVENTPAYLOAD \
+ _IOWR('V', BASE_VIDIOC_PRIVATE + 1, struct msm_camera_v4l2_ioctl_t)
+
+#define VIDIOC_MSM_CPP_GET_INST_INFO \
+ _IOWR('V', BASE_VIDIOC_PRIVATE + 2, struct msm_camera_v4l2_ioctl_t)
+
+#define V4L2_EVENT_CPP_FRAME_DONE (V4L2_EVENT_PRIVATE_START + 0)
+
+/* Instance Handle - inst_handle
+ * Data bundle containing the information about where
+ * to get a buffer for a particular camera instance.
+ * This is a bitmask containing the following data:
+ * Buffer Handle Bitmask:
+ * ------------------------------------
+ * Bits : Purpose
+ * ------------------------------------
+ * 31 : is Dev ID valid?
+ * 30 - 24 : Dev ID.
+ * 23 : is Image mode valid?
+ * 22 - 16 : Image mode.
+ * 15 : is MCTL PP inst idx valid?
+ * 14 - 8 : MCTL PP inst idx.
+ * 7 : is Video inst idx valid?
+ * 6 - 0 : Video inst idx.
+ */
+#define CLR_DEVID_MODE(handle) (handle &= 0x00FFFFFF)
+#define SET_DEVID_MODE(handle, data) \
+ (handle |= ((0x1 << 31) | ((data & 0x7F) << 24)))
+#define GET_DEVID_MODE(handle) \
+ ((handle & 0x80000000) ? ((handle & 0x7F000000) >> 24) : 0xFF)
+
+#define CLR_IMG_MODE(handle) (handle &= 0xFF00FFFF)
+#define SET_IMG_MODE(handle, data) \
+ (handle |= ((0x1 << 23) | ((data & 0x7F) << 16)))
+#define GET_IMG_MODE(handle) \
+ ((handle & 0x800000) ? ((handle & 0x7F0000) >> 16) : 0xFF)
+
+#define CLR_MCTLPP_INST_IDX(handle) (handle &= 0xFFFF00FF)
+#define SET_MCTLPP_INST_IDX(handle, data) \
+ (handle |= ((0x1 << 15) | ((data & 0x7F) << 8)))
+#define GET_MCTLPP_INST_IDX(handle) \
+ ((handle & 0x8000) ? ((handle & 0x7F00) >> 8) : 0xFF)
+
+#define CLR_VIDEO_INST_IDX(handle) (handle &= 0xFFFFFF00)
+#define GET_VIDEO_INST_IDX(handle) \
+ ((handle & 0x80) ? (handle & 0x7F) : 0xFF)
+#define SET_VIDEO_INST_IDX(handle, data) \
+ (handle |= (0x1 << 7) | (data & 0x7F))
+#endif
diff --git a/include/uapi/media/msm_camsensor_sdk.h b/include/uapi/media/msm_camsensor_sdk.h
new file mode 100644
index 0000000..5266c02
--- /dev/null
+++ b/include/uapi/media/msm_camsensor_sdk.h
@@ -0,0 +1,431 @@
+#ifndef __UAPI_LINUX_MSM_CAMSENSOR_SDK_H
+#define __UAPI_LINUX_MSM_CAMSENSOR_SDK_H
+
+#include <linux/videodev2.h>
+
+#define KVERSION 0x1
+
+#define MAX_POWER_CONFIG 12
+#define GPIO_OUT_LOW (0 << 1)
+#define GPIO_OUT_HIGH (1 << 1)
+#define CSI_EMBED_DATA 0x12
+#define CSI_RESERVED_DATA_0 0x13
+#define CSI_YUV422_8 0x1E
+#define CSI_RAW8 0x2A
+#define CSI_RAW10 0x2B
+#define CSI_RAW12 0x2C
+#define CSI_DECODE_6BIT 0
+#define CSI_DECODE_8BIT 1
+#define CSI_DECODE_10BIT 2
+#define CSI_DECODE_12BIT 3
+#define CSI_DECODE_DPCM_10_6_10 4
+#define CSI_DECODE_DPCM_10_8_10 5
+#define MAX_CID 16
+#define I2C_SEQ_REG_DATA_MAX 1024
+#define I2C_REG_DATA_MAX (8*1024)
+
+#define MSM_V4L2_PIX_FMT_META v4l2_fourcc('M', 'E', 'T', 'A') /* META */
+#define MSM_V4L2_PIX_FMT_SBGGR14 v4l2_fourcc('B', 'G', '1', '4')
+ /* 14 BGBG.. GRGR.. */
+#define MSM_V4L2_PIX_FMT_SGBRG14 v4l2_fourcc('G', 'B', '1', '4')
+ /* 14 GBGB.. RGRG.. */
+#define MSM_V4L2_PIX_FMT_SGRBG14 v4l2_fourcc('B', 'A', '1', '4')
+ /* 14 GRGR.. BGBG.. */
+#define MSM_V4L2_PIX_FMT_SRGGB14 v4l2_fourcc('R', 'G', '1', '4')
+ /* 14 RGRG.. GBGB.. */
+
+#define MAX_ACTUATOR_REG_TBL_SIZE 8
+#define MAX_ACTUATOR_REGION 5
+#define NUM_ACTUATOR_DIR 2
+#define MAX_ACTUATOR_SCENARIO 8
+#define MAX_ACT_MOD_NAME_SIZE 32
+#define MAX_ACT_NAME_SIZE 32
+#define MAX_ACTUATOR_INIT_SET 120
+#define MAX_I2C_REG_SET 12
+
+#define MAX_LED_TRIGGERS 3
+
+#define MSM_EEPROM_MEMORY_MAP_MAX_SIZE 80
+#define MSM_EEPROM_MAX_MEM_MAP_CNT 8
+
+#define MSM_SENSOR_BYPASS_VIDEO_NODE 1
+
+enum msm_sensor_camera_id_t {
+ CAMERA_0,
+ CAMERA_1,
+ CAMERA_2,
+ CAMERA_3,
+ MAX_CAMERAS,
+};
+
+enum i2c_freq_mode_t {
+ I2C_STANDARD_MODE,
+ I2C_FAST_MODE,
+ I2C_CUSTOM_MODE,
+ I2C_FAST_PLUS_MODE,
+ I2C_MAX_MODES,
+};
+
+enum camb_position_t {
+ BACK_CAMERA_B,
+ FRONT_CAMERA_B,
+ AUX_CAMERA_B = 0x100,
+ INVALID_CAMERA_B,
+};
+
+enum msm_sensor_power_seq_type_t {
+ SENSOR_CLK,
+ SENSOR_GPIO,
+ SENSOR_VREG,
+ SENSOR_I2C_MUX,
+ SENSOR_I2C,
+};
+
+enum msm_camera_i2c_reg_addr_type {
+ MSM_CAMERA_I2C_BYTE_ADDR = 1,
+ MSM_CAMERA_I2C_WORD_ADDR,
+ MSM_CAMERA_I2C_3B_ADDR,
+ MSM_CAMERA_I2C_DWORD_ADDR,
+ MSM_CAMERA_I2C_ADDR_TYPE_MAX,
+};
+#define MSM_CAMERA_I2C_DWORD_ADDR MSM_CAMERA_I2C_DWORD_ADDR
+
+enum msm_camera_i2c_data_type {
+ MSM_CAMERA_I2C_BYTE_DATA = 1,
+ MSM_CAMERA_I2C_WORD_DATA,
+ MSM_CAMERA_I2C_DWORD_DATA,
+ MSM_CAMERA_I2C_SET_BYTE_MASK,
+ MSM_CAMERA_I2C_UNSET_BYTE_MASK,
+ MSM_CAMERA_I2C_SET_WORD_MASK,
+ MSM_CAMERA_I2C_UNSET_WORD_MASK,
+ MSM_CAMERA_I2C_SET_BYTE_WRITE_MASK_DATA,
+ MSM_CAMERA_I2C_DATA_TYPE_MAX,
+};
+
+enum msm_sensor_power_seq_gpio_t {
+ SENSOR_GPIO_RESET,
+ SENSOR_GPIO_STANDBY,
+ SENSOR_GPIO_AF_PWDM,
+ SENSOR_GPIO_VIO,
+ SENSOR_GPIO_VANA,
+ SENSOR_GPIO_VDIG,
+ SENSOR_GPIO_VAF,
+ SENSOR_GPIO_FL_EN,
+ SENSOR_GPIO_FL_NOW,
+ SENSOR_GPIO_FL_RESET,
+ SENSOR_GPIO_CUSTOM1,
+ SENSOR_GPIO_CUSTOM2,
+ SENSOR_GPIO_CUSTOM3,
+ SENSOR_GPIO_MAX,
+};
+#define SENSOR_GPIO_CUSTOM3 SENSOR_GPIO_CUSTOM3
+
+enum msm_ir_cut_filter_gpio_t {
+ IR_CUT_FILTER_GPIO_P = 0,
+ IR_CUT_FILTER_GPIO_M,
+ IR_CUT_FILTER_GPIO_MAX,
+};
+#define IR_CUT_FILTER_GPIO_P IR_CUT_FILTER_GPIO_P
+#define IR_CUT_FILTER_GPIO_M IR_CUT_FILTER_GPIO_M
+#define R_CUT_FILTER_GPIO_MAX IR_CUT_FILTER_GPIO_MAX
+
+enum msm_camera_vreg_name_t {
+ CAM_VDIG,
+ CAM_VIO,
+ CAM_VANA,
+ CAM_VAF,
+ CAM_V_CUSTOM1,
+ CAM_V_CUSTOM2,
+ CAM_VREG_MAX,
+};
+
+enum msm_sensor_clk_type_t {
+ SENSOR_CAM_MCLK,
+ SENSOR_CAM_CLK,
+ SENSOR_CAM_CLK_MAX,
+};
+
+enum camerab_mode_t {
+ CAMERA_MODE_2D_B = (1<<0),
+ CAMERA_MODE_3D_B = (1<<1),
+ CAMERA_MODE_INVALID = (1<<2),
+};
+
+enum msm_actuator_data_type {
+ MSM_ACTUATOR_BYTE_DATA = 1,
+ MSM_ACTUATOR_WORD_DATA,
+};
+
+enum msm_actuator_addr_type {
+ MSM_ACTUATOR_BYTE_ADDR = 1,
+ MSM_ACTUATOR_WORD_ADDR,
+};
+
+enum msm_actuator_write_type {
+ MSM_ACTUATOR_WRITE_HW_DAMP,
+ MSM_ACTUATOR_WRITE_DAC,
+ MSM_ACTUATOR_WRITE,
+ MSM_ACTUATOR_WRITE_DIR_REG,
+ MSM_ACTUATOR_POLL,
+ MSM_ACTUATOR_READ_WRITE,
+};
+
+enum msm_actuator_i2c_operation {
+ MSM_ACT_WRITE = 0,
+ MSM_ACT_POLL,
+};
+
+enum actuator_type {
+ ACTUATOR_VCM,
+ ACTUATOR_PIEZO,
+ ACTUATOR_HVCM,
+ ACTUATOR_BIVCM,
+};
+
+enum msm_flash_driver_type {
+ FLASH_DRIVER_PMIC,
+ FLASH_DRIVER_I2C,
+ FLASH_DRIVER_GPIO,
+ FLASH_DRIVER_DEFAULT
+};
+
+enum msm_flash_cfg_type_t {
+ CFG_FLASH_INIT,
+ CFG_FLASH_RELEASE,
+ CFG_FLASH_OFF,
+ CFG_FLASH_LOW,
+ CFG_FLASH_HIGH,
+};
+
+enum msm_ir_led_cfg_type_t {
+ CFG_IR_LED_INIT = 0,
+ CFG_IR_LED_RELEASE,
+ CFG_IR_LED_OFF,
+ CFG_IR_LED_ON,
+};
+#define CFG_IR_LED_INIT CFG_IR_LED_INIT
+#define CFG_IR_LED_RELEASE CFG_IR_LED_RELEASE
+#define CFG_IR_LED_OFF CFG_IR_LED_OFF
+#define CFG_IR_LED_ON CFG_IR_LED_ON
+
+enum msm_laser_led_cfg_type_t {
+ CFG_LASER_LED_INIT,
+ CFG_LASER_LED_CONTROL,
+};
+#define CFG_LASER_LED_INIT CFG_LASER_LED_INIT
+#define CFG_LASER_LED_CONTROL CFG_LASER_LED_CONTROL
+
+enum msm_ir_cut_cfg_type_t {
+ CFG_IR_CUT_INIT = 0,
+ CFG_IR_CUT_RELEASE,
+ CFG_IR_CUT_OFF,
+ CFG_IR_CUT_ON,
+};
+#define CFG_IR_CUT_INIT CFG_IR_CUT_INIT
+#define CFG_IR_CUT_RELEASE CFG_IR_CUT_RELEASE
+#define CFG_IR_CUT_OFF CFG_IR_CUT_OFF
+#define CFG_IR_CUT_ON CFG_IR_CUT_ON
+
+enum msm_sensor_output_format_t {
+ MSM_SENSOR_BAYER,
+ MSM_SENSOR_YCBCR,
+ MSM_SENSOR_META,
+};
+
+struct msm_sensor_power_setting {
+ enum msm_sensor_power_seq_type_t seq_type;
+ unsigned short seq_val;
+ long config_val;
+ unsigned short delay;
+ void *data[10];
+};
+
+struct msm_sensor_power_setting_array {
+ struct msm_sensor_power_setting power_setting_a[MAX_POWER_CONFIG];
+ struct msm_sensor_power_setting *power_setting;
+ unsigned short size;
+ struct msm_sensor_power_setting power_down_setting_a[MAX_POWER_CONFIG];
+ struct msm_sensor_power_setting *power_down_setting;
+ unsigned short size_down;
+};
+
+enum msm_camera_i2c_operation {
+ MSM_CAM_WRITE = 0,
+ MSM_CAM_POLL,
+ MSM_CAM_READ,
+};
+
+struct msm_sensor_i2c_sync_params {
+ unsigned int cid;
+ int csid;
+ unsigned short line;
+ unsigned short delay;
+};
+
+struct msm_camera_reg_settings_t {
+ uint16_t reg_addr;
+ enum msm_camera_i2c_reg_addr_type addr_type;
+ uint16_t reg_data;
+ enum msm_camera_i2c_data_type data_type;
+ enum msm_camera_i2c_operation i2c_operation;
+ uint16_t delay;
+};
+
+struct msm_eeprom_mem_map_t {
+ int slave_addr;
+ struct msm_camera_reg_settings_t
+ mem_settings[MSM_EEPROM_MEMORY_MAP_MAX_SIZE];
+ int memory_map_size;
+};
+
+struct msm_eeprom_memory_map_array {
+ struct msm_eeprom_mem_map_t memory_map[MSM_EEPROM_MAX_MEM_MAP_CNT];
+ uint32_t msm_size_of_max_mappings;
+};
+
+struct msm_sensor_init_params {
+ /* mask of modes supported: 2D, 3D */
+ int modes_supported;
+ /* sensor position: front, back */
+ enum camb_position_t position;
+ /* sensor mount angle */
+ unsigned int sensor_mount_angle;
+};
+
+struct msm_sensor_id_info_t {
+ unsigned short sensor_id_reg_addr;
+ unsigned short sensor_id;
+ unsigned short sensor_id_mask;
+};
+
+struct msm_camera_sensor_slave_info {
+ char sensor_name[32];
+ char eeprom_name[32];
+ char actuator_name[32];
+ char ois_name[32];
+ char flash_name[32];
+ enum msm_sensor_camera_id_t camera_id;
+ unsigned short slave_addr;
+ enum i2c_freq_mode_t i2c_freq_mode;
+ enum msm_camera_i2c_reg_addr_type addr_type;
+ struct msm_sensor_id_info_t sensor_id_info;
+ struct msm_sensor_power_setting_array power_setting_array;
+ unsigned char is_init_params_valid;
+ struct msm_sensor_init_params sensor_init_params;
+ enum msm_sensor_output_format_t output_format;
+ uint8_t bypass_video_node_creation;
+};
+
+struct msm_camera_i2c_reg_array {
+ unsigned short reg_addr;
+ unsigned short reg_data;
+ unsigned int delay;
+};
+
+struct msm_camera_i2c_reg_setting {
+ struct msm_camera_i2c_reg_array *reg_setting;
+ unsigned short size;
+ enum msm_camera_i2c_reg_addr_type addr_type;
+ enum msm_camera_i2c_data_type data_type;
+ unsigned short delay;
+};
+
+struct msm_camera_csid_vc_cfg {
+ unsigned char cid;
+ unsigned char dt;
+ unsigned char decode_format;
+};
+
+struct msm_camera_csid_lut_params {
+ unsigned char num_cid;
+ struct msm_camera_csid_vc_cfg vc_cfg_a[MAX_CID];
+ struct msm_camera_csid_vc_cfg *vc_cfg[MAX_CID];
+};
+
+struct msm_camera_csid_params {
+ unsigned char lane_cnt;
+ unsigned short lane_assign;
+ unsigned char phy_sel;
+ unsigned int csi_clk;
+ struct msm_camera_csid_lut_params lut_params;
+ unsigned char csi_3p_sel;
+};
+
+struct msm_camera_csid_testmode_parms {
+ unsigned int num_bytes_per_line;
+ unsigned int num_lines;
+ unsigned int h_blanking_count;
+ unsigned int v_blanking_count;
+ unsigned int payload_mode;
+};
+
+struct msm_camera_csiphy_params {
+ unsigned char lane_cnt;
+ unsigned char settle_cnt;
+ unsigned short lane_mask;
+ unsigned char combo_mode;
+ unsigned char csid_core;
+ unsigned int csiphy_clk;
+ unsigned char csi_3phase;
+};
+
+struct msm_camera_i2c_seq_reg_array {
+ unsigned short reg_addr;
+ unsigned char reg_data[I2C_SEQ_REG_DATA_MAX];
+ unsigned short reg_data_size;
+};
+
+struct msm_camera_i2c_seq_reg_setting {
+ struct msm_camera_i2c_seq_reg_array *reg_setting;
+ unsigned short size;
+ enum msm_camera_i2c_reg_addr_type addr_type;
+ unsigned short delay;
+};
+
+struct msm_actuator_reg_params_t {
+ enum msm_actuator_write_type reg_write_type;
+ unsigned int hw_mask;
+ unsigned short reg_addr;
+ unsigned short hw_shift;
+ unsigned short data_shift;
+ unsigned short data_type;
+ unsigned short addr_type;
+ unsigned short reg_data;
+ unsigned short delay;
+};
+
+
+struct damping_params_t {
+ unsigned int damping_step;
+ unsigned int damping_delay;
+ unsigned int hw_params;
+};
+
+struct region_params_t {
+ /* [0] = ForwardDirection Macro boundary
+ * [1] = ReverseDirection Inf boundary
+ */
+ unsigned short step_bound[2];
+ unsigned short code_per_step;
+ /* qvalue for converting float type numbers to integer format */
+ unsigned int qvalue;
+};
+
+struct reg_settings_t {
+ unsigned short reg_addr;
+ enum msm_camera_i2c_reg_addr_type addr_type;
+ unsigned short reg_data;
+ enum msm_camera_i2c_data_type data_type;
+ enum msm_actuator_i2c_operation i2c_operation;
+ unsigned int delay;
+};
+
+struct msm_camera_i2c_reg_setting_array {
+ struct msm_camera_i2c_reg_array reg_setting_a[MAX_I2C_REG_SET];
+ unsigned short size;
+ enum msm_camera_i2c_reg_addr_type addr_type;
+ enum msm_camera_i2c_data_type data_type;
+ unsigned short delay;
+};
+
+#endif
diff --git a/include/uapi/media/msm_fd.h b/include/uapi/media/msm_fd.h
new file mode 100644
index 0000000..eb3bd78
--- /dev/null
+++ b/include/uapi/media/msm_fd.h
@@ -0,0 +1,76 @@
+#ifndef __UAPI_MSM_FD__
+#define __UAPI_MSM_FD__
+
+#include <linux/videodev2.h>
+#include <linux/types.h>
+
+/*
+ * struct msm_fd_event - Structure contain event info.
+ * @buf_index: Buffer index.
+ * @frame_id: Frame id.
+ * @face_cnt: Detected faces.
+ */
+struct msm_fd_event {
+ __u32 buf_index;
+ __u32 frame_id;
+ __u32 face_cnt;
+};
+
+/*
+ * enum msm_fd_pose - Face pose.
+ */
+enum msm_fd_pose {
+ MSM_FD_POSE_FRONT,
+ MSM_FD_POSE_RIGHT_DIAGONAL,
+ MSM_FD_POSE_RIGHT,
+ MSM_FD_POSE_LEFT_DIAGONAL,
+ MSM_FD_POSE_LEFT,
+};
+
+/*
+ * struct msm_fd_face_data - Structure contain detected face data.
+ * @pose: refer to enum msm_fd_pose.
+ * @angle: Face angle
+ * @confidence: Face confidence level.
+ * @reserved: Reserved data for future use.
+ * @face: Face rectangle.
+ */
+struct msm_fd_face_data {
+ __u32 pose;
+ __u32 angle;
+ __u32 confidence;
+ __u32 reserved;
+ struct v4l2_rect face;
+};
+
+/*
+ * struct msm_fd_result - Structure contain detected faces result.
+ * @frame_id: Frame id of requested result.
+ * @face_cnt: Number of result faces, driver can modify this value (to smaller)
+ * @face_data: Pointer to array of face data structures.
+ * Array size should not be smaller then face_cnt.
+ */
+struct msm_fd_result {
+ __u32 frame_id;
+ __u32 face_cnt;
+ struct msm_fd_face_data __user *face_data;
+};
+
+/* MSM FD private ioctl ID */
+#define VIDIOC_MSM_FD_GET_RESULT \
+ _IOWR('V', BASE_VIDIOC_PRIVATE, struct msm_fd_result)
+
+/* MSM FD event ID */
+#define MSM_EVENT_FD (V4L2_EVENT_PRIVATE_START)
+
+/* MSM FD control ID's */
+#define V4L2_CID_FD_SPEED (V4L2_CID_PRIVATE_BASE)
+#define V4L2_CID_FD_FACE_ANGLE (V4L2_CID_PRIVATE_BASE + 1)
+#define V4L2_CID_FD_MIN_FACE_SIZE (V4L2_CID_PRIVATE_BASE + 2)
+#define V4L2_CID_FD_FACE_DIRECTION (V4L2_CID_PRIVATE_BASE + 3)
+#define V4L2_CID_FD_DETECTION_THRESHOLD (V4L2_CID_PRIVATE_BASE + 4)
+#define V4L2_CID_FD_WORK_MEMORY_SIZE (V4L2_CID_PRIVATE_BASE + 5)
+#define V4L2_CID_FD_WORK_MEMORY_FD (V4L2_CID_PRIVATE_BASE + 6)
+
+#endif
+
diff --git a/include/uapi/media/msm_isp.h b/include/uapi/media/msm_isp.h
new file mode 100644
index 0000000..90d87c2
--- /dev/null
+++ b/include/uapi/media/msm_isp.h
@@ -0,0 +1,344 @@
+#ifndef __UAPI_MSM_ISP_H__
+#define __UAPI_MSM_ISP_H__
+
+#define BIT(nr) (1UL << (nr))
+
+/* ISP message IDs */
+#define MSG_ID_RESET_ACK 0
+#define MSG_ID_START_ACK 1
+#define MSG_ID_STOP_ACK 2
+#define MSG_ID_UPDATE_ACK 3
+#define MSG_ID_OUTPUT_P 4
+#define MSG_ID_OUTPUT_T 5
+#define MSG_ID_OUTPUT_S 6
+#define MSG_ID_OUTPUT_V 7
+#define MSG_ID_SNAPSHOT_DONE 8
+#define MSG_ID_STATS_AEC 9
+#define MSG_ID_STATS_AF 10
+#define MSG_ID_STATS_AWB 11
+#define MSG_ID_STATS_RS 12
+#define MSG_ID_STATS_CS 13
+#define MSG_ID_STATS_IHIST 14
+#define MSG_ID_STATS_SKIN 15
+#define MSG_ID_EPOCH1 16
+#define MSG_ID_EPOCH2 17
+#define MSG_ID_SYNC_TIMER0_DONE 18
+#define MSG_ID_SYNC_TIMER1_DONE 19
+#define MSG_ID_SYNC_TIMER2_DONE 20
+#define MSG_ID_ASYNC_TIMER0_DONE 21
+#define MSG_ID_ASYNC_TIMER1_DONE 22
+#define MSG_ID_ASYNC_TIMER2_DONE 23
+#define MSG_ID_ASYNC_TIMER3_DONE 24
+#define MSG_ID_AE_OVERFLOW 25
+#define MSG_ID_AF_OVERFLOW 26
+#define MSG_ID_AWB_OVERFLOW 27
+#define MSG_ID_RS_OVERFLOW 28
+#define MSG_ID_CS_OVERFLOW 29
+#define MSG_ID_IHIST_OVERFLOW 30
+#define MSG_ID_SKIN_OVERFLOW 31
+#define MSG_ID_AXI_ERROR 32
+#define MSG_ID_CAMIF_OVERFLOW 33
+#define MSG_ID_VIOLATION 34
+#define MSG_ID_CAMIF_ERROR 35
+#define MSG_ID_BUS_OVERFLOW 36
+#define MSG_ID_SOF_ACK 37
+#define MSG_ID_STOP_REC_ACK 38
+#define MSG_ID_STATS_AWB_AEC 39
+#define MSG_ID_OUTPUT_PRIMARY 40
+#define MSG_ID_OUTPUT_SECONDARY 41
+#define MSG_ID_STATS_COMPOSITE 42
+#define MSG_ID_OUTPUT_TERTIARY1 43
+#define MSG_ID_STOP_LS_ACK 44
+#define MSG_ID_OUTPUT_TERTIARY2 45
+#define MSG_ID_STATS_BG 46
+#define MSG_ID_STATS_BF 47
+#define MSG_ID_STATS_BHIST 48
+#define MSG_ID_RDI0_UPDATE_ACK 49
+#define MSG_ID_RDI1_UPDATE_ACK 50
+#define MSG_ID_RDI2_UPDATE_ACK 51
+#define MSG_ID_PIX0_UPDATE_ACK 52
+#define MSG_ID_PREV_STOP_ACK 53
+#define MSG_ID_STATS_BE 54
+
+
+/* ISP command IDs */
+#define VFE_CMD_DUMMY_0 0
+#define VFE_CMD_SET_CLK 1
+#define VFE_CMD_RESET 2
+#define VFE_CMD_START 3
+#define VFE_CMD_TEST_GEN_START 4
+#define VFE_CMD_OPERATION_CFG 5
+#define VFE_CMD_AXI_OUT_CFG 6
+#define VFE_CMD_CAMIF_CFG 7
+#define VFE_CMD_AXI_INPUT_CFG 8
+#define VFE_CMD_BLACK_LEVEL_CFG 9
+#define VFE_CMD_MESH_ROLL_OFF_CFG 10
+#define VFE_CMD_DEMUX_CFG 11
+#define VFE_CMD_FOV_CFG 12
+#define VFE_CMD_MAIN_SCALER_CFG 13
+#define VFE_CMD_WB_CFG 14
+#define VFE_CMD_COLOR_COR_CFG 15
+#define VFE_CMD_RGB_G_CFG 16
+#define VFE_CMD_LA_CFG 17
+#define VFE_CMD_CHROMA_EN_CFG 18
+#define VFE_CMD_CHROMA_SUP_CFG 19
+#define VFE_CMD_MCE_CFG 20
+#define VFE_CMD_SK_ENHAN_CFG 21
+#define VFE_CMD_ASF_CFG 22
+#define VFE_CMD_S2Y_CFG 23
+#define VFE_CMD_S2CbCr_CFG 24
+#define VFE_CMD_CHROMA_SUBS_CFG 25
+#define VFE_CMD_OUT_CLAMP_CFG 26
+#define VFE_CMD_FRAME_SKIP_CFG 27
+#define VFE_CMD_DUMMY_1 28
+#define VFE_CMD_DUMMY_2 29
+#define VFE_CMD_DUMMY_3 30
+#define VFE_CMD_UPDATE 31
+#define VFE_CMD_BL_LVL_UPDATE 32
+#define VFE_CMD_DEMUX_UPDATE 33
+#define VFE_CMD_FOV_UPDATE 34
+#define VFE_CMD_MAIN_SCALER_UPDATE 35
+#define VFE_CMD_WB_UPDATE 36
+#define VFE_CMD_COLOR_COR_UPDATE 37
+#define VFE_CMD_RGB_G_UPDATE 38
+#define VFE_CMD_LA_UPDATE 39
+#define VFE_CMD_CHROMA_EN_UPDATE 40
+#define VFE_CMD_CHROMA_SUP_UPDATE 41
+#define VFE_CMD_MCE_UPDATE 42
+#define VFE_CMD_SK_ENHAN_UPDATE 43
+#define VFE_CMD_S2CbCr_UPDATE 44
+#define VFE_CMD_S2Y_UPDATE 45
+#define VFE_CMD_ASF_UPDATE 46
+#define VFE_CMD_FRAME_SKIP_UPDATE 47
+#define VFE_CMD_CAMIF_FRAME_UPDATE 48
+#define VFE_CMD_STATS_AF_UPDATE 49
+#define VFE_CMD_STATS_AE_UPDATE 50
+#define VFE_CMD_STATS_AWB_UPDATE 51
+#define VFE_CMD_STATS_RS_UPDATE 52
+#define VFE_CMD_STATS_CS_UPDATE 53
+#define VFE_CMD_STATS_SKIN_UPDATE 54
+#define VFE_CMD_STATS_IHIST_UPDATE 55
+#define VFE_CMD_DUMMY_4 56
+#define VFE_CMD_EPOCH1_ACK 57
+#define VFE_CMD_EPOCH2_ACK 58
+#define VFE_CMD_START_RECORDING 59
+#define VFE_CMD_STOP_RECORDING 60
+#define VFE_CMD_DUMMY_5 61
+#define VFE_CMD_DUMMY_6 62
+#define VFE_CMD_CAPTURE 63
+#define VFE_CMD_DUMMY_7 64
+#define VFE_CMD_STOP 65
+#define VFE_CMD_GET_HW_VERSION 66
+#define VFE_CMD_GET_FRAME_SKIP_COUNTS 67
+#define VFE_CMD_OUTPUT1_BUFFER_ENQ 68
+#define VFE_CMD_OUTPUT2_BUFFER_ENQ 69
+#define VFE_CMD_OUTPUT3_BUFFER_ENQ 70
+#define VFE_CMD_JPEG_OUT_BUF_ENQ 71
+#define VFE_CMD_RAW_OUT_BUF_ENQ 72
+#define VFE_CMD_RAW_IN_BUF_ENQ 73
+#define VFE_CMD_STATS_AF_ENQ 74
+#define VFE_CMD_STATS_AE_ENQ 75
+#define VFE_CMD_STATS_AWB_ENQ 76
+#define VFE_CMD_STATS_RS_ENQ 77
+#define VFE_CMD_STATS_CS_ENQ 78
+#define VFE_CMD_STATS_SKIN_ENQ 79
+#define VFE_CMD_STATS_IHIST_ENQ 80
+#define VFE_CMD_DUMMY_8 81
+#define VFE_CMD_JPEG_ENC_CFG 82
+#define VFE_CMD_DUMMY_9 83
+#define VFE_CMD_STATS_AF_START 84
+#define VFE_CMD_STATS_AF_STOP 85
+#define VFE_CMD_STATS_AE_START 86
+#define VFE_CMD_STATS_AE_STOP 87
+#define VFE_CMD_STATS_AWB_START 88
+#define VFE_CMD_STATS_AWB_STOP 89
+#define VFE_CMD_STATS_RS_START 90
+#define VFE_CMD_STATS_RS_STOP 91
+#define VFE_CMD_STATS_CS_START 92
+#define VFE_CMD_STATS_CS_STOP 93
+#define VFE_CMD_STATS_SKIN_START 94
+#define VFE_CMD_STATS_SKIN_STOP 95
+#define VFE_CMD_STATS_IHIST_START 96
+#define VFE_CMD_STATS_IHIST_STOP 97
+#define VFE_CMD_DUMMY_10 98
+#define VFE_CMD_SYNC_TIMER_SETTING 99
+#define VFE_CMD_ASYNC_TIMER_SETTING 100
+#define VFE_CMD_LIVESHOT 101
+#define VFE_CMD_LA_SETUP 102
+#define VFE_CMD_LINEARIZATION_CFG 103
+#define VFE_CMD_DEMOSAICV3 104
+#define VFE_CMD_DEMOSAICV3_ABCC_CFG 105
+#define VFE_CMD_DEMOSAICV3_DBCC_CFG 106
+#define VFE_CMD_DEMOSAICV3_DBPC_CFG 107
+#define VFE_CMD_DEMOSAICV3_ABF_CFG 108
+#define VFE_CMD_DEMOSAICV3_ABCC_UPDATE 109
+#define VFE_CMD_DEMOSAICV3_DBCC_UPDATE 110
+#define VFE_CMD_DEMOSAICV3_DBPC_UPDATE 111
+#define VFE_CMD_XBAR_CFG 112
+#define VFE_CMD_MODULE_CFG 113
+#define VFE_CMD_ZSL 114
+#define VFE_CMD_LINEARIZATION_UPDATE 115
+#define VFE_CMD_DEMOSAICV3_ABF_UPDATE 116
+#define VFE_CMD_CLF_CFG 117
+#define VFE_CMD_CLF_LUMA_UPDATE 118
+#define VFE_CMD_CLF_CHROMA_UPDATE 119
+#define VFE_CMD_PCA_ROLL_OFF_CFG 120
+#define VFE_CMD_PCA_ROLL_OFF_UPDATE 121
+#define VFE_CMD_GET_REG_DUMP 122
+#define VFE_CMD_GET_LINEARIZATON_TABLE 123
+#define VFE_CMD_GET_MESH_ROLLOFF_TABLE 124
+#define VFE_CMD_GET_PCA_ROLLOFF_TABLE 125
+#define VFE_CMD_GET_RGB_G_TABLE 126
+#define VFE_CMD_GET_LA_TABLE 127
+#define VFE_CMD_DEMOSAICV3_UPDATE 128
+#define VFE_CMD_ACTIVE_REGION_CFG 129
+#define VFE_CMD_COLOR_PROCESSING_CONFIG 130
+#define VFE_CMD_STATS_WB_AEC_CONFIG 131
+#define VFE_CMD_STATS_WB_AEC_UPDATE 132
+#define VFE_CMD_Y_GAMMA_CONFIG 133
+#define VFE_CMD_SCALE_OUTPUT1_CONFIG 134
+#define VFE_CMD_SCALE_OUTPUT2_CONFIG 135
+#define VFE_CMD_CAPTURE_RAW 136
+#define VFE_CMD_STOP_LIVESHOT 137
+#define VFE_CMD_RECONFIG_VFE 138
+#define VFE_CMD_STATS_REQBUF 139
+#define VFE_CMD_STATS_ENQUEUEBUF 140
+#define VFE_CMD_STATS_FLUSH_BUFQ 141
+#define VFE_CMD_STATS_UNREGBUF 142
+#define VFE_CMD_STATS_BG_START 143
+#define VFE_CMD_STATS_BG_STOP 144
+#define VFE_CMD_STATS_BF_START 145
+#define VFE_CMD_STATS_BF_STOP 146
+#define VFE_CMD_STATS_BHIST_START 147
+#define VFE_CMD_STATS_BHIST_STOP 148
+#define VFE_CMD_RESET_2 149
+#define VFE_CMD_FOV_ENC_CFG 150
+#define VFE_CMD_FOV_VIEW_CFG 151
+#define VFE_CMD_FOV_ENC_UPDATE 152
+#define VFE_CMD_FOV_VIEW_UPDATE 153
+#define VFE_CMD_SCALER_ENC_CFG 154
+#define VFE_CMD_SCALER_VIEW_CFG 155
+#define VFE_CMD_SCALER_ENC_UPDATE 156
+#define VFE_CMD_SCALER_VIEW_UPDATE 157
+#define VFE_CMD_COLORXFORM_ENC_CFG 158
+#define VFE_CMD_COLORXFORM_VIEW_CFG 159
+#define VFE_CMD_COLORXFORM_ENC_UPDATE 160
+#define VFE_CMD_COLORXFORM_VIEW_UPDATE 161
+#define VFE_CMD_TEST_GEN_CFG 162
+#define VFE_CMD_STATS_BE_START 163
+#define VFE_CMD_STATS_BE_STOP 164
+struct msm_isp_cmd {
+ int32_t id;
+ uint16_t length;
+ void *value;
+};
+
+#define VPE_CMD_DUMMY_0 0
+#define VPE_CMD_INIT 1
+#define VPE_CMD_DEINIT 2
+#define VPE_CMD_ENABLE 3
+#define VPE_CMD_DISABLE 4
+#define VPE_CMD_RESET 5
+#define VPE_CMD_FLUSH 6
+#define VPE_CMD_OPERATION_MODE_CFG 7
+#define VPE_CMD_INPUT_PLANE_CFG 8
+#define VPE_CMD_OUTPUT_PLANE_CFG 9
+#define VPE_CMD_INPUT_PLANE_UPDATE 10
+#define VPE_CMD_SCALE_CFG_TYPE 11
+#define VPE_CMD_ZOOM 13
+#define VPE_CMD_MAX 14
+
+#define MSM_PP_CMD_TYPE_NOT_USED 0 /* not used */
+#define MSM_PP_CMD_TYPE_VPE 1 /* VPE cmd */
+#define MSM_PP_CMD_TYPE_MCTL 2 /* MCTL cmd */
+
+#define MCTL_CMD_DUMMY_0 0 /* not used */
+#define MCTL_CMD_GET_FRAME_BUFFER 1 /* reserve a free frame buffer */
+#define MCTL_CMD_PUT_FRAME_BUFFER 2 /* return the free frame buffer */
+#define MCTL_CMD_DIVERT_FRAME_PP_PATH 3 /* divert frame for pp */
+
+/* event typese sending to MCTL PP module */
+#define MCTL_PP_EVENT_NOTUSED 0
+#define MCTL_PP_EVENT_CMD_ACK 1
+
+#define VPE_OPERATION_MODE_CFG_LEN 4
+#define VPE_INPUT_PLANE_CFG_LEN 24
+#define VPE_OUTPUT_PLANE_CFG_LEN 20
+#define VPE_INPUT_PLANE_UPDATE_LEN 12
+#define VPE_SCALER_CONFIG_LEN 260
+#define VPE_DIS_OFFSET_CFG_LEN 12
+
+
+#define CAPTURE_WIDTH 1280
+#define IMEM_Y_SIZE (CAPTURE_WIDTH*16)
+#define IMEM_CBCR_SIZE (CAPTURE_WIDTH*8)
+
+#define IMEM_Y_PING_OFFSET 0x2E000000
+#define IMEM_CBCR_PING_OFFSET (IMEM_Y_PING_OFFSET + IMEM_Y_SIZE)
+
+#define IMEM_Y_PONG_OFFSET (IMEM_CBCR_PING_OFFSET + IMEM_CBCR_SIZE)
+#define IMEM_CBCR_PONG_OFFSET (IMEM_Y_PONG_OFFSET + IMEM_Y_SIZE)
+
+
+struct msm_vpe_op_mode_cfg {
+ uint8_t op_mode_cfg[VPE_OPERATION_MODE_CFG_LEN];
+};
+
+struct msm_vpe_input_plane_cfg {
+ uint8_t input_plane_cfg[VPE_INPUT_PLANE_CFG_LEN];
+};
+
+struct msm_vpe_output_plane_cfg {
+ uint8_t output_plane_cfg[VPE_OUTPUT_PLANE_CFG_LEN];
+};
+
+struct msm_vpe_input_plane_update_cfg {
+ uint8_t input_plane_update_cfg[VPE_INPUT_PLANE_UPDATE_LEN];
+};
+
+struct msm_vpe_scaler_cfg {
+ uint8_t scaler_cfg[VPE_SCALER_CONFIG_LEN];
+};
+
+struct msm_vpe_flush_frame_buffer {
+ uint32_t src_buf_handle;
+ uint32_t dest_buf_handle;
+ int path;
+};
+
+struct msm_mctl_pp_frame_buffer {
+ uint32_t buf_handle;
+ int path;
+};
+struct msm_mctl_pp_divert_pp {
+ int path;
+ int enable;
+};
+struct msm_vpe_clock_rate {
+ uint32_t rate;
+};
+
+#define MSM_MCTL_PP_VPE_FRAME_ACK (1<<0)
+#define MSM_MCTL_PP_VPE_FRAME_TO_APP (1<<1)
+
+#define VFE_OUTPUTS_MAIN_AND_PREVIEW BIT(0)
+#define VFE_OUTPUTS_MAIN_AND_VIDEO BIT(1)
+#define VFE_OUTPUTS_MAIN_AND_THUMB BIT(2)
+#define VFE_OUTPUTS_THUMB_AND_MAIN BIT(3)
+#define VFE_OUTPUTS_PREVIEW_AND_VIDEO BIT(4)
+#define VFE_OUTPUTS_VIDEO_AND_PREVIEW BIT(5)
+#define VFE_OUTPUTS_PREVIEW BIT(6)
+#define VFE_OUTPUTS_VIDEO BIT(7)
+#define VFE_OUTPUTS_RAW BIT(8)
+#define VFE_OUTPUTS_JPEG_AND_THUMB BIT(9)
+#define VFE_OUTPUTS_THUMB_AND_JPEG BIT(10)
+#define VFE_OUTPUTS_RDI0 BIT(11)
+#define VFE_OUTPUTS_RDI1 BIT(12)
+
+struct msm_frame_info {
+ uint32_t inst_handle;
+ uint32_t path;
+};
+
+#endif /*__UAPI_MSM_ISP_H__*/
+
diff --git a/include/uapi/media/msm_jpeg.h b/include/uapi/media/msm_jpeg.h
new file mode 100644
index 0000000..897a180
--- /dev/null
+++ b/include/uapi/media/msm_jpeg.h
@@ -0,0 +1,125 @@
+#ifndef __UAPI_LINUX_MSM_JPEG_H
+#define __UAPI_LINUX_MSM_JPEG_H
+
+#include <linux/types.h>
+#include <linux/ioctl.h>
+
+#define OUTPUT_H2V1 0
+#define OUTPUT_H2V2 1
+#define OUTPUT_BYTE 6
+
+#define MSM_JPEG_IOCTL_MAGIC 'g'
+
+#define MSM_JPEG_IOCTL_GET_HW_VERSION \
+ _IOW(MSM_JPEG_IOCTL_MAGIC, 1, struct msm_jpeg_hw_cmd)
+
+#define MSM_JPEG_IOCTL_RESET \
+ _IOW(MSM_JPEG_IOCTL_MAGIC, 2, struct msm_jpeg_ctrl_cmd)
+
+#define MSM_JPEG_IOCTL_STOP \
+ _IOW(MSM_JPEG_IOCTL_MAGIC, 3, struct msm_jpeg_hw_cmds)
+
+#define MSM_JPEG_IOCTL_START \
+ _IOW(MSM_JPEG_IOCTL_MAGIC, 4, struct msm_jpeg_hw_cmds)
+
+#define MSM_JPEG_IOCTL_INPUT_BUF_ENQUEUE \
+ _IOW(MSM_JPEG_IOCTL_MAGIC, 5, struct msm_jpeg_buf)
+
+#define MSM_JPEG_IOCTL_INPUT_GET \
+ _IOW(MSM_JPEG_IOCTL_MAGIC, 6, struct msm_jpeg_buf)
+
+#define MSM_JPEG_IOCTL_INPUT_GET_UNBLOCK \
+ _IOW(MSM_JPEG_IOCTL_MAGIC, 7, int)
+
+#define MSM_JPEG_IOCTL_OUTPUT_BUF_ENQUEUE \
+ _IOW(MSM_JPEG_IOCTL_MAGIC, 8, struct msm_jpeg_buf)
+
+#define MSM_JPEG_IOCTL_OUTPUT_GET \
+ _IOW(MSM_JPEG_IOCTL_MAGIC, 9, struct msm_jpeg_buf)
+
+#define MSM_JPEG_IOCTL_OUTPUT_GET_UNBLOCK \
+ _IOW(MSM_JPEG_IOCTL_MAGIC, 10, int)
+
+#define MSM_JPEG_IOCTL_EVT_GET \
+ _IOW(MSM_JPEG_IOCTL_MAGIC, 11, struct msm_jpeg_ctrl_cmd)
+
+#define MSM_JPEG_IOCTL_EVT_GET_UNBLOCK \
+ _IOW(MSM_JPEG_IOCTL_MAGIC, 12, int)
+
+#define MSM_JPEG_IOCTL_HW_CMD \
+ _IOW(MSM_JPEG_IOCTL_MAGIC, 13, struct msm_jpeg_hw_cmd)
+
+#define MSM_JPEG_IOCTL_HW_CMDS \
+ _IOW(MSM_JPEG_IOCTL_MAGIC, 14, struct msm_jpeg_hw_cmds)
+
+#define MSM_JPEG_IOCTL_TEST_DUMP_REGION \
+ _IOW(MSM_JPEG_IOCTL_MAGIC, 15, unsigned long)
+
+#define MSM_JPEG_IOCTL_SET_CLK_RATE \
+ _IOW(MSM_JPEG_IOCTL_MAGIC, 16, unsigned int)
+
+#define MSM_JPEG_MODE_REALTIME_ENCODE 0
+#define MSM_JPEG_MODE_OFFLINE_ENCODE 1
+#define MSM_JPEG_MODE_REALTIME_ROTATION 2
+#define MSM_JPEG_MODE_OFFLINE_ROTATION 3
+
+struct msm_jpeg_ctrl_cmd {
+ uint32_t type;
+ uint32_t len;
+ void *value;
+};
+
+#define MSM_JPEG_EVT_RESET 0
+#define MSM_JPEG_EVT_SESSION_DONE 1
+#define MSM_JPEG_EVT_ERR 2
+
+struct msm_jpeg_buf {
+ uint32_t type;
+ int fd;
+
+ void *vaddr;
+
+ uint32_t y_off;
+ uint32_t y_len;
+ uint32_t framedone_len;
+
+ uint32_t cbcr_off;
+ uint32_t cbcr_len;
+
+ uint32_t num_of_mcu_rows;
+ uint32_t offset;
+ uint32_t pln2_off;
+ uint32_t pln2_len;
+};
+
+#define MSM_JPEG_HW_CMD_TYPE_READ 0
+#define MSM_JPEG_HW_CMD_TYPE_WRITE 1
+#define MSM_JPEG_HW_CMD_TYPE_WRITE_OR 2
+#define MSM_JPEG_HW_CMD_TYPE_UWAIT 3
+#define MSM_JPEG_HW_CMD_TYPE_MWAIT 4
+#define MSM_JPEG_HW_CMD_TYPE_MDELAY 5
+#define MSM_JPEG_HW_CMD_TYPE_UDELAY 6
+struct msm_jpeg_hw_cmd {
+
+ uint32_t type:4;
+
+ /* n microseconds of timeout for WAIT */
+ /* n microseconds of time for DELAY */
+ /* repeat n times for READ/WRITE */
+ /* max is 0xFFF, 4095 */
+ uint32_t n:12;
+ uint32_t offset:16;
+ uint32_t mask;
+ union {
+ uint32_t data; /* for single READ/WRITE/WAIT, n = 1 */
+ uint32_t *pdata; /* for multiple READ/WRITE/WAIT, n > 1 */
+ };
+};
+
+struct msm_jpeg_hw_cmds {
+ uint32_t m; /* number of elements in the hw_cmd array */
+ struct msm_jpeg_hw_cmd hw_cmd[1];
+};
+
+#endif
+
diff --git a/include/uapi/media/msm_jpeg_dma.h b/include/uapi/media/msm_jpeg_dma.h
new file mode 100644
index 0000000..a3eab9f
--- /dev/null
+++ b/include/uapi/media/msm_jpeg_dma.h
@@ -0,0 +1,28 @@
+/* Copyright (c) 2015-2016, 2018, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __UAPI_MSM_JPEG_DMA__
+#define __UAPI_MSM_JPEG_DMA__
+
+#include <linux/videodev2.h>
+
+/* msm jpeg dma control ID's */
+#define V4L2_CID_JPEG_DMA_SPEED (V4L2_CID_PRIVATE_BASE)
+#define V4L2_CID_JPEG_DMA_MAX_DOWN_SCALE (V4L2_CID_PRIVATE_BASE + 1)
+
+/* msm_jpeg_dma_buf */
+struct msm_jpeg_dma_buff {
+ int32_t fd;
+ uint32_t offset;
+};
+
+#endif /* __UAPI_MSM_JPEG_DMA__ */
diff --git a/include/uapi/media/msmb_camera.h b/include/uapi/media/msmb_camera.h
new file mode 100644
index 0000000..58aff97
--- /dev/null
+++ b/include/uapi/media/msmb_camera.h
@@ -0,0 +1,230 @@
+#ifndef __UAPI_LINUX_MSMB_CAMERA_H
+#define __UAPI_LINUX_MSMB_CAMERA_H
+
+#include <linux/videodev2.h>
+#include <linux/types.h>
+#include <linux/ioctl.h>
+
+#define MSM_CAM_LOGSYNC_FILE_NAME "logsync"
+#define MSM_CAM_LOGSYNC_FILE_BASEDIR "camera"
+
+#define MSM_CAM_V4L2_IOCTL_NOTIFY \
+ _IOW('V', BASE_VIDIOC_PRIVATE + 30, struct msm_v4l2_event_data)
+
+#define MSM_CAM_V4L2_IOCTL_NOTIFY_META \
+ _IOW('V', BASE_VIDIOC_PRIVATE + 31, struct msm_v4l2_event_data)
+
+#define MSM_CAM_V4L2_IOCTL_CMD_ACK \
+ _IOW('V', BASE_VIDIOC_PRIVATE + 32, struct msm_v4l2_event_data)
+
+#define MSM_CAM_V4L2_IOCTL_NOTIFY_ERROR \
+ _IOW('V', BASE_VIDIOC_PRIVATE + 33, struct msm_v4l2_event_data)
+
+#define MSM_CAM_V4L2_IOCTL_NOTIFY_DEBUG \
+ _IOW('V', BASE_VIDIOC_PRIVATE + 34, struct msm_v4l2_event_data)
+
+#define MSM_CAM_V4L2_IOCTL_DAEMON_DISABLED \
+ _IOW('V', BASE_VIDIOC_PRIVATE + 35, struct msm_v4l2_event_data)
+
+#define QCAMERA_DEVICE_GROUP_ID 1
+#define QCAMERA_VNODE_GROUP_ID 2
+#define MSM_CAMERA_NAME "msm_camera"
+#define MSM_CONFIGURATION_NAME "msm_config"
+
+#define MSM_CAMERA_SUBDEV_CSIPHY 0
+#define MSM_CAMERA_SUBDEV_CSID 1
+#define MSM_CAMERA_SUBDEV_ISPIF 2
+#define MSM_CAMERA_SUBDEV_VFE 3
+#define MSM_CAMERA_SUBDEV_AXI 4
+#define MSM_CAMERA_SUBDEV_VPE 5
+#define MSM_CAMERA_SUBDEV_SENSOR 6
+#define MSM_CAMERA_SUBDEV_ACTUATOR 7
+#define MSM_CAMERA_SUBDEV_EEPROM 8
+#define MSM_CAMERA_SUBDEV_CPP 9
+#define MSM_CAMERA_SUBDEV_CCI 10
+#define MSM_CAMERA_SUBDEV_LED_FLASH 11
+#define MSM_CAMERA_SUBDEV_STROBE_FLASH 12
+#define MSM_CAMERA_SUBDEV_BUF_MNGR 13
+#define MSM_CAMERA_SUBDEV_SENSOR_INIT 14
+#define MSM_CAMERA_SUBDEV_OIS 15
+#define MSM_CAMERA_SUBDEV_FLASH 16
+#define MSM_CAMERA_SUBDEV_IR_LED 17
+#define MSM_CAMERA_SUBDEV_IR_CUT 18
+#define MSM_CAMERA_SUBDEV_EXT 19
+#define MSM_CAMERA_SUBDEV_TOF 20
+#define MSM_CAMERA_SUBDEV_LASER_LED 21
+#define MSM_MAX_CAMERA_SENSORS 5
+
+/* The below macro is defined to put an upper limit on maximum
+ * number of buffer requested per stream. In case of extremely
+ * large value for number of buffer due to data structure corruption
+ * we return error to avoid integer overflow. Group processing
+ * can have max of 9 groups of 8 bufs each. This value may be
+ * configured in future
+ */
+#define MSM_CAMERA_MAX_STREAM_BUF 72
+
+/* Max batch size of processing */
+#define MSM_CAMERA_MAX_USER_BUFF_CNT 16
+
+/* featur base */
+#define MSM_CAMERA_FEATURE_BASE 0x00010000
+#define MSM_CAMERA_FEATURE_SHUTDOWN (MSM_CAMERA_FEATURE_BASE + 1)
+
+#define MSM_CAMERA_STATUS_BASE 0x00020000
+#define MSM_CAMERA_STATUS_FAIL (MSM_CAMERA_STATUS_BASE + 1)
+#define MSM_CAMERA_STATUS_SUCCESS (MSM_CAMERA_STATUS_BASE + 2)
+
+/* event type */
+#define MSM_CAMERA_V4L2_EVENT_TYPE (V4L2_EVENT_PRIVATE_START + 0x00002000)
+
+/* event id */
+#define MSM_CAMERA_EVENT_MIN 0
+#define MSM_CAMERA_NEW_SESSION (MSM_CAMERA_EVENT_MIN + 1)
+#define MSM_CAMERA_DEL_SESSION (MSM_CAMERA_EVENT_MIN + 2)
+#define MSM_CAMERA_SET_PARM (MSM_CAMERA_EVENT_MIN + 3)
+#define MSM_CAMERA_GET_PARM (MSM_CAMERA_EVENT_MIN + 4)
+#define MSM_CAMERA_MAPPING_CFG (MSM_CAMERA_EVENT_MIN + 5)
+#define MSM_CAMERA_MAPPING_SES (MSM_CAMERA_EVENT_MIN + 6)
+#define MSM_CAMERA_MSM_NOTIFY (MSM_CAMERA_EVENT_MIN + 7)
+#define MSM_CAMERA_EVENT_MAX (MSM_CAMERA_EVENT_MIN + 8)
+
+/* data.command */
+#define MSM_CAMERA_PRIV_S_CROP (V4L2_CID_PRIVATE_BASE + 1)
+#define MSM_CAMERA_PRIV_G_CROP (V4L2_CID_PRIVATE_BASE + 2)
+#define MSM_CAMERA_PRIV_G_FMT (V4L2_CID_PRIVATE_BASE + 3)
+#define MSM_CAMERA_PRIV_S_FMT (V4L2_CID_PRIVATE_BASE + 4)
+#define MSM_CAMERA_PRIV_TRY_FMT (V4L2_CID_PRIVATE_BASE + 5)
+#define MSM_CAMERA_PRIV_METADATA (V4L2_CID_PRIVATE_BASE + 6)
+#define MSM_CAMERA_PRIV_QUERY_CAP (V4L2_CID_PRIVATE_BASE + 7)
+#define MSM_CAMERA_PRIV_STREAM_ON (V4L2_CID_PRIVATE_BASE + 8)
+#define MSM_CAMERA_PRIV_STREAM_OFF (V4L2_CID_PRIVATE_BASE + 9)
+#define MSM_CAMERA_PRIV_NEW_STREAM (V4L2_CID_PRIVATE_BASE + 10)
+#define MSM_CAMERA_PRIV_DEL_STREAM (V4L2_CID_PRIVATE_BASE + 11)
+#define MSM_CAMERA_PRIV_SHUTDOWN (V4L2_CID_PRIVATE_BASE + 12)
+#define MSM_CAMERA_PRIV_STREAM_INFO_SYNC \
+ (V4L2_CID_PRIVATE_BASE + 13)
+#define MSM_CAMERA_PRIV_G_SESSION_ID (V4L2_CID_PRIVATE_BASE + 14)
+#define MSM_CAMERA_PRIV_CMD_MAX 20
+
+/* data.status - success */
+#define MSM_CAMERA_CMD_SUCCESS 0x00000001
+#define MSM_CAMERA_BUF_MAP_SUCCESS 0x00000002
+
+/* data.status - error */
+#define MSM_CAMERA_ERR_EVT_BASE 0x00010000
+#define MSM_CAMERA_ERR_CMD_FAIL (MSM_CAMERA_ERR_EVT_BASE + 1)
+#define MSM_CAMERA_ERR_MAPPING (MSM_CAMERA_ERR_EVT_BASE + 2)
+#define MSM_CAMERA_ERR_DEVICE_BUSY (MSM_CAMERA_ERR_EVT_BASE + 3)
+
+/* The msm_v4l2_event_data structure should match the
+ * v4l2_event.u.data field.
+ * should not exceed 16 elements
+ */
+struct msm_v4l2_event_data {
+ /*word 0*/
+ unsigned int command;
+ /*word 1*/
+ unsigned int status;
+ /*word 2*/
+ unsigned int session_id;
+ /*word 3*/
+ unsigned int stream_id;
+ /*word 4*/
+ unsigned int map_op;
+ /*word 5*/
+ unsigned int map_buf_idx;
+ /*word 6*/
+ unsigned int notify;
+ /*word 7*/
+ unsigned int arg_value;
+ /*word 8*/
+ unsigned int ret_value;
+ /*word 9*/
+ unsigned int v4l2_event_type;
+ /*word 10*/
+ unsigned int v4l2_event_id;
+ /*word 11*/
+ unsigned int handle;
+ /*word 12*/
+ unsigned int nop6;
+ /*word 13*/
+ unsigned int nop7;
+ /*word 14*/
+ unsigned int nop8;
+ /*word 15*/
+ unsigned int nop9;
+};
+
+/* map to v4l2_format.fmt.raw_data */
+struct msm_v4l2_format_data {
+ enum v4l2_buf_type type;
+ unsigned int width;
+ unsigned int height;
+ unsigned int pixelformat; /* FOURCC */
+ unsigned char num_planes;
+ unsigned int plane_sizes[VIDEO_MAX_PLANES];
+};
+
+/* MSM Four-character-code (FOURCC) */
+#define msm_v4l2_fourcc(a, b, c, d)\
+ ((__u32)(a) | ((__u32)(b) << 8) | ((__u32)(c) << 16) |\
+ ((__u32)(d) << 24))
+
+/* Composite stats */
+#define MSM_V4L2_PIX_FMT_STATS_COMB v4l2_fourcc('S', 'T', 'C', 'M')
+/* AEC stats */
+#define MSM_V4L2_PIX_FMT_STATS_AE v4l2_fourcc('S', 'T', 'A', 'E')
+/* AF stats */
+#define MSM_V4L2_PIX_FMT_STATS_AF v4l2_fourcc('S', 'T', 'A', 'F')
+/* AWB stats */
+#define MSM_V4L2_PIX_FMT_STATS_AWB v4l2_fourcc('S', 'T', 'W', 'B')
+/* IHIST stats */
+#define MSM_V4L2_PIX_FMT_STATS_IHST v4l2_fourcc('I', 'H', 'S', 'T')
+/* Column count stats */
+#define MSM_V4L2_PIX_FMT_STATS_CS v4l2_fourcc('S', 'T', 'C', 'S')
+/* Row count stats */
+#define MSM_V4L2_PIX_FMT_STATS_RS v4l2_fourcc('S', 'T', 'R', 'S')
+/* Bayer Grid stats */
+#define MSM_V4L2_PIX_FMT_STATS_BG v4l2_fourcc('S', 'T', 'B', 'G')
+/* Bayer focus stats */
+#define MSM_V4L2_PIX_FMT_STATS_BF v4l2_fourcc('S', 'T', 'B', 'F')
+/* Bayer hist stats */
+#define MSM_V4L2_PIX_FMT_STATS_BHST v4l2_fourcc('B', 'H', 'S', 'T')
+
+enum smmu_attach_mode {
+ NON_SECURE_MODE = 0x01,
+ SECURE_MODE = 0x02,
+ MAX_PROTECTION_MODE = 0x03,
+};
+
+struct msm_camera_smmu_attach_type {
+ enum smmu_attach_mode attach;
+};
+
+struct msm_camera_user_buf_cont_t {
+ unsigned int buf_cnt;
+ unsigned int buf_idx[MSM_CAMERA_MAX_USER_BUFF_CNT];
+};
+
+struct msm_camera_return_buf {
+ __u32 index;
+ __u32 reserved;
+};
+
+#define MSM_CAMERA_PRIV_IOCTL_ID_BASE 0
+#define MSM_CAMERA_PRIV_IOCTL_ID_RETURN_BUF 1
+
+struct msm_camera_private_ioctl_arg {
+ __u32 id;
+ __u32 size;
+ __u32 result;
+ __u32 reserved;
+ __u64 ioctl_ptr;
+};
+
+#define VIDIOC_MSM_CAMERA_PRIVATE_IOCTL_CMD \
+ _IOWR('V', BASE_VIDIOC_PRIVATE, struct msm_camera_private_ioctl_arg)
+
+#endif
+
diff --git a/include/uapi/media/msmb_generic_buf_mgr.h b/include/uapi/media/msmb_generic_buf_mgr.h
new file mode 100644
index 0000000..2961cae
--- /dev/null
+++ b/include/uapi/media/msmb_generic_buf_mgr.h
@@ -0,0 +1,66 @@
+#ifndef __UAPI_MEDIA_MSMB_GENERIC_BUF_MGR_H__
+#define __UAPI_MEDIA_MSMB_GENERIC_BUF_MGR_H__
+
+#include <media/msmb_camera.h>
+
+enum msm_camera_buf_mngr_cmd {
+ MSM_CAMERA_BUF_MNGR_CONT_MAP,
+ MSM_CAMERA_BUF_MNGR_CONT_UNMAP,
+ MSM_CAMERA_BUF_MNGR_CONT_MAX,
+};
+
+enum msm_camera_buf_mngr_buf_type {
+ MSM_CAMERA_BUF_MNGR_BUF_PLANAR,
+ MSM_CAMERA_BUF_MNGR_BUF_USER,
+ MSM_CAMERA_BUF_MNGR_BUF_INVALID,
+};
+
+struct msm_buf_mngr_info {
+ uint32_t session_id;
+ uint32_t stream_id;
+ uint32_t frame_id;
+ struct timeval timestamp;
+ uint32_t index;
+ uint32_t reserved;
+ enum msm_camera_buf_mngr_buf_type type;
+ struct msm_camera_user_buf_cont_t user_buf;
+};
+
+struct msm_buf_mngr_main_cont_info {
+ uint32_t session_id;
+ uint32_t stream_id;
+ enum msm_camera_buf_mngr_cmd cmd;
+ uint32_t cnt;
+ int32_t cont_fd;
+};
+
+#define MSM_CAMERA_BUF_MNGR_IOCTL_ID_BASE 0
+#define MSM_CAMERA_BUF_MNGR_IOCTL_ID_GET_BUF_BY_IDX 1
+
+#define VIDIOC_MSM_BUF_MNGR_GET_BUF \
+ _IOWR('V', BASE_VIDIOC_PRIVATE + 33, struct msm_buf_mngr_info)
+
+#define VIDIOC_MSM_BUF_MNGR_PUT_BUF \
+ _IOWR('V', BASE_VIDIOC_PRIVATE + 34, struct msm_buf_mngr_info)
+
+#define VIDIOC_MSM_BUF_MNGR_BUF_DONE \
+ _IOWR('V', BASE_VIDIOC_PRIVATE + 35, struct msm_buf_mngr_info)
+
+#define VIDIOC_MSM_BUF_MNGR_CONT_CMD \
+ _IOWR('V', BASE_VIDIOC_PRIVATE + 36, struct msm_buf_mngr_main_cont_info)
+
+#define VIDIOC_MSM_BUF_MNGR_INIT \
+ _IOWR('V', BASE_VIDIOC_PRIVATE + 37, struct msm_buf_mngr_info)
+
+#define VIDIOC_MSM_BUF_MNGR_DEINIT \
+ _IOWR('V', BASE_VIDIOC_PRIVATE + 38, struct msm_buf_mngr_info)
+
+#define VIDIOC_MSM_BUF_MNGR_FLUSH \
+ _IOWR('V', BASE_VIDIOC_PRIVATE + 39, struct msm_buf_mngr_info)
+
+#define VIDIOC_MSM_BUF_MNGR_IOCTL_CMD \
+ _IOWR('V', BASE_VIDIOC_PRIVATE + 40, \
+ struct msm_camera_private_ioctl_arg)
+
+#endif
+
diff --git a/include/uapi/media/msmb_isp.h b/include/uapi/media/msmb_isp.h
new file mode 100644
index 0000000..2b10748
--- /dev/null
+++ b/include/uapi/media/msmb_isp.h
@@ -0,0 +1,1042 @@
+#ifndef __UAPI_MSMB_ISP__
+#define __UAPI_MSMB_ISP__
+
+#include <linux/videodev2.h>
+#include <media/msmb_camera.h>
+
+#define MAX_PLANES_PER_STREAM 3
+#define MAX_NUM_STREAM 7
+
+#define ISP_VERSION_48 48
+#define ISP_VERSION_47 47
+#define ISP_VERSION_46 46
+#define ISP_VERSION_44 44
+#define ISP_VERSION_40 40
+#define ISP_VERSION_32 32
+#define ISP_NATIVE_BUF_BIT (0x10000 << 0)
+#define ISP0_BIT (0x10000 << 1)
+#define ISP1_BIT (0x10000 << 2)
+#define ISP_META_CHANNEL_BIT (0x10000 << 3)
+#define ISP_SCRATCH_BUF_BIT (0x10000 << 4)
+#define ISP_OFFLINE_STATS_BIT (0x10000 << 5)
+#define ISP_SVHDR_IN_BIT (0x10000 << 6) /* RDI hw stream for SVHDR */
+#define ISP_SVHDR_OUT_BIT (0x10000 << 7) /* SVHDR output bufq stream*/
+
+#define ISP_STATS_STREAM_BIT 0x80000000
+
+#define VFE_HW_LIMIT 1
+
+struct msm_vfe_cfg_cmd_list;
+
+enum ISP_START_PIXEL_PATTERN {
+ ISP_BAYER_RGRGRG,
+ ISP_BAYER_GRGRGR,
+ ISP_BAYER_BGBGBG,
+ ISP_BAYER_GBGBGB,
+ ISP_YUV_YCbYCr,
+ ISP_YUV_YCrYCb,
+ ISP_YUV_CbYCrY,
+ ISP_YUV_CrYCbY,
+ ISP_PIX_PATTERN_MAX
+};
+
+enum msm_vfe_plane_fmt {
+ Y_PLANE,
+ CB_PLANE,
+ CR_PLANE,
+ CRCB_PLANE,
+ CBCR_PLANE,
+ VFE_PLANE_FMT_MAX
+};
+
+enum msm_vfe_input_src {
+ VFE_PIX_0,
+ VFE_RAW_0,
+ VFE_RAW_1,
+ VFE_RAW_2,
+ VFE_SRC_MAX,
+};
+
+enum msm_vfe_axi_stream_src {
+ PIX_ENCODER,
+ PIX_VIEWFINDER,
+ PIX_VIDEO,
+ CAMIF_RAW,
+ IDEAL_RAW,
+ RDI_INTF_0,
+ RDI_INTF_1,
+ RDI_INTF_2,
+ VFE_AXI_SRC_MAX
+};
+
+enum msm_vfe_frame_skip_pattern {
+ NO_SKIP,
+ EVERY_2FRAME,
+ EVERY_3FRAME,
+ EVERY_4FRAME,
+ EVERY_5FRAME,
+ EVERY_6FRAME,
+ EVERY_7FRAME,
+ EVERY_8FRAME,
+ EVERY_16FRAME,
+ EVERY_32FRAME,
+ SKIP_ALL,
+ SKIP_RANGE,
+ MAX_SKIP,
+};
+
+/*
+ * Define an unused period. When this period is set it means that the stream is
+ * stopped(i.e the pattern is 0). We don't track the current pattern, just the
+ * period defines what the pattern is, if period is this then pattern is 0 else
+ * pattern is 1
+ */
+#define MSM_VFE_STREAM_STOP_PERIOD 15
+
+enum msm_isp_stats_type {
+ MSM_ISP_STATS_AEC, /* legacy based AEC */
+ MSM_ISP_STATS_AF, /* legacy based AF */
+ MSM_ISP_STATS_AWB, /* legacy based AWB */
+ MSM_ISP_STATS_RS, /* legacy based RS */
+ MSM_ISP_STATS_CS, /* legacy based CS */
+ MSM_ISP_STATS_IHIST, /* legacy based HIST */
+ MSM_ISP_STATS_SKIN, /* legacy based SKIN */
+ MSM_ISP_STATS_BG, /* Bayer Grids */
+ MSM_ISP_STATS_BF, /* Bayer Focus */
+ MSM_ISP_STATS_BE, /* Bayer Exposure*/
+ MSM_ISP_STATS_BHIST, /* Bayer Hist */
+ MSM_ISP_STATS_BF_SCALE, /* Bayer Focus scale */
+ MSM_ISP_STATS_HDR_BE, /* HDR Bayer Exposure */
+ MSM_ISP_STATS_HDR_BHIST, /* HDR Bayer Hist */
+ MSM_ISP_STATS_AEC_BG, /* AEC BG */
+ MSM_ISP_STATS_MAX /* MAX */
+};
+
+/*
+ * @stats_type_mask: Stats type mask (enum msm_isp_stats_type).
+ * @stream_src_mask: Stream src mask (enum msm_vfe_axi_stream_src)
+ * @skip_mode: skip pattern, if skip mode is range only then min/max is used
+ * @min_frame_id: minimum frame id (valid only if skip_mode = RANGE)
+ * @max_frame_id: maximum frame id (valid only if skip_mode = RANGE)
+ */
+struct msm_isp_sw_framskip {
+ uint32_t stats_type_mask;
+ uint32_t stream_src_mask;
+ enum msm_vfe_frame_skip_pattern skip_mode;
+ uint32_t min_frame_id;
+ uint32_t max_frame_id;
+};
+
+enum msm_vfe_testgen_color_pattern {
+ COLOR_BAR_8_COLOR,
+ UNICOLOR_WHITE,
+ UNICOLOR_YELLOW,
+ UNICOLOR_CYAN,
+ UNICOLOR_GREEN,
+ UNICOLOR_MAGENTA,
+ UNICOLOR_RED,
+ UNICOLOR_BLUE,
+ UNICOLOR_BLACK,
+ MAX_COLOR,
+};
+
+enum msm_vfe_camif_input {
+ CAMIF_DISABLED,
+ CAMIF_PAD_REG_INPUT,
+ CAMIF_MIDDI_INPUT,
+ CAMIF_MIPI_INPUT,
+};
+
+struct msm_vfe_fetch_engine_cfg {
+ uint32_t input_format;
+ uint32_t buf_width;
+ uint32_t buf_height;
+ uint32_t fetch_width;
+ uint32_t fetch_height;
+ uint32_t x_offset;
+ uint32_t y_offset;
+ uint32_t buf_stride;
+};
+
+enum msm_vfe_camif_output_format {
+ CAMIF_QCOM_RAW,
+ CAMIF_MIPI_RAW,
+ CAMIF_PLAIN_8,
+ CAMIF_PLAIN_16,
+ CAMIF_MAX_FORMAT,
+};
+
+/*
+ * Camif output general configuration
+ */
+struct msm_vfe_camif_subsample_cfg {
+ uint32_t irq_subsample_period;
+ uint32_t irq_subsample_pattern;
+ uint32_t sof_counter_step;
+ uint32_t pixel_skip;
+ uint32_t line_skip;
+ uint32_t first_line;
+ uint32_t last_line;
+ uint32_t first_pixel;
+ uint32_t last_pixel;
+ enum msm_vfe_camif_output_format output_format;
+};
+
+/*
+ * Camif frame and window configuration
+ */
+struct msm_vfe_camif_cfg {
+ uint32_t lines_per_frame;
+ uint32_t pixels_per_line;
+ uint32_t first_pixel;
+ uint32_t last_pixel;
+ uint32_t first_line;
+ uint32_t last_line;
+ uint32_t epoch_line0;
+ uint32_t epoch_line1;
+ uint32_t is_split;
+ enum msm_vfe_camif_input camif_input;
+ struct msm_vfe_camif_subsample_cfg subsample_cfg;
+};
+
+struct msm_vfe_testgen_cfg {
+ uint32_t lines_per_frame;
+ uint32_t pixels_per_line;
+ uint32_t v_blank;
+ uint32_t h_blank;
+ enum ISP_START_PIXEL_PATTERN pixel_bayer_pattern;
+ uint32_t rotate_period;
+ enum msm_vfe_testgen_color_pattern color_bar_pattern;
+ uint32_t burst_num_frame;
+};
+
+enum msm_vfe_inputmux {
+ CAMIF,
+ TESTGEN,
+ EXTERNAL_READ,
+};
+
+enum msm_vfe_stats_composite_group {
+ STATS_COMPOSITE_GRP_NONE,
+ STATS_COMPOSITE_GRP_1,
+ STATS_COMPOSITE_GRP_2,
+ STATS_COMPOSITE_GRP_MAX,
+};
+
+enum msm_vfe_hvx_streaming_cmd {
+ HVX_DISABLE,
+ HVX_ONE_WAY,
+ HVX_ROUND_TRIP
+};
+
+struct msm_vfe_pix_cfg {
+ struct msm_vfe_camif_cfg camif_cfg;
+ struct msm_vfe_testgen_cfg testgen_cfg;
+ struct msm_vfe_fetch_engine_cfg fetch_engine_cfg;
+ enum msm_vfe_inputmux input_mux;
+ enum ISP_START_PIXEL_PATTERN pixel_pattern;
+ uint32_t input_format;
+ enum msm_vfe_hvx_streaming_cmd hvx_cmd;
+ uint32_t is_split;
+};
+
+struct msm_vfe_rdi_cfg {
+ uint8_t cid;
+ uint8_t frame_based;
+};
+
+struct msm_vfe_input_cfg {
+ union {
+ struct msm_vfe_pix_cfg pix_cfg;
+ struct msm_vfe_rdi_cfg rdi_cfg;
+ } d;
+ enum msm_vfe_input_src input_src;
+ uint32_t input_pix_clk;
+};
+
+struct msm_vfe_fetch_eng_start {
+ uint32_t session_id;
+ uint32_t stream_id;
+ uint32_t buf_idx;
+ uint8_t offline_mode;
+ uint32_t fd;
+ uint32_t buf_addr;
+ uint32_t frame_id;
+};
+
+enum msm_vfe_fetch_eng_pass {
+ OFFLINE_FIRST_PASS,
+ OFFLINE_SECOND_PASS,
+ OFFLINE_MAX_PASS,
+};
+
+struct msm_vfe_fetch_eng_multi_pass_start {
+ uint32_t session_id;
+ uint32_t stream_id;
+ uint32_t buf_idx;
+ uint8_t offline_mode;
+ uint32_t fd;
+ uint32_t buf_addr;
+ uint32_t frame_id;
+ uint32_t output_buf_idx;
+ uint32_t input_buf_offset;
+ enum msm_vfe_fetch_eng_pass offline_pass;
+ uint32_t output_stream_id;
+};
+
+struct msm_vfe_axi_plane_cfg {
+ uint32_t output_width; /*Include padding*/
+ uint32_t output_height;
+ uint32_t output_stride;
+ uint32_t output_scan_lines;
+ uint32_t output_plane_format; /*Y/Cb/Cr/CbCr*/
+ uint32_t plane_addr_offset;
+ uint8_t csid_src; /*RDI 0-2*/
+ uint8_t rdi_cid;/*CID 1-16*/
+};
+
+enum msm_stream_rdi_input_type {
+ MSM_CAMERA_RDI_MIN,
+ MSM_CAMERA_RDI_PDAF,
+ MSM_CAMERA_RDI_MAX,
+};
+
+struct msm_vfe_axi_stream_request_cmd {
+ uint32_t session_id;
+ uint32_t stream_id;
+ uint32_t vt_enable;
+ uint32_t output_format;/*Planar/RAW/Misc*/
+ enum msm_vfe_axi_stream_src stream_src; /*CAMIF/IDEAL/RDIs*/
+ struct msm_vfe_axi_plane_cfg plane_cfg[MAX_PLANES_PER_STREAM];
+
+ uint32_t burst_count;
+ uint32_t hfr_mode;
+ uint8_t frame_base;
+
+ uint32_t init_frame_drop; /*MAX 31 Frames*/
+ enum msm_vfe_frame_skip_pattern frame_skip_pattern;
+ uint8_t buf_divert; /* if TRUE no vb2 buf done. */
+ /*Return values*/
+ uint32_t axi_stream_handle;
+ uint32_t controllable_output;
+ uint32_t burst_len;
+ /* Flag indicating memory input stream */
+ enum msm_stream_rdi_input_type rdi_input_type;
+};
+
+struct msm_vfe_axi_stream_release_cmd {
+ uint32_t stream_handle;
+};
+
+enum msm_vfe_axi_stream_cmd {
+ STOP_STREAM,
+ START_STREAM,
+ STOP_IMMEDIATELY,
+};
+
+struct msm_vfe_axi_stream_cfg_cmd {
+ uint8_t num_streams;
+ uint32_t stream_handle[VFE_AXI_SRC_MAX];
+ enum msm_vfe_axi_stream_cmd cmd;
+ uint8_t sync_frame_id_src;
+};
+
+enum msm_vfe_axi_stream_update_type {
+ ENABLE_STREAM_BUF_DIVERT,
+ DISABLE_STREAM_BUF_DIVERT,
+ UPDATE_STREAM_FRAMEDROP_PATTERN,
+ UPDATE_STREAM_STATS_FRAMEDROP_PATTERN,
+ UPDATE_STREAM_AXI_CONFIG,
+ UPDATE_STREAM_REQUEST_FRAMES,
+ UPDATE_STREAM_ADD_BUFQ,
+ UPDATE_STREAM_REMOVE_BUFQ,
+ UPDATE_STREAM_SW_FRAME_DROP,
+ UPDATE_STREAM_REQUEST_FRAMES_VER2,
+ UPDATE_STREAM_OFFLINE_AXI_CONFIG,
+};
+#define UPDATE_STREAM_REQUEST_FRAMES_VER2 UPDATE_STREAM_REQUEST_FRAMES_VER2
+
+enum msm_vfe_iommu_type {
+ IOMMU_ATTACH,
+ IOMMU_DETACH,
+};
+
+enum msm_vfe_buff_queue_id {
+ VFE_BUF_QUEUE_DEFAULT,
+ VFE_BUF_QUEUE_SHARED,
+ VFE_BUF_QUEUE_MAX,
+};
+
+struct msm_vfe_axi_stream_cfg_update_info {
+ uint32_t stream_handle;
+ uint32_t output_format;
+ uint32_t user_stream_id;
+ uint32_t frame_id;
+ enum msm_vfe_frame_skip_pattern skip_pattern;
+ struct msm_vfe_axi_plane_cfg plane_cfg[MAX_PLANES_PER_STREAM];
+ struct msm_isp_sw_framskip sw_skip_info;
+};
+
+struct msm_vfe_axi_stream_cfg_update_info_req_frm {
+ uint32_t stream_handle;
+ uint32_t user_stream_id;
+ uint32_t frame_id;
+ uint32_t buf_index;
+};
+
+struct msm_vfe_axi_halt_cmd {
+ uint32_t stop_camif;
+ uint32_t overflow_detected;
+ uint32_t blocking_halt;
+};
+
+struct msm_vfe_axi_reset_cmd {
+ uint32_t blocking;
+ uint32_t frame_id;
+};
+
+struct msm_vfe_axi_restart_cmd {
+ uint32_t enable_camif;
+};
+
+struct msm_vfe_axi_stream_update_cmd {
+ uint32_t num_streams;
+ enum msm_vfe_axi_stream_update_type update_type;
+ /*
+ * For backward compatibility, ensure 1st member of any struct
+ * in union below is uint32_t stream_handle.
+ */
+ union {
+ struct msm_vfe_axi_stream_cfg_update_info
+ update_info[MSM_ISP_STATS_MAX];
+ struct msm_vfe_axi_stream_cfg_update_info_req_frm req_frm_ver2;
+ };
+};
+
+struct msm_vfe_smmu_attach_cmd {
+ uint32_t security_mode;
+ uint32_t iommu_attach_mode;
+};
+
+struct msm_vfe_stats_stream_request_cmd {
+ uint32_t session_id;
+ uint32_t stream_id;
+ enum msm_isp_stats_type stats_type;
+ uint32_t composite_flag;
+ uint32_t framedrop_pattern;
+ uint32_t init_frame_drop; /*MAX 31 Frames*/
+ uint32_t irq_subsample_pattern;
+ uint32_t buffer_offset;
+ uint32_t stream_handle;
+};
+
+struct msm_vfe_stats_stream_release_cmd {
+ uint32_t stream_handle;
+};
+struct msm_vfe_stats_stream_cfg_cmd {
+ uint8_t num_streams;
+ uint32_t stream_handle[MSM_ISP_STATS_MAX];
+ uint8_t enable;
+ uint32_t stats_burst_len;
+};
+
+enum msm_vfe_reg_cfg_type {
+ VFE_WRITE,
+ VFE_WRITE_MB,
+ VFE_READ,
+ VFE_CFG_MASK,
+ VFE_WRITE_DMI_16BIT,
+ VFE_WRITE_DMI_32BIT,
+ VFE_WRITE_DMI_64BIT,
+ VFE_READ_DMI_16BIT,
+ VFE_READ_DMI_32BIT,
+ VFE_READ_DMI_64BIT,
+ GET_MAX_CLK_RATE,
+ GET_CLK_RATES,
+ GET_ISP_ID,
+ VFE_HW_UPDATE_LOCK,
+ VFE_HW_UPDATE_UNLOCK,
+ SET_WM_UB_SIZE,
+ SET_UB_POLICY,
+ GET_VFE_HW_LIMIT,
+};
+
+struct msm_vfe_cfg_cmd2 {
+ uint16_t num_cfg;
+ uint16_t cmd_len;
+ void __user *cfg_data;
+ void __user *cfg_cmd;
+};
+
+struct msm_vfe_cfg_cmd_list {
+ struct msm_vfe_cfg_cmd2 cfg_cmd;
+ struct msm_vfe_cfg_cmd_list *next;
+ uint32_t next_size;
+};
+
+struct msm_vfe_reg_rw_info {
+ uint32_t reg_offset;
+ uint32_t cmd_data_offset;
+ uint32_t len;
+};
+
+struct msm_vfe_reg_mask_info {
+ uint32_t reg_offset;
+ uint32_t mask;
+ uint32_t val;
+};
+
+struct msm_vfe_reg_dmi_info {
+ uint32_t hi_tbl_offset; /*Optional*/
+ uint32_t lo_tbl_offset; /*Required*/
+ uint32_t len;
+};
+
+struct msm_vfe_reg_cfg_cmd {
+ union {
+ struct msm_vfe_reg_rw_info rw_info;
+ struct msm_vfe_reg_mask_info mask_info;
+ struct msm_vfe_reg_dmi_info dmi_info;
+ } u;
+
+ enum msm_vfe_reg_cfg_type cmd_type;
+};
+
+enum vfe_sd_type {
+ VFE_SD_0 = 0,
+ VFE_SD_1,
+ VFE_SD_COMMON,
+ VFE_SD_MAX,
+};
+
+/* When you change the value below, check for the sof event_data size.
+ * V4l2 limits payload to 64 bytes
+ */
+#define MS_NUM_SLAVE_MAX 1
+
+/* Usecases when 2 HW need to be related or synced */
+enum msm_vfe_dual_hw_type {
+ DUAL_NONE = 0,
+ DUAL_HW_VFE_SPLIT = 1,
+ DUAL_HW_MASTER_SLAVE = 2,
+};
+
+/* Type for 2 INTF when used in Master-Slave mode */
+enum msm_vfe_dual_hw_ms_type {
+ MS_TYPE_NONE,
+ MS_TYPE_MASTER,
+ MS_TYPE_SLAVE,
+};
+
+struct msm_isp_set_dual_hw_ms_cmd {
+ uint8_t num_src;
+ /* Each session can be only one type but multiple intf if YUV cam */
+ enum msm_vfe_dual_hw_ms_type dual_hw_ms_type;
+ /* Primary intf is mostly associated with preview.
+ * This primary intf SOF frame_id and timestamp is tracked
+ * and used to calculate delta
+ */
+ enum msm_vfe_input_src primary_intf;
+ /* input_src array indicates other input INTF that may be Master/Slave.
+ * For these additional intf, frame_id and timestamp are not saved.
+ * However, if these are slaves then they will still get their
+ * frame_id from Master
+ */
+ enum msm_vfe_input_src input_src[VFE_SRC_MAX];
+ uint32_t sof_delta_threshold; /* In milliseconds. Sent for Master */
+};
+
+enum msm_isp_buf_type {
+ ISP_PRIVATE_BUF,
+ ISP_SHARE_BUF,
+ MAX_ISP_BUF_TYPE,
+};
+
+struct msm_isp_unmap_buf_req {
+ uint32_t fd;
+};
+
+struct msm_isp_buf_request {
+ uint32_t session_id;
+ uint32_t stream_id;
+ uint8_t num_buf;
+ uint32_t handle;
+ enum msm_isp_buf_type buf_type;
+};
+
+struct msm_isp_buf_request_ver2 {
+ uint32_t session_id;
+ uint32_t stream_id;
+ uint8_t num_buf;
+ uint32_t handle;
+ enum msm_isp_buf_type buf_type;
+ enum smmu_attach_mode security_mode;
+ uint32_t reserved[4];
+};
+
+struct msm_isp_qbuf_plane {
+ uint32_t addr;
+ uint32_t offset;
+ uint32_t length;
+};
+
+struct msm_isp_qbuf_buffer {
+ struct msm_isp_qbuf_plane planes[MAX_PLANES_PER_STREAM];
+ uint32_t num_planes;
+};
+
+struct msm_isp_qbuf_info {
+ uint32_t handle;
+ int32_t buf_idx;
+ /*Only used for prepare buffer*/
+ struct msm_isp_qbuf_buffer buffer;
+ /*Only used for diverted buffer*/
+ uint32_t dirty_buf;
+};
+
+struct msm_isp_clk_rates {
+ uint32_t svs_rate;
+ uint32_t nominal_rate;
+ uint32_t high_rate;
+};
+
+struct msm_vfe_axi_src_state {
+ enum msm_vfe_input_src input_src;
+ uint32_t src_active;
+ uint32_t src_frame_id;
+};
+
+enum msm_isp_event_mask_index {
+ ISP_EVENT_MASK_INDEX_STATS_NOTIFY = 0,
+ ISP_EVENT_MASK_INDEX_ERROR = 1,
+ ISP_EVENT_MASK_INDEX_IOMMU_P_FAULT = 2,
+ ISP_EVENT_MASK_INDEX_STREAM_UPDATE_DONE = 3,
+ ISP_EVENT_MASK_INDEX_REG_UPDATE = 4,
+ ISP_EVENT_MASK_INDEX_SOF = 5,
+ ISP_EVENT_MASK_INDEX_BUF_DIVERT = 6,
+ ISP_EVENT_MASK_INDEX_COMP_STATS_NOTIFY = 7,
+ ISP_EVENT_MASK_INDEX_MASK_FE_READ_DONE = 8,
+ ISP_EVENT_MASK_INDEX_BUF_DONE = 9,
+ ISP_EVENT_MASK_INDEX_REG_UPDATE_MISSING = 10,
+ ISP_EVENT_MASK_INDEX_PING_PONG_MISMATCH = 11,
+ ISP_EVENT_MASK_INDEX_BUF_FATAL_ERROR = 12,
+};
+
+
+#define ISP_EVENT_SUBS_MASK_NONE 0
+
+#define ISP_EVENT_SUBS_MASK_STATS_NOTIFY \
+ (1 << ISP_EVENT_MASK_INDEX_STATS_NOTIFY)
+
+#define ISP_EVENT_SUBS_MASK_ERROR \
+ (1 << ISP_EVENT_MASK_INDEX_ERROR)
+
+#define ISP_EVENT_SUBS_MASK_IOMMU_P_FAULT \
+ (1 << ISP_EVENT_MASK_INDEX_IOMMU_P_FAULT)
+
+#define ISP_EVENT_SUBS_MASK_STREAM_UPDATE_DONE \
+ (1 << ISP_EVENT_MASK_INDEX_STREAM_UPDATE_DONE)
+
+#define ISP_EVENT_SUBS_MASK_REG_UPDATE \
+ (1 << ISP_EVENT_MASK_INDEX_REG_UPDATE)
+
+#define ISP_EVENT_SUBS_MASK_SOF \
+ (1 << ISP_EVENT_MASK_INDEX_SOF)
+
+#define ISP_EVENT_SUBS_MASK_BUF_DIVERT \
+ (1 << ISP_EVENT_MASK_INDEX_BUF_DIVERT)
+
+#define ISP_EVENT_SUBS_MASK_COMP_STATS_NOTIFY \
+ (1 << ISP_EVENT_MASK_INDEX_COMP_STATS_NOTIFY)
+
+#define ISP_EVENT_SUBS_MASK_FE_READ_DONE \
+ (1 << ISP_EVENT_MASK_INDEX_MASK_FE_READ_DONE)
+
+#define ISP_EVENT_SUBS_MASK_BUF_DONE \
+ (1 << ISP_EVENT_MASK_INDEX_BUF_DONE)
+
+#define ISP_EVENT_SUBS_MASK_REG_UPDATE_MISSING \
+ (1 << ISP_EVENT_MASK_INDEX_REG_UPDATE_MISSING)
+
+#define ISP_EVENT_SUBS_MASK_PING_PONG_MISMATCH \
+ (1 << ISP_EVENT_MASK_INDEX_PING_PONG_MISMATCH)
+
+#define ISP_EVENT_SUBS_MASK_BUF_FATAL_ERROR \
+ (1 << ISP_EVENT_MASK_INDEX_BUF_FATAL_ERROR)
+
+enum msm_isp_event_idx {
+ ISP_REG_UPDATE = 0,
+ ISP_EPOCH_0 = 1,
+ ISP_EPOCH_1 = 2,
+ ISP_START_ACK = 3,
+ ISP_STOP_ACK = 4,
+ ISP_IRQ_VIOLATION = 5,
+ ISP_STATS_OVERFLOW = 6,
+ ISP_BUF_DONE = 7,
+ ISP_FE_RD_DONE = 8,
+ ISP_IOMMU_P_FAULT = 9,
+ ISP_ERROR = 10,
+ ISP_HW_FATAL_ERROR = 11,
+ ISP_PING_PONG_MISMATCH = 12,
+ ISP_REG_UPDATE_MISSING = 13,
+ ISP_BUF_FATAL_ERROR = 14,
+ ISP_EVENT_MAX = 15
+};
+
+#define ISP_EVENT_OFFSET 8
+#define ISP_EVENT_BASE (V4L2_EVENT_PRIVATE_START)
+#define ISP_BUF_EVENT_BASE (ISP_EVENT_BASE + (1 << ISP_EVENT_OFFSET))
+#define ISP_STATS_EVENT_BASE (ISP_EVENT_BASE + (2 << ISP_EVENT_OFFSET))
+#define ISP_CAMIF_EVENT_BASE (ISP_EVENT_BASE + (3 << ISP_EVENT_OFFSET))
+#define ISP_STREAM_EVENT_BASE (ISP_EVENT_BASE + (4 << ISP_EVENT_OFFSET))
+#define ISP_EVENT_REG_UPDATE (ISP_EVENT_BASE + ISP_REG_UPDATE)
+#define ISP_EVENT_EPOCH_0 (ISP_EVENT_BASE + ISP_EPOCH_0)
+#define ISP_EVENT_EPOCH_1 (ISP_EVENT_BASE + ISP_EPOCH_1)
+#define ISP_EVENT_START_ACK (ISP_EVENT_BASE + ISP_START_ACK)
+#define ISP_EVENT_STOP_ACK (ISP_EVENT_BASE + ISP_STOP_ACK)
+#define ISP_EVENT_IRQ_VIOLATION (ISP_EVENT_BASE + ISP_IRQ_VIOLATION)
+#define ISP_EVENT_STATS_OVERFLOW (ISP_EVENT_BASE + ISP_STATS_OVERFLOW)
+#define ISP_EVENT_ERROR (ISP_EVENT_BASE + ISP_ERROR)
+#define ISP_EVENT_SOF (ISP_CAMIF_EVENT_BASE)
+#define ISP_EVENT_EOF (ISP_CAMIF_EVENT_BASE + 1)
+#define ISP_EVENT_BUF_DONE (ISP_EVENT_BASE + ISP_BUF_DONE)
+#define ISP_EVENT_BUF_DIVERT (ISP_BUF_EVENT_BASE)
+#define ISP_EVENT_STATS_NOTIFY (ISP_STATS_EVENT_BASE)
+#define ISP_EVENT_COMP_STATS_NOTIFY (ISP_EVENT_STATS_NOTIFY + MSM_ISP_STATS_MAX)
+#define ISP_EVENT_FE_READ_DONE (ISP_EVENT_BASE + ISP_FE_RD_DONE)
+#define ISP_EVENT_IOMMU_P_FAULT (ISP_EVENT_BASE + ISP_IOMMU_P_FAULT)
+#define ISP_EVENT_HW_FATAL_ERROR (ISP_EVENT_BASE + ISP_HW_FATAL_ERROR)
+#define ISP_EVENT_PING_PONG_MISMATCH (ISP_EVENT_BASE + ISP_PING_PONG_MISMATCH)
+#define ISP_EVENT_REG_UPDATE_MISSING (ISP_EVENT_BASE + ISP_REG_UPDATE_MISSING)
+#define ISP_EVENT_BUF_FATAL_ERROR (ISP_EVENT_BASE + ISP_BUF_FATAL_ERROR)
+#define ISP_EVENT_STREAM_UPDATE_DONE (ISP_STREAM_EVENT_BASE)
+
+/* The msm_v4l2_event_data structure should match the
+ * v4l2_event.u.data field.
+ * should not exceed 64 bytes
+ */
+
+struct msm_isp_buf_event {
+ uint32_t session_id;
+ uint32_t stream_id;
+ uint32_t handle;
+ uint32_t output_format;
+ int8_t buf_idx;
+};
+struct msm_isp_fetch_eng_event {
+ uint32_t session_id;
+ uint32_t stream_id;
+ uint32_t handle;
+ uint32_t fd;
+ int8_t buf_idx;
+ int8_t offline_mode;
+};
+struct msm_isp_stats_event {
+ uint32_t stats_mask; /* 4 bytes */
+ uint8_t stats_buf_idxs[MSM_ISP_STATS_MAX]; /* 11 bytes */
+ uint8_t pd_stats_idx;
+};
+
+struct msm_isp_stream_ack {
+ uint32_t session_id;
+ uint32_t stream_id;
+ uint32_t handle;
+};
+
+enum msm_vfe_error_type {
+ ISP_ERROR_NONE,
+ ISP_ERROR_CAMIF,
+ ISP_ERROR_BUS_OVERFLOW,
+ ISP_ERROR_RETURN_EMPTY_BUFFER,
+ ISP_ERROR_FRAME_ID_MISMATCH,
+ ISP_ERROR_MAX,
+};
+
+struct msm_isp_error_info {
+ enum msm_vfe_error_type err_type;
+ uint32_t session_id;
+ uint32_t stream_id;
+ uint32_t stream_id_mask;
+};
+
+/* This structure reports delta between master and slave */
+struct msm_isp_ms_delta_info {
+ uint8_t num_delta_info;
+ uint32_t delta[MS_NUM_SLAVE_MAX];
+};
+
+/* This is sent in EPOCH irq */
+struct msm_isp_output_info {
+ uint8_t regs_not_updated;
+ /* mask with bufq_handle for regs not updated or return empty */
+ uint16_t output_err_mask;
+ /* mask with stream_idx for get_buf failed */
+ uint8_t stream_framedrop_mask;
+ /* mask with stats stream_idx for get_buf failed */
+ uint16_t stats_framedrop_mask;
+ /* delta between master and slave */
+};
+
+/* This structure is piggybacked with SOF event */
+struct msm_isp_sof_info {
+ uint8_t regs_not_updated;
+ /* mask with bufq_handle for regs not updated */
+ uint16_t reg_update_fail_mask;
+ /* mask with bufq_handle for get_buf failed */
+ uint32_t stream_get_buf_fail_mask;
+ /* mask with stats stream_idx for get_buf failed */
+ uint16_t stats_get_buf_fail_mask;
+ /* delta between master and slave */
+ struct msm_isp_ms_delta_info ms_delta_info;
+ /*
+ * mask with AXI_SRC in paused state. In PAUSED
+ * state there is no Buffer output. So this mask is used
+ * to report drop.
+ */
+ uint16_t axi_updating_mask;
+ /* extended mask with bufq_handle for regs not updated */
+ uint32_t reg_update_fail_mask_ext;
+};
+#define AXI_UPDATING_MASK 1
+#define REG_UPDATE_FAIL_MASK_EXT 1
+
+struct msm_isp_event_data {
+ /*Wall clock except for buffer divert events
+ *which use monotonic clock
+ */
+ struct timeval timestamp;
+ /* Monotonic timestamp since bootup */
+ struct timeval mono_timestamp;
+ uint32_t frame_id;
+ union {
+ /* Sent for Stats_Done event */
+ struct msm_isp_stats_event stats;
+ /* Sent for Buf_Divert event */
+ struct msm_isp_buf_event buf_done;
+ /* Sent for offline fetch done event */
+ struct msm_isp_fetch_eng_event fetch_done;
+ /* Sent for Error_Event */
+ struct msm_isp_error_info error_info;
+ /*
+ * This struct needs to be removed once
+ * userspace switches to sof_info
+ */
+ struct msm_isp_output_info output_info;
+ /* Sent for SOF event */
+ struct msm_isp_sof_info sof_info;
+ } u; /* union can have max 52 bytes */
+};
+
+enum msm_vfe_ahb_clk_vote {
+ MSM_ISP_CAMERA_AHB_SVS_VOTE = 1,
+ MSM_ISP_CAMERA_AHB_TURBO_VOTE = 2,
+ MSM_ISP_CAMERA_AHB_NOMINAL_VOTE = 3,
+ MSM_ISP_CAMERA_AHB_SUSPEND_VOTE = 4,
+};
+
+struct msm_isp_ahb_clk_cfg {
+ uint32_t vote;
+ uint32_t reserved[2];
+};
+
+enum msm_vfe_dual_cam_sync_mode {
+ MSM_ISP_DUAL_CAM_ASYNC,
+ MSM_ISP_DUAL_CAM_SYNC,
+};
+
+struct msm_isp_dual_hw_master_slave_sync {
+ uint32_t sync_mode;
+ uint32_t reserved[2];
+};
+
+struct msm_vfe_dual_lpm_mode {
+ enum msm_vfe_axi_stream_src stream_src[VFE_AXI_SRC_MAX];
+ uint32_t num_src;
+ uint32_t lpm_mode;
+};
+#define V4L2_PIX_FMT_QBGGR8 v4l2_fourcc('Q', 'B', 'G', '8')
+#define V4L2_PIX_FMT_QGBRG8 v4l2_fourcc('Q', 'G', 'B', '8')
+#define V4L2_PIX_FMT_QGRBG8 v4l2_fourcc('Q', 'G', 'R', '8')
+#define V4L2_PIX_FMT_QRGGB8 v4l2_fourcc('Q', 'R', 'G', '8')
+#define V4L2_PIX_FMT_QBGGR10 v4l2_fourcc('Q', 'B', 'G', '0')
+#define V4L2_PIX_FMT_QGBRG10 v4l2_fourcc('Q', 'G', 'B', '0')
+#define V4L2_PIX_FMT_QGRBG10 v4l2_fourcc('Q', 'G', 'R', '0')
+#define V4L2_PIX_FMT_QRGGB10 v4l2_fourcc('Q', 'R', 'G', '0')
+#define V4L2_PIX_FMT_QBGGR12 v4l2_fourcc('Q', 'B', 'G', '2')
+#define V4L2_PIX_FMT_QGBRG12 v4l2_fourcc('Q', 'G', 'B', '2')
+#define V4L2_PIX_FMT_QGRBG12 v4l2_fourcc('Q', 'G', 'R', '2')
+#define V4L2_PIX_FMT_QRGGB12 v4l2_fourcc('Q', 'R', 'G', '2')
+#define V4L2_PIX_FMT_QBGGR14 v4l2_fourcc('Q', 'B', 'G', '4')
+#define V4L2_PIX_FMT_QGBRG14 v4l2_fourcc('Q', 'G', 'B', '4')
+#define V4L2_PIX_FMT_QGRBG14 v4l2_fourcc('Q', 'G', 'R', '4')
+#define V4L2_PIX_FMT_QRGGB14 v4l2_fourcc('Q', 'R', 'G', '4')
+#define V4L2_PIX_FMT_P16BGGR10 v4l2_fourcc('P', 'B', 'G', '0')
+#define V4L2_PIX_FMT_P16GBRG10 v4l2_fourcc('P', 'G', 'B', '0')
+#define V4L2_PIX_FMT_P16GRBG10 v4l2_fourcc('P', 'G', 'R', '0')
+#define V4L2_PIX_FMT_P16RGGB10 v4l2_fourcc('P', 'R', 'G', '0')
+#define V4L2_PIX_FMT_NV14 v4l2_fourcc('N', 'V', '1', '4')
+#define V4L2_PIX_FMT_NV41 v4l2_fourcc('N', 'V', '4', '1')
+#define V4L2_PIX_FMT_META v4l2_fourcc('Q', 'M', 'E', 'T')
+#define V4L2_PIX_FMT_META10 v4l2_fourcc('Q', 'M', '1', '0')
+#define V4L2_PIX_FMT_SBGGR14 v4l2_fourcc('B', 'G', '1', '4') /* 14 BGBG.GRGR.*/
+#define V4L2_PIX_FMT_SGBRG14 v4l2_fourcc('G', 'B', '1', '4') /* 14 GBGB.RGRG.*/
+#define V4L2_PIX_FMT_SGRBG14 v4l2_fourcc('B', 'A', '1', '4') /* 14 GRGR.BGBG.*/
+#define V4L2_PIX_FMT_SRGGB14 v4l2_fourcc('R', 'G', '1', '4') /* 14 RGRG.GBGB.*/
+
+enum msm_isp_ioctl_cmd_code {
+ MSM_VFE_REG_CFG = BASE_VIDIOC_PRIVATE,
+ MSM_ISP_REQUEST_BUF,
+ MSM_ISP_ENQUEUE_BUF,
+ MSM_ISP_RELEASE_BUF,
+ MSM_ISP_REQUEST_STREAM,
+ MSM_ISP_CFG_STREAM,
+ MSM_ISP_RELEASE_STREAM,
+ MSM_ISP_INPUT_CFG,
+ MSM_ISP_SET_SRC_STATE,
+ MSM_ISP_REQUEST_STATS_STREAM,
+ MSM_ISP_CFG_STATS_STREAM,
+ MSM_ISP_RELEASE_STATS_STREAM,
+ MSM_ISP_REG_UPDATE_CMD,
+ MSM_ISP_UPDATE_STREAM,
+ MSM_VFE_REG_LIST_CFG,
+ MSM_ISP_SMMU_ATTACH,
+ MSM_ISP_UPDATE_STATS_STREAM,
+ MSM_ISP_AXI_HALT,
+ MSM_ISP_AXI_RESET,
+ MSM_ISP_AXI_RESTART,
+ MSM_ISP_FETCH_ENG_START,
+ MSM_ISP_DEQUEUE_BUF,
+ MSM_ISP_SET_DUAL_HW_MASTER_SLAVE,
+ MSM_ISP_MAP_BUF_START_FE,
+ MSM_ISP_UNMAP_BUF,
+ MSM_ISP_AHB_CLK_CFG,
+ MSM_ISP_DUAL_HW_MASTER_SLAVE_SYNC,
+ MSM_ISP_FETCH_ENG_MULTI_PASS_START,
+ MSM_ISP_MAP_BUF_START_MULTI_PASS_FE,
+ MSM_ISP_REQUEST_BUF_VER2,
+ MSM_ISP_DUAL_HW_LPM_MODE,
+};
+
+#define VIDIOC_MSM_VFE_REG_CFG \
+ _IOWR('V', MSM_VFE_REG_CFG, \
+ struct msm_vfe_cfg_cmd2)
+
+#define VIDIOC_MSM_ISP_REQUEST_BUF \
+ _IOWR('V', MSM_ISP_REQUEST_BUF, \
+ struct msm_isp_buf_request)
+
+#define VIDIOC_MSM_ISP_ENQUEUE_BUF \
+ _IOWR('V', MSM_ISP_ENQUEUE_BUF, \
+ struct msm_isp_qbuf_info)
+
+#define VIDIOC_MSM_ISP_RELEASE_BUF \
+ _IOWR('V', MSM_ISP_RELEASE_BUF, \
+ struct msm_isp_buf_request)
+
+#define VIDIOC_MSM_ISP_REQUEST_STREAM \
+ _IOWR('V', MSM_ISP_REQUEST_STREAM, \
+ struct msm_vfe_axi_stream_request_cmd)
+
+#define VIDIOC_MSM_ISP_CFG_STREAM \
+ _IOWR('V', MSM_ISP_CFG_STREAM, \
+ struct msm_vfe_axi_stream_cfg_cmd)
+
+#define VIDIOC_MSM_ISP_RELEASE_STREAM \
+ _IOWR('V', MSM_ISP_RELEASE_STREAM, \
+ struct msm_vfe_axi_stream_release_cmd)
+
+#define VIDIOC_MSM_ISP_INPUT_CFG \
+ _IOWR('V', MSM_ISP_INPUT_CFG, \
+ struct msm_vfe_input_cfg)
+
+#define VIDIOC_MSM_ISP_SET_SRC_STATE \
+ _IOWR('V', MSM_ISP_SET_SRC_STATE, \
+ struct msm_vfe_axi_src_state)
+
+#define VIDIOC_MSM_ISP_REQUEST_STATS_STREAM \
+ _IOWR('V', MSM_ISP_REQUEST_STATS_STREAM, \
+ struct msm_vfe_stats_stream_request_cmd)
+
+#define VIDIOC_MSM_ISP_CFG_STATS_STREAM \
+ _IOWR('V', MSM_ISP_CFG_STATS_STREAM, \
+ struct msm_vfe_stats_stream_cfg_cmd)
+
+#define VIDIOC_MSM_ISP_RELEASE_STATS_STREAM \
+ _IOWR('V', MSM_ISP_RELEASE_STATS_STREAM, \
+ struct msm_vfe_stats_stream_release_cmd)
+
+#define VIDIOC_MSM_ISP_REG_UPDATE_CMD \
+ _IOWR('V', MSM_ISP_REG_UPDATE_CMD, \
+ enum msm_vfe_input_src)
+
+#define VIDIOC_MSM_ISP_UPDATE_STREAM \
+ _IOWR('V', MSM_ISP_UPDATE_STREAM, \
+ struct msm_vfe_axi_stream_update_cmd)
+
+#define VIDIOC_MSM_VFE_REG_LIST_CFG \
+ _IOWR('V', MSM_VFE_REG_LIST_CFG, \
+ struct msm_vfe_cfg_cmd_list)
+
+#define VIDIOC_MSM_ISP_SMMU_ATTACH \
+ _IOWR('V', MSM_ISP_SMMU_ATTACH, \
+ struct msm_vfe_smmu_attach_cmd)
+
+#define VIDIOC_MSM_ISP_UPDATE_STATS_STREAM \
+ _IOWR('V', MSM_ISP_UPDATE_STATS_STREAM, \
+ struct msm_vfe_axi_stream_update_cmd)
+
+#define VIDIOC_MSM_ISP_AXI_HALT \
+ _IOWR('V', MSM_ISP_AXI_HALT, \
+ struct msm_vfe_axi_halt_cmd)
+
+#define VIDIOC_MSM_ISP_AXI_RESET \
+ _IOWR('V', MSM_ISP_AXI_RESET, \
+ struct msm_vfe_axi_reset_cmd)
+
+#define VIDIOC_MSM_ISP_AXI_RESTART \
+ _IOWR('V', MSM_ISP_AXI_RESTART, \
+ struct msm_vfe_axi_restart_cmd)
+
+#define VIDIOC_MSM_ISP_FETCH_ENG_START \
+ _IOWR('V', MSM_ISP_FETCH_ENG_START, \
+ struct msm_vfe_fetch_eng_start)
+
+#define VIDIOC_MSM_ISP_DEQUEUE_BUF \
+ _IOWR('V', MSM_ISP_DEQUEUE_BUF, \
+ struct msm_isp_qbuf_info)
+
+#define VIDIOC_MSM_ISP_SET_DUAL_HW_MASTER_SLAVE \
+ _IOWR('V', MSM_ISP_SET_DUAL_HW_MASTER_SLAVE, \
+ struct msm_isp_set_dual_hw_ms_cmd)
+
+#define VIDIOC_MSM_ISP_MAP_BUF_START_FE \
+ _IOWR('V', MSM_ISP_MAP_BUF_START_FE, \
+ struct msm_vfe_fetch_eng_start)
+
+#define VIDIOC_MSM_ISP_UNMAP_BUF \
+ _IOWR('V', MSM_ISP_UNMAP_BUF, \
+ struct msm_isp_unmap_buf_req)
+
+#define VIDIOC_MSM_ISP_AHB_CLK_CFG \
+ _IOWR('V', MSM_ISP_AHB_CLK_CFG, struct msm_isp_ahb_clk_cfg)
+
+#define VIDIOC_MSM_ISP_DUAL_HW_MASTER_SLAVE_SYNC \
+ _IOWR('V', MSM_ISP_DUAL_HW_MASTER_SLAVE_SYNC, \
+ struct msm_isp_dual_hw_master_slave_sync)
+
+#define VIDIOC_MSM_ISP_FETCH_ENG_MULTI_PASS_START \
+ _IOWR('V', MSM_ISP_FETCH_ENG_MULTI_PASS_START, \
+ struct msm_vfe_fetch_eng_multi_pass_start)
+
+#define VIDIOC_MSM_ISP_MAP_BUF_START_MULTI_PASS_FE \
+ _IOWR('V', MSM_ISP_MAP_BUF_START_MULTI_PASS_FE, \
+ struct msm_vfe_fetch_eng_multi_pass_start)
+
+#define VIDIOC_MSM_ISP_REQUEST_BUF_VER2 \
+ _IOWR('V', MSM_ISP_REQUEST_BUF_VER2, struct msm_isp_buf_request_ver2)
+
+#define VIDIOC_MSM_ISP_DUAL_HW_LPM_MODE \
+ _IOWR('V', MSM_ISP_DUAL_HW_LPM_MODE, \
+ struct msm_vfe_dual_lpm_mode)
+
+#endif /* __MSMB_ISP__ */
diff --git a/include/uapi/media/msmb_ispif.h b/include/uapi/media/msmb_ispif.h
new file mode 100644
index 0000000..d532037
--- /dev/null
+++ b/include/uapi/media/msmb_ispif.h
@@ -0,0 +1,179 @@
+#ifndef UAPI_MSMB_ISPIF_H
+#define UAPI_MSMB_ISPIF_H
+
+#include <linux/types.h>
+#include <linux/ioctl.h>
+#include <linux/videodev2.h>
+
+#define CSID_VERSION_V20 0x02000011
+#define CSID_VERSION_V22 0x02001000
+#define CSID_VERSION_V30 0x30000000
+#define CSID_VERSION_V3 0x30000000
+
+enum msm_ispif_vfe_intf {
+ VFE0,
+ VFE1,
+ VFE_MAX
+};
+#define VFE0_MASK (1 << VFE0)
+#define VFE1_MASK (1 << VFE1)
+
+enum msm_ispif_intftype {
+ PIX0,
+ RDI0,
+ PIX1,
+ RDI1,
+ RDI2,
+ INTF_MAX
+};
+#define MAX_PARAM_ENTRIES (INTF_MAX * 2)
+#define MAX_CID_CH 8
+#define MAX_CID_CH_PARAM_ENTRY 3
+
+#define PIX0_MASK (1 << PIX0)
+#define PIX1_MASK (1 << PIX1)
+#define RDI0_MASK (1 << RDI0)
+#define RDI1_MASK (1 << RDI1)
+#define RDI2_MASK (1 << RDI2)
+
+enum msm_ispif_vc {
+ VC0,
+ VC1,
+ VC2,
+ VC3,
+ VC_MAX
+};
+
+enum msm_ispif_cid {
+ CID0,
+ CID1,
+ CID2,
+ CID3,
+ CID4,
+ CID5,
+ CID6,
+ CID7,
+ CID8,
+ CID9,
+ CID10,
+ CID11,
+ CID12,
+ CID13,
+ CID14,
+ CID15,
+ CID_MAX
+};
+
+enum msm_ispif_csid {
+ CSID0,
+ CSID1,
+ CSID2,
+ CSID3,
+ CSID_MAX
+};
+
+enum msm_ispif_pixel_odd_even {
+ PIX_EVEN,
+ PIX_ODD
+};
+
+enum msm_ispif_pixel_pack_mode {
+ PACK_BYTE,
+ PACK_PLAIN_PACK,
+ PACK_NV_P8,
+ PACK_NV_P16
+};
+
+struct msm_ispif_pack_cfg {
+ int pixel_swap_en;
+ enum msm_ispif_pixel_odd_even even_odd_sel;
+ enum msm_ispif_pixel_pack_mode pack_mode;
+};
+
+struct msm_ispif_params_entry {
+ enum msm_ispif_vfe_intf vfe_intf;
+ enum msm_ispif_intftype intftype;
+ int num_cids;
+ enum msm_ispif_cid cids[MAX_CID_CH_PARAM_ENTRY];
+ enum msm_ispif_csid csid;
+ int crop_enable;
+ uint16_t crop_start_pixel;
+ uint16_t crop_end_pixel;
+};
+
+struct msm_ispif_right_param_entry {
+ enum msm_ispif_cid cids[MAX_CID_CH_PARAM_ENTRY];
+ enum msm_ispif_csid csid;
+};
+
+struct msm_ispif_param_data_ext {
+ uint32_t num;
+ struct msm_ispif_params_entry entries[MAX_PARAM_ENTRIES];
+ struct msm_ispif_pack_cfg pack_cfg[CID_MAX];
+ struct msm_ispif_right_param_entry right_entries[MAX_PARAM_ENTRIES];
+ uint32_t stereo_enable;
+ uint16_t line_width[VFE_MAX];
+};
+
+struct msm_ispif_param_data {
+ uint32_t num;
+ struct msm_ispif_params_entry entries[MAX_PARAM_ENTRIES];
+};
+
+struct msm_isp_info {
+ uint32_t max_resolution;
+ uint32_t id;
+ uint32_t ver;
+};
+
+struct msm_ispif_vfe_info {
+ int num_vfe;
+ struct msm_isp_info info[VFE_MAX];
+};
+
+enum ispif_cfg_type_t {
+ ISPIF_CLK_ENABLE,
+ ISPIF_CLK_DISABLE,
+ ISPIF_INIT,
+ ISPIF_CFG,
+ ISPIF_START_FRAME_BOUNDARY,
+ ISPIF_RESTART_FRAME_BOUNDARY,
+ ISPIF_STOP_FRAME_BOUNDARY,
+ ISPIF_STOP_IMMEDIATELY,
+ ISPIF_RELEASE,
+ ISPIF_ENABLE_REG_DUMP,
+ ISPIF_SET_VFE_INFO,
+ ISPIF_CFG2,
+ ISPIF_CFG_STEREO,
+};
+
+struct ispif_cfg_data {
+ enum ispif_cfg_type_t cfg_type;
+ union {
+ int reg_dump; /* ISPIF_ENABLE_REG_DUMP */
+ uint32_t csid_version; /* ISPIF_INIT */
+ struct msm_ispif_vfe_info vfe_info; /* ISPIF_SET_VFE_INFO */
+ struct msm_ispif_param_data params; /* CFG, START, STOP */
+ };
+};
+
+struct ispif_cfg_data_ext {
+ enum ispif_cfg_type_t cfg_type;
+ void __user *data;
+ uint32_t size;
+};
+
+#define ISPIF_RDI_PACK_MODE_SUPPORT 1
+
+#define ISPIF_3D_SUPPORT 1
+
+#define ISPIF_LINE_WIDTH_SUPPORT 1
+
+#define VIDIOC_MSM_ISPIF_CFG \
+ _IOWR('V', BASE_VIDIOC_PRIVATE, struct ispif_cfg_data)
+
+#define VIDIOC_MSM_ISPIF_CFG_EXT \
+ _IOWR('V', BASE_VIDIOC_PRIVATE+1, struct ispif_cfg_data_ext)
+
+#endif
+
diff --git a/include/uapi/media/msmb_pproc.h b/include/uapi/media/msmb_pproc.h
new file mode 100644
index 0000000..8f45457
--- /dev/null
+++ b/include/uapi/media/msmb_pproc.h
@@ -0,0 +1,255 @@
+#ifndef __UAPI_MSMB_PPROC_H
+#define __UAPI_MSMB_PPROC_H
+
+#include <linux/videodev2.h>
+#include <linux/types.h>
+#include <media/msmb_generic_buf_mgr.h>
+
+/* Should be same as VIDEO_MAX_PLANES in videodev2.h */
+#define MAX_PLANES VIDEO_MAX_PLANES
+/* PARTIAL_FRAME_STRIPE_COUNT must be even */
+#define PARTIAL_FRAME_STRIPE_COUNT 4
+
+#define MAX_NUM_CPP_STRIPS 8
+#define MSM_CPP_MAX_NUM_PLANES 3
+#define MSM_CPP_MIN_FRAME_LENGTH 13
+#define MSM_CPP_MAX_FRAME_LENGTH 4096
+#define MSM_CPP_MAX_FW_NAME_LEN 32
+#define MAX_FREQ_TBL 10
+#define MSM_OUTPUT_BUF_CNT 8
+
+enum msm_cpp_frame_type {
+ MSM_CPP_OFFLINE_FRAME,
+ MSM_CPP_REALTIME_FRAME,
+};
+
+enum msm_vpe_frame_type {
+ MSM_VPE_OFFLINE_FRAME,
+ MSM_VPE_REALTIME_FRAME,
+};
+
+struct msm_cpp_buffer_info_t {
+ int32_t fd;
+ uint32_t index;
+ uint32_t offset;
+ uint8_t native_buff;
+ uint8_t processed_divert;
+ uint32_t identity;
+};
+
+struct msm_cpp_stream_buff_info_t {
+ uint32_t identity;
+ uint32_t num_buffs;
+ struct msm_cpp_buffer_info_t *buffer_info;
+};
+
+enum msm_cpp_batch_mode_t {
+ BATCH_MODE_NONE,
+ BATCH_MODE_VIDEO,
+ BATCH_MODE_PREVIEW
+};
+
+struct msm_cpp_batch_info_t {
+ enum msm_cpp_batch_mode_t batch_mode;
+ uint32_t batch_size;
+ uint32_t intra_plane_offset[MAX_PLANES];
+ uint32_t pick_preview_idx;
+ uint32_t cont_idx;
+};
+
+struct msm_cpp_frame_info_t {
+ int32_t frame_id;
+ struct timeval timestamp;
+ uint32_t inst_id;
+ uint32_t identity;
+ uint32_t client_id;
+ enum msm_cpp_frame_type frame_type;
+ uint32_t num_strips;
+ uint32_t msg_len;
+ uint32_t *cpp_cmd_msg;
+ int src_fd;
+ int dst_fd;
+ struct timeval in_time, out_time;
+ void __user *cookie;
+ int32_t *status;
+ int32_t duplicate_output;
+ uint32_t duplicate_identity;
+ uint32_t feature_mask;
+ uint8_t we_disable;
+ struct msm_cpp_buffer_info_t input_buffer_info;
+ struct msm_cpp_buffer_info_t output_buffer_info[MSM_OUTPUT_BUF_CNT];
+ struct msm_cpp_buffer_info_t duplicate_buffer_info;
+ struct msm_cpp_buffer_info_t tnr_scratch_buffer_info[2];
+ uint32_t reserved;
+ uint8_t partial_frame_indicator;
+ /* the followings are used only for partial_frame type
+ * and is only used for offline frame processing and
+ * only if payload big enough and need to be split into partial_frame
+ * if first_payload, kernel acquires output buffer
+ * first payload must have the last stripe
+ * buffer addresses from 0 to last_stripe_index are updated.
+ * kernel updates payload with msg_len and stripe_info
+ * kernel sends top level, plane level, then only stripes
+ * starting with first_stripe_index and
+ * ends with last_stripe_index
+ * kernel then sends trailing flag at frame done,
+ * if last payload, kernel queues the output buffer to HAL
+ */
+ uint8_t first_payload;
+ uint8_t last_payload;
+ uint32_t first_stripe_index;
+ uint32_t last_stripe_index;
+ uint32_t stripe_info_offset;
+ uint32_t stripe_info;
+ struct msm_cpp_batch_info_t batch_info;
+};
+
+struct msm_cpp_pop_stream_info_t {
+ int32_t frame_id;
+ uint32_t identity;
+};
+
+struct cpp_hw_info {
+ uint32_t cpp_hw_version;
+ uint32_t cpp_hw_caps;
+ unsigned long freq_tbl[MAX_FREQ_TBL];
+ uint32_t freq_tbl_count;
+};
+
+struct msm_vpe_frame_strip_info {
+ uint32_t src_w;
+ uint32_t src_h;
+ uint32_t dst_w;
+ uint32_t dst_h;
+ uint32_t src_x;
+ uint32_t src_y;
+ uint32_t phase_step_x;
+ uint32_t phase_step_y;
+ uint32_t phase_init_x;
+ uint32_t phase_init_y;
+};
+
+struct msm_vpe_buffer_info_t {
+ int32_t fd;
+ uint32_t index;
+ uint32_t offset;
+ uint8_t native_buff;
+ uint8_t processed_divert;
+};
+
+struct msm_vpe_stream_buff_info_t {
+ uint32_t identity;
+ uint32_t num_buffs;
+ struct msm_vpe_buffer_info_t *buffer_info;
+};
+
+struct msm_vpe_frame_info_t {
+ int32_t frame_id;
+ struct timeval timestamp;
+ uint32_t inst_id;
+ uint32_t identity;
+ uint32_t client_id;
+ enum msm_vpe_frame_type frame_type;
+ struct msm_vpe_frame_strip_info strip_info;
+ unsigned long src_fd;
+ unsigned long dst_fd;
+ struct ion_handle *src_ion_handle;
+ struct ion_handle *dest_ion_handle;
+ unsigned long src_phyaddr;
+ unsigned long dest_phyaddr;
+ unsigned long src_chroma_plane_offset;
+ unsigned long dest_chroma_plane_offset;
+ struct timeval in_time, out_time;
+ void *cookie;
+
+ struct msm_vpe_buffer_info_t input_buffer_info;
+ struct msm_vpe_buffer_info_t output_buffer_info;
+};
+
+struct msm_pproc_queue_buf_info {
+ struct msm_buf_mngr_info buff_mgr_info;
+ uint8_t is_buf_dirty;
+};
+
+struct msm_cpp_clock_settings_t {
+ unsigned long clock_rate;
+ uint64_t avg;
+ uint64_t inst;
+};
+
+#define VIDIOC_MSM_CPP_CFG \
+ _IOWR('V', BASE_VIDIOC_PRIVATE, struct msm_camera_v4l2_ioctl_t)
+
+#define VIDIOC_MSM_CPP_GET_EVENTPAYLOAD \
+ _IOWR('V', BASE_VIDIOC_PRIVATE + 1, struct msm_camera_v4l2_ioctl_t)
+
+#define VIDIOC_MSM_CPP_GET_INST_INFO \
+ _IOWR('V', BASE_VIDIOC_PRIVATE + 2, struct msm_camera_v4l2_ioctl_t)
+
+#define VIDIOC_MSM_CPP_LOAD_FIRMWARE \
+ _IOWR('V', BASE_VIDIOC_PRIVATE + 3, struct msm_camera_v4l2_ioctl_t)
+
+#define VIDIOC_MSM_CPP_GET_HW_INFO \
+ _IOWR('V', BASE_VIDIOC_PRIVATE + 4, struct msm_camera_v4l2_ioctl_t)
+
+#define VIDIOC_MSM_CPP_FLUSH_QUEUE \
+ _IOWR('V', BASE_VIDIOC_PRIVATE + 5, struct msm_camera_v4l2_ioctl_t)
+
+#define VIDIOC_MSM_CPP_ENQUEUE_STREAM_BUFF_INFO \
+ _IOWR('V', BASE_VIDIOC_PRIVATE + 6, struct msm_camera_v4l2_ioctl_t)
+
+#define VIDIOC_MSM_CPP_DEQUEUE_STREAM_BUFF_INFO \
+ _IOWR('V', BASE_VIDIOC_PRIVATE + 7, struct msm_camera_v4l2_ioctl_t)
+
+#define VIDIOC_MSM_VPE_CFG \
+ _IOWR('V', BASE_VIDIOC_PRIVATE + 8, struct msm_camera_v4l2_ioctl_t)
+
+#define VIDIOC_MSM_VPE_TRANSACTION_SETUP \
+ _IOWR('V', BASE_VIDIOC_PRIVATE + 9, struct msm_camera_v4l2_ioctl_t)
+
+#define VIDIOC_MSM_VPE_GET_EVENTPAYLOAD \
+ _IOWR('V', BASE_VIDIOC_PRIVATE + 10, struct msm_camera_v4l2_ioctl_t)
+
+#define VIDIOC_MSM_VPE_GET_INST_INFO \
+ _IOWR('V', BASE_VIDIOC_PRIVATE + 11, struct msm_camera_v4l2_ioctl_t)
+
+#define VIDIOC_MSM_VPE_ENQUEUE_STREAM_BUFF_INFO \
+ _IOWR('V', BASE_VIDIOC_PRIVATE + 12, struct msm_camera_v4l2_ioctl_t)
+
+#define VIDIOC_MSM_VPE_DEQUEUE_STREAM_BUFF_INFO \
+ _IOWR('V', BASE_VIDIOC_PRIVATE + 13, struct msm_camera_v4l2_ioctl_t)
+
+#define VIDIOC_MSM_CPP_QUEUE_BUF \
+ _IOWR('V', BASE_VIDIOC_PRIVATE + 14, struct msm_camera_v4l2_ioctl_t)
+
+#define VIDIOC_MSM_CPP_APPEND_STREAM_BUFF_INFO \
+ _IOWR('V', BASE_VIDIOC_PRIVATE + 15, struct msm_camera_v4l2_ioctl_t)
+
+#define VIDIOC_MSM_CPP_SET_CLOCK \
+ _IOWR('V', BASE_VIDIOC_PRIVATE + 16, struct msm_camera_v4l2_ioctl_t)
+
+#define VIDIOC_MSM_CPP_POP_STREAM_BUFFER \
+ _IOWR('V', BASE_VIDIOC_PRIVATE + 17, struct msm_camera_v4l2_ioctl_t)
+
+#define VIDIOC_MSM_CPP_IOMMU_ATTACH \
+ _IOWR('V', BASE_VIDIOC_PRIVATE + 18, struct msm_camera_v4l2_ioctl_t)
+
+#define VIDIOC_MSM_CPP_IOMMU_DETACH \
+ _IOWR('V', BASE_VIDIOC_PRIVATE + 19, struct msm_camera_v4l2_ioctl_t)
+
+#define VIDIOC_MSM_CPP_DELETE_STREAM_BUFF\
+ _IOWR('V', BASE_VIDIOC_PRIVATE + 20, struct msm_camera_v4l2_ioctl_t)
+
+
+#define V4L2_EVENT_CPP_FRAME_DONE (V4L2_EVENT_PRIVATE_START + 0)
+#define V4L2_EVENT_VPE_FRAME_DONE (V4L2_EVENT_PRIVATE_START + 1)
+
+struct msm_camera_v4l2_ioctl_t {
+ uint32_t id;
+ size_t len;
+ int32_t trans_code;
+ void __user *ioctl_ptr;
+};
+
+#endif
+