ARM: cns3xxx: Use IO memory accessors everywhere
Before it isn't too late let's switch to IO memory accessors.
This patch converts all current _REG users and _REG definitions.
There should be no functional changes.
Suggested-by: Ben Dooks <ben-linux@fluff.org>
Suggested-by: Sergei Shtylyov <sshtylyov@mvista.com>
Signed-off-by: Anton Vorontsov <avorontsov@mvista.com>
diff --git a/arch/arm/mach-cns3xxx/pm.c b/arch/arm/mach-cns3xxx/pm.c
index 725e1a4..38e4470 100644
--- a/arch/arm/mach-cns3xxx/pm.c
+++ b/arch/arm/mach-cns3xxx/pm.c
@@ -6,18 +6,25 @@
* published by the Free Software Foundation.
*/
+#include <linux/io.h>
#include <linux/delay.h>
#include <mach/system.h>
#include <mach/cns3xxx.h>
void cns3xxx_pwr_clk_en(unsigned int block)
{
- PM_CLK_GATE_REG |= (block & PM_CLK_GATE_REG_MASK);
+ u32 reg = __raw_readl(PM_CLK_GATE_REG);
+
+ reg |= (block & PM_CLK_GATE_REG_MASK);
+ __raw_writel(reg, PM_CLK_GATE_REG);
}
void cns3xxx_pwr_power_up(unsigned int block)
{
- PM_PLL_HM_PD_CTRL_REG &= ~(block & CNS3XXX_PWR_PLL_ALL);
+ u32 reg = __raw_readl(PM_PLL_HM_PD_CTRL_REG);
+
+ reg &= ~(block & CNS3XXX_PWR_PLL_ALL);
+ __raw_writel(reg, PM_PLL_HM_PD_CTRL_REG);
/* Wait for 300us for the PLL output clock locked. */
udelay(300);
@@ -25,22 +32,29 @@
void cns3xxx_pwr_power_down(unsigned int block)
{
+ u32 reg = __raw_readl(PM_PLL_HM_PD_CTRL_REG);
+
/* write '1' to power down */
- PM_PLL_HM_PD_CTRL_REG |= (block & CNS3XXX_PWR_PLL_ALL);
+ reg |= (block & CNS3XXX_PWR_PLL_ALL);
+ __raw_writel(reg, PM_PLL_HM_PD_CTRL_REG);
};
static void cns3xxx_pwr_soft_rst_force(unsigned int block)
{
+ u32 reg = __raw_readl(PM_SOFT_RST_REG);
+
/*
* bit 0, 28, 29 => program low to reset,
* the other else program low and then high
*/
if (block & 0x30000001) {
- PM_SOFT_RST_REG &= ~(block & PM_SOFT_RST_REG_MASK);
+ reg &= ~(block & PM_SOFT_RST_REG_MASK);
} else {
- PM_SOFT_RST_REG &= ~(block & PM_SOFT_RST_REG_MASK);
- PM_SOFT_RST_REG |= (block & PM_SOFT_RST_REG_MASK);
+ reg &= ~(block & PM_SOFT_RST_REG_MASK);
+ reg |= (block & PM_SOFT_RST_REG_MASK);
}
+
+ __raw_writel(reg, PM_SOFT_RST_REG);
}
void cns3xxx_pwr_soft_rst(unsigned int block)
@@ -73,12 +87,13 @@
*/
int cns3xxx_cpu_clock(void)
{
+ u32 reg = __raw_readl(PM_CLK_CTRL_REG);
int cpu;
int cpu_sel;
int div_sel;
- cpu_sel = (PM_CLK_CTRL_REG >> PM_CLK_CTRL_REG_OFFSET_PLL_CPU_SEL) & 0xf;
- div_sel = (PM_CLK_CTRL_REG >> PM_CLK_CTRL_REG_OFFSET_CPU_CLK_DIV) & 0x3;
+ cpu_sel = (reg >> PM_CLK_CTRL_REG_OFFSET_PLL_CPU_SEL) & 0xf;
+ div_sel = (reg >> PM_CLK_CTRL_REG_OFFSET_CPU_CLK_DIV) & 0x3;
cpu = (300 + ((cpu_sel / 3) * 100) + ((cpu_sel % 3) * 33)) >> div_sel;