commit 6f0aba63bfb3eb33b68cf746c44b6ab302599180
author Paul Burton <paul.burton@imgtec.com> Mon Jul 27 12:58:17 2015 -0700
committer Ralf Baechle <ralf@linux-mips.org> Thu Sep 03 12:07:56 2015 +0200
tree 01c394a504d3e87ab500c9e826f7602facb896ef
parent 64243c2a945640392b59fe1dc66c30ee1ca04170

MIPS: Skip odd double FP registers when copying FP32 sigcontext

When a task uses 32 bit floating point, the odd indexed 32b register
values are stored in bits 63:32 of the preceding even indexed 64b
FP register field in saved context. Thus there is no point in
preserving the odd indexed 64b register fields since they hold no
valid context. This patch will cause them to be skipped, as is
already done in arch/mips/kernel/signal32.c.

[ralf@linux-mips.org: Fixed reject.]

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: Guenter Roeck <linux@roeck-us.net>
Cc: Matthew Fortune <matthew.fortune@imgtec.com>
Cc: Michael Ellerman <mpe@ellerman.id.au>
Cc: linux-kernel@vger.kernel.org
Cc: Richard Weinberger <richard@nod.at>
Cc: Andy Lutomirski <luto@amacapital.net>
Cc: Maciej W. Rozycki <macro@codesourcery.com>
Cc: Andrew Morton <akpm@linux-foundation.org>
Patchwork: https://patchwork.linux-mips.org/patch/10791/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

arch/mips/kernel/signal.c

diff --git a/arch/mips/kernel/signal.c b/arch/mips/kernel/signal.c
index 9c42c50..cc3a01f 100644
--- a/arch/mips/kernel/signal.c
+++ b/arch/mips/kernel/signal.c
@@ -69,8 +69,9 @@
 	uint32_t __user *csr = sc + abi->off_sc_fpc_csr;
 	int i;
 	int err = 0;
+	int inc = test_thread_flag(TIF_32BIT_FPREGS) ? 2 : 1;
 
-	for (i = 0; i < NUM_FPU_REGS; i++) {
+	for (i = 0; i < NUM_FPU_REGS; i += inc) {
 		err |=
 		    __put_user(get_fpr64(&current->thread.fpu.fpr[i], 0),
 			       &fpregs[i]);
@@ -87,9 +88,10 @@
 	uint32_t __user *csr = sc + abi->off_sc_fpc_csr;
 	int i;
 	int err = 0;
+	int inc = test_thread_flag(TIF_32BIT_FPREGS) ? 2 : 1;
 	u64 fpr_val;
 
-	for (i = 0; i < NUM_FPU_REGS; i++) {
+	for (i = 0; i < NUM_FPU_REGS; i += inc) {
 		err |= __get_user(fpr_val, &fpregs[i]);
 		set_fpr64(&current->thread.fpu.fpr[i], 0, fpr_val);
 	}