| commit | 6f15c506e0cec601fad9fabb7ded0d1811b8002f | [log] [tgz] |
|---|---|---|
| author | Alex Deucher <alexdeucher@gmail.com> | Fri May 20 12:36:12 2011 -0400 |
| committer | Dave Airlie <airlied@gmail.com> | Sun May 22 20:20:05 2011 +1000 |
| tree | 014495d41f3db1388f08412a4d690267b95bf99e | |
| parent | d291767b6056540277497d91baa9120428d7cd1a [diff] |
drm/radeon/kms: properly set the CLK_REF bit for DCE3 devices If the ss clock is external, the CLK_REF bit needs to be set in the SetPixelClock parameters. This should fix DP failures in the channel equalization loop. Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@gmail.com>