tree 014495d41f3db1388f08412a4d690267b95bf99e
parent d291767b6056540277497d91baa9120428d7cd1a
author Alex Deucher <alexdeucher@gmail.com> 1305909372 -0400
committer Dave Airlie <airlied@gmail.com> 1306059605 +1000

drm/radeon/kms: properly set the CLK_REF bit for DCE3 devices

If the ss clock is external, the CLK_REF bit needs to be set
in the SetPixelClock parameters.  This should fix DP failures
in the channel equalization loop.

Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Signed-off-by: Dave Airlie <airlied@gmail.com>