| commit | 704b93b3c101ec301516f2da9017ce25650be6b6 | [log] [tgz] |
|---|---|---|
| author | Shashank Babu Chinta Venkata <sbchin@codeaurora.org> | Mon Feb 06 15:23:11 2017 -0800 |
| committer | Shashank Babu Chinta Venkata <sbchin@codeaurora.org> | Fri Apr 07 11:34:05 2017 -0700 |
| tree | 893016624140b0aee3a5eedc01bac92921b22a49 | |
| parent | 49ae9119a5524835deed5f425c93f625dd6699c9 [diff] |
msm: clk: qcom: upstream clock framework support on 10nm MDSS PLL Configure MDSS DSI PLL using upstream clock framework APIs on 10 nm PLL driver Change-Id: Ic5ce623a6767d4f3a273ebbde8747ec35fe23c03 Signed-off-by: Shashank Babu Chinta Venkata <sbchin@codeaurora.org>