| commit | 2e523e98bb593950de2c749d4ceb45cc20313c1a | [log] [tgz] |
|---|---|---|
| author | Ville Syrjälä <ville.syrjala@linux.intel.com> | Fri Apr 10 18:21:27 2015 +0300 |
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | Fri May 08 15:55:22 2015 +0200 |
| tree | 7e6263ccf6e240558843bcc88df1d09eafeeccad | |
| parent | ac935a8b6db00079e2de65cadf4c735ed8f0175b [diff] |
drm/i915: Implement chv display PHY lane stagger setup Set up the chv display PHY lane stagger registers according to "Programming Guide for 1273 CHV eDP/DP/HDMI Display PHY" v1.04 Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Deepak S <deepak.s@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>