| commit | 712424fd95134bf88d27f3885389fe6ab13f34ac | [log] [tgz] |
|---|---|---|
| author | Lennert Buytenhek <buytenh@wantstofly.org> | Fri Feb 20 02:31:58 2009 +0100 |
| committer | Nicolas Pitre <nico@cam.org> | Thu Feb 19 22:41:37 2009 -0500 |
| tree | 8b146e05b2f2810bddd1c55f30764a690a534a7f | |
| parent | cfdeb6376e439c58c2d37de492d2a8c763621022 [diff] |
[ARM] mv78xx0: force eth2/eth3 to PHYless mode on pre-A0 silicon On pre-A0 revisions of the mv78xx0 SoC, the third and fourth ethernet interface are not brought out to pins, but are internally cross-connected, so if we run on pre-A0 silicon, we'll force eth2 and eth3 to PHYless mode. Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>