drm/msm/sde: check both the rect's of sDMA before enabling UBWC const alpha
Both the rectangles of a sDMA 2.0 HW pipe share the same UBWC static
control register where constant alpha bit will be set. This change
checks both rectangle eligibility before setting the bit.
Change-Id: I48e504387c4ebc0b6bdc06205f8ac3b7c0294cb7
Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
diff --git a/drivers/gpu/drm/msm/sde/sde_hw_sspp.c b/drivers/gpu/drm/msm/sde/sde_hw_sspp.c
index e7aa6ea..0d85c53 100644
--- a/drivers/gpu/drm/msm/sde/sde_hw_sspp.c
+++ b/drivers/gpu/drm/msm/sde/sde_hw_sspp.c
@@ -260,13 +260,13 @@
*/
static void sde_hw_sspp_setup_format(struct sde_hw_pipe *ctx,
const struct sde_format *fmt,
- bool blend_enabled, u32 flags,
+ bool const_alpha_en, u32 flags,
enum sde_sspp_multirect_index rect_mode)
{
struct sde_hw_blk_reg_map *c;
u32 chroma_samp, unpack, src_format;
u32 opmode = 0;
- u32 fast_clear = 0;
+ u32 alpha_en_mask = 0;
u32 op_mode_off, unpack_pat_off, format_off;
u32 idx;
@@ -329,11 +329,10 @@
SDE_FETCH_CONFIG_RESET_VALUE |
ctx->mdp->highest_bank_bit << 18);
if (IS_UBWC_20_SUPPORTED(ctx->catalog->ubwc_version)) {
- fast_clear = (fmt->alpha_enable && blend_enabled) ?
- BIT(31) : 0;
+ alpha_en_mask = const_alpha_en ? BIT(31) : 0;
SDE_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL,
- fast_clear | (ctx->mdp->ubwc_swizzle) |
- (ctx->mdp->highest_bank_bit << 4));
+ alpha_en_mask | (ctx->mdp->ubwc_swizzle) |
+ (ctx->mdp->highest_bank_bit << 4));
}
}
diff --git a/drivers/gpu/drm/msm/sde/sde_plane.c b/drivers/gpu/drm/msm/sde/sde_plane.c
index 9f27286..b0ba72e 100644
--- a/drivers/gpu/drm/msm/sde/sde_plane.c
+++ b/drivers/gpu/drm/msm/sde/sde_plane.c
@@ -2810,6 +2810,7 @@
bool parallel_fetch_qualified = true;
enum sde_sspp_multirect_mode mode = SDE_SSPP_MULTIRECT_NONE;
const struct msm_format *msm_fmt;
+ bool const_alpha_enable = true;
for (i = 0; i < R_MAX; i++) {
drm_state[i] = i ? plane->r1 : plane->r0;
@@ -2877,6 +2878,10 @@
if (sde_plane[i]->is_virtual)
mode = sde_plane_get_property(pstate[i],
PLANE_PROP_MULTIRECT_MODE);
+
+ if (pstate[i]->const_alpha_en != const_alpha_enable)
+ const_alpha_enable = false;
+
}
buffer_lines = 2 * max_tile_height;
@@ -2936,8 +2941,10 @@
break;
}
- for (i = 0; i < R_MAX; i++)
+ for (i = 0; i < R_MAX; i++) {
pstate[i]->multirect_mode = mode;
+ pstate[i]->const_alpha_en = const_alpha_enable;
+ }
if (mode == SDE_SSPP_MULTIRECT_NONE)
return -EINVAL;
@@ -3541,6 +3548,10 @@
pstate->excl_rect.w, pstate->excl_rect.h);
}
+ pstate->const_alpha_en = fmt->alpha_enable &&
+ (SDE_DRM_BLEND_OP_OPAQUE !=
+ sde_plane_get_property(pstate, PLANE_PROP_BLEND_OP));
+
modeset_update:
if (!ret)
_sde_plane_sspp_atomic_check_mode_changed(psde,
@@ -3638,7 +3649,6 @@
struct drm_framebuffer *fb;
struct sde_rect src, dst;
bool q16_data = true;
- bool blend_enabled = true;
int idx;
if (!plane) {
@@ -3876,12 +3886,9 @@
if (rstate->out_rotation & DRM_REFLECT_Y)
src_flags |= SDE_SSPP_FLIP_UD;
- blend_enabled = (SDE_DRM_BLEND_OP_OPAQUE !=
- sde_plane_get_property(pstate, PLANE_PROP_BLEND_OP));
-
/* update format */
psde->pipe_hw->ops.setup_format(psde->pipe_hw, fmt,
- blend_enabled, src_flags,
+ pstate->const_alpha_en, src_flags,
pstate->multirect_index);
if (psde->pipe_hw->ops.setup_cdp) {
diff --git a/drivers/gpu/drm/msm/sde/sde_plane.h b/drivers/gpu/drm/msm/sde/sde_plane.h
index d1eb399..e8b621c 100644
--- a/drivers/gpu/drm/msm/sde/sde_plane.h
+++ b/drivers/gpu/drm/msm/sde/sde_plane.h
@@ -128,6 +128,7 @@
* @dirty: bitmask for which pipe h/w config functions need to be updated
* @multirect_index: index of the rectangle of SSPP
* @multirect_mode: parallel or time multiplex multirect mode
+ * @const_alpha_en: const alpha channel is enabled for this HW pipe
* @pending: whether the current update is still pending
* @defer_prepare_fb: indicate if prepare_fb call was deferred
* @scaler3_cfg: configuration data for scaler3
@@ -146,6 +147,7 @@
uint32_t dirty;
uint32_t multirect_index;
uint32_t multirect_mode;
+ bool const_alpha_en;
bool pending;
bool defer_prepare_fb;