drm/msm/sde: check both the rect's of sDMA before enabling UBWC const alpha
Both the rectangles of a sDMA 2.0 HW pipe share the same UBWC static
control register where constant alpha bit will be set. This change
checks both rectangle eligibility before setting the bit.
Change-Id: I48e504387c4ebc0b6bdc06205f8ac3b7c0294cb7
Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
diff --git a/drivers/gpu/drm/msm/sde/sde_plane.h b/drivers/gpu/drm/msm/sde/sde_plane.h
index d1eb399..e8b621c 100644
--- a/drivers/gpu/drm/msm/sde/sde_plane.h
+++ b/drivers/gpu/drm/msm/sde/sde_plane.h
@@ -128,6 +128,7 @@
* @dirty: bitmask for which pipe h/w config functions need to be updated
* @multirect_index: index of the rectangle of SSPP
* @multirect_mode: parallel or time multiplex multirect mode
+ * @const_alpha_en: const alpha channel is enabled for this HW pipe
* @pending: whether the current update is still pending
* @defer_prepare_fb: indicate if prepare_fb call was deferred
* @scaler3_cfg: configuration data for scaler3
@@ -146,6 +147,7 @@
uint32_t dirty;
uint32_t multirect_index;
uint32_t multirect_mode;
+ bool const_alpha_en;
bool pending;
bool defer_prepare_fb;