| commit | b987c4b2c9c9db2393f4c089e63d1734301214e5 | [log] [tgz] |
|---|---|---|
| author | Sekhar Nori <nsekhar@ti.com> | Tue Jul 20 16:46:51 2010 +0530 |
| committer | Kevin Hilman <khilman@deeprootsystems.com> | Fri Sep 24 07:40:25 2010 -0700 |
| tree | 446b9ae602d8669e9e03107b976c9a88040b84ca | |
| parent | 30a2c5d2f0134df6175af26ce554aacaee304280 [diff] |
davinci: am18x/da850/omap-l138: keep async clock constant with cpufreq Keep PLL0 SYSCLK3 at a constant rate of 100MHz. This enables the AEMIF timing to remain valid even as the PLL0 output is changed by cpufreq driver to save power. Signed-off-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>