arch/arm64/boot/dts/qcom/sdm429.dtsi

/*
 * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 and
 * only version 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */
#include "sdm439.dtsi"
#include "sdm429-cpu.dtsi"

/ {
	model = "Qualcomm Technologies, Inc. SDM429";
	compatible = "qcom,sdm429";
	qcom,msm-id = <354 0x0>;
};

&soc {
	/delete-node/ etm@619c000;
	/delete-node/ etm@619d000;
	/delete-node/ etm@619e000;
	/delete-node/ etm@619f000;
	/delete-node/ cti@6198000;
	/delete-node/ cti@6199000;
	/delete-node/ cti@619a000;
	/delete-node/ cti@619b000;
	/delete-node/ jtagmm@619c000;
	/delete-node/ jtagmm@619d000;
	/delete-node/ jtagmm@619e000;
	/delete-node/ jtagmm@619f000;

	qcom,spm@b1d2000 {
		qcom,cpu-vctl-list = <&CPU0 &CPU1 &CPU2 &CPU3>;
	};

	qcom,lpm-levels {
		qcom,pm-cluster@0 {
			/delete-node/qcom,pm-cluster@1;
		};
	};

	/delete-node/ qcom,msm-cpufreq;
	msm_cpufreq: qcom,msm-cpufreq {
		compatible = "qcom,msm-cpufreq";
		clock-names =
			"l2_clk",
			"cpu0_clk";
		clocks = <&clock_cpu clk_cci_clk>,
			 <&clock_cpu clk_a53_bc_clk>;

		qcom,governor-per-policy;

		qcom,cpufreq-table =
			 <  960000 >,
			 < 1305600 >,
			 < 1497600 >,
			 < 1708800 >,
			 < 1804800 >,
			 < 1958400 >,
			 < 2016000 >;
	};

	/delete-node/ devfreq-cpufreq;
	devfreq-cpufreq {
		cpubw-cpufreq {
		target-dev = <&cpubw>;
		cpu-to-dev-map =
			<  960000  2929 >,
			< 1305600  5053 >,
			< 1497600  5712 >,
			< 1708800  6445 >,
			< 1804800  7104 >,
			< 1958400  7104 >,
			< 2016000  7104 >;
		};

		cci-cpufreq {
		target-dev = <&cci_cache>;
		cpu-to-dev-map =
			<  960000  400000 >,
			< 1305600  400000 >,
			< 1497600  400000 >,
			< 1708800  533000 >,
			< 1804800  576000 >,
			< 1958400  576000 >,
			< 2016000  576000 >;
		};

		mincpubw-cpufreq {
			target-dev = <&mincpubw>;
			cpu-to-dev-map =
				< 1305600 2929 >,
				< 1804800 5712 >;
		};
	};
};

&funnel_apss {
	ports {
		/delete-node/ port@1;
		/delete-node/ port@2;
		/delete-node/ port@3;
		/delete-node/ port@4;
	};
};

&thermal_zones {
	hexa-cpu-max-step {
		cooling-maps {
			/delete-node/ cpu4_cdev;
			/delete-node/ cpu5_cdev;
			/delete-node/ cpu6_cdev;
			/delete-node/ cpu7_cdev;
		};
	};

	/delete-node/ cpuss0-step;

	quiet-therm-step {
		cooling-maps {
			/delete-node/ skin_cpu4;
			/delete-node/ skin_cpu5;
			/delete-node/ skin_cpu6;
			/delete-node/ skin_cpu7;
		};
	};
};

&clock_gcc {
	compatible = "qcom,gcc-sdm429";
	reg = <0x1800000 0x80000>,
		<0xb016000 0x00040>;
	reg-names = "cc_base", "apcs_c1_base";
	vdd_dig-supply = <&pm8953_s2_level>;
	vdd_hf_dig-supply = <&pm8953_s2_level_ao>;
	vdd_hf_pll-supply = <&pm8953_l7_ao>;
};

&clock_debug {
	compatible = "qcom,cc-debug-8917";
	reg = <0x1874000 0x4>,
		<0xb01101c 0x8>;
	reg-names = "cc_base", "meas";
	#clock-cells = <1>;
};

&soc {
	devfreq_spdm_cpu {
		status = "disabled";
	};

	devfreq_spdm_gov {
		status = "disabled";
	};
};

&soc {
	/delete-node/ qcom,cpu-clock-8939@b111050;
	clock_cpu: qcom,cpu-clock-8939@b111050 {
		compatible = "qcom,cpu-clock-sdm429";

		reg =   <0xb011050 0x8>,
			<0xb1d1050 0x8>,
			<0x00a412c 0x8>;
		reg-names = "apcs-c1-rcg-base",
			"apcs-cci-rcg-base", "efuse";

		qcom,num-cluster;
		vdd-c1-supply = <&apc_vreg_corner>;
		vdd-cci-supply = <&apc_vreg_corner>;

		clocks = <&clock_gcc clk_gpll0_ao_clk_src>,
			<&clock_gcc clk_a53ss_c1_pll>,
			<&clock_gcc clk_gpll0_ao_clk_src>,
			<&clock_gcc clk_gpll0_ao_clk_src>;
		clock-names = "clk-c1-4", "clk-c1-5",
				"clk-cci-4", "clk-cci-2";

		qcom,speed0-bin-v0-c1 =
			<          0 0>,
			<  960000000 1>,
			< 1305600000 1>,
			< 1497600000 2>,
			< 1708800000 3>,
			< 1958400000 5>;

		qcom,speed0-bin-v0-cci =
			<          0 0>,
			<  400000000 1>,
			<  533333333 3>;

		qcom,speed1-bin-v0-c1 =
			<          0 0>,
			<  960000000 1>,
			< 1305600000 1>,
			< 1497600000 2>,
			< 1708800000 3>,
			< 1804800000 5>;

		qcom,speed1-bin-v0-cci =
			<          0 0>,
			<  400000000 1>,
			<  533333333 3>;

		qcom,speed4-bin-v0-c1 =
			<          0 0>,
			<  960000000 1>,
			< 1305600000 1>,
			< 1497600000 2>,
			< 1708800000 3>,
			< 1958400000 5>,
			< 2016000000 6>;

		qcom,speed4-bin-v0-cci =
			<          0 0>,
			<  400000000 1>,
			<  533333333 3>;

		qcom,speed5-bin-v0-c1 =
			<          0 0>,
			<  960000000 1>,
			< 1305600000 1>,
			< 1497600000 2>,
			< 1708800000 3>;

		qcom,speed5-bin-v0-cci =
			<          0 0>,
			<  400000000 1>,
			<  533333333 3>;

		#clock-cells = <1>;
	};

	/* Disable secure_mem node */
	qcom,ion {
		/delete-node/ qcom,ion-heap@8;
	};
	/* delete hypervisor node for GPU*/
	/delete-node/ qcom,kgsl-hyp;
};

&secure_mem {
	status = "disabled";
};

&qseecom_ta_mem {
	size = <0 0x400000>;
};

&clock_gcc_mdss {
	compatible = "qcom,gcc-mdss-sdm429";
	clocks = <&mdss_dsi0_pll clk_dsi0pll_pixel_clk_src>,
		 <&mdss_dsi0_pll clk_dsi0pll_byte_clk_src>,
		 <&mdss_dsi1_pll clk_dsi1pll_pixel_clk_src>,
		 <&mdss_dsi1_pll clk_dsi1pll_byte_clk_src>;
	clock-names = "pclk0_src", "byte0_src", "pclk1_src",
		"byte1_src";
	#clock-cells = <1>;
};

/* GPU overrides */
&msm_gpu {
	/* Update GPU chip ID*/
	qcom,chipid = <0x05000400>;

	/* disable mem pools */
	/delete-node/qcom,gpu-mempools;
};

/* Disable secure context for Graphics*/
&kgsl_msm_iommu {
	/delete-node/ gfx3d_secure;
};