tree 80fb28570b7cf060188bdad013f0aa58b4a25fb0
parent 124764f17473479061942429ada2e5e786d5d6ed
author Michel Dänzer <michel.daenzer@amd.com> 1406799829 +0900
committer Alex Deucher <alexander.deucher@amd.com> 1407243225 -0400

drm/radeon: Always flush the HDP cache before submitting a CS to the GPU

This ensures the GPU sees all previous CPU writes to VRAM, which makes it
safe:

* For userspace to stream data from CPU to GPU via VRAM instead of GTT
* For IBs to be stored in VRAM instead of GTT
* For ring buffers to be stored in VRAM instead of GTT, if the HPD flush
  is performed via MMIO

Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>