| commit | 73acc7df534ff458a81435178dab3ea037ed6d78 | [log] [tgz] |
|---|---|---|
| author | Ralf Baechle <ralf@linux-mips.org> | Thu Jun 20 14:56:17 2013 +0200 |
| committer | Ralf Baechle <ralf@linux-mips.org> | Fri Jun 21 18:07:03 2013 +0200 |
| tree | 7e6f7c7af7ccbeb81224eb88bc17d498fa529290 | |
| parent | b90b3802624e1f2a509f3e9f39775d94ec4762d7 [diff] |
MIPS: Fix TLBR-use hazards for R2 cores in the TLB reload handlers MIPS R2 documents state that an execution hazard barrier is needed after a TLBR before reading EntryLo. Original patch by Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>. Signed-off-by: Ralf Baechle <ralf@linux-mips.org> Patchwork: https://patchwork.linux-mips.org/patch/5526/