| commit | 74a4dd2e4594804ffeb04b3e60ff4cfbf6b8ce10 | [log] [tgz] |
|---|---|---|
| author | Vijay Purushothaman <vijay.a.purushothaman@intel.com> | Thu Sep 27 19:13:04 2012 +0530 |
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | Fri Sep 28 16:49:53 2012 +0200 |
| tree | 5b15df8a3458116a8111f4913d8eb4a9826e8078 | |
| parent | b56747aace48a269fefa7d337963cbae6e95b0a0 [diff] |
drm/i915: Program correct m n tu register for Valleyview m n tu register offset has changed in Valleyview. Also fixed DP limit frequencies. Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@intel.com> Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com> Acked-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>