msm: ep_pcie: add the support for sdxpoorwills in PCIe EP driver
Update the PCIe endpoint driver to support sdxpoorwills.
Change-Id: Idb38ee61fe17eef223c6074225874c7360b94d00
Signed-off-by: Yan He <yanhe@codeaurora.org>
diff --git a/drivers/platform/msm/ep_pcie/ep_pcie_com.h b/drivers/platform/msm/ep_pcie/ep_pcie_com.h
index 1b56a40..00ca8dc4 100644
--- a/drivers/platform/msm/ep_pcie/ep_pcie_com.h
+++ b/drivers/platform/msm/ep_pcie/ep_pcie_com.h
@@ -53,6 +53,8 @@
#define PCIE20_PARF_DBI_BASE_ADDR_HI 0x354
#define PCIE20_PARF_SLV_ADDR_SPACE_SIZE 0x358
#define PCIE20_PARF_SLV_ADDR_SPACE_SIZE_HI 0x35C
+#define PCIE20_PARF_ATU_BASE_ADDR 0x634
+#define PCIE20_PARF_ATU_BASE_ADDR_HI 0x638
#define PCIE20_PARF_DEVICE_TYPE 0x1000
#define PCIE20_ELBI_VERSION 0x00
@@ -147,7 +149,7 @@
#define EP_PCIE_LOG_PAGES 50
#define EP_PCIE_MAX_VREG 2
-#define EP_PCIE_MAX_CLK 5
+#define EP_PCIE_MAX_CLK 7
#define EP_PCIE_MAX_PIPE_CLK 1
#define EP_PCIE_MAX_RESET 2
diff --git a/drivers/platform/msm/ep_pcie/ep_pcie_core.c b/drivers/platform/msm/ep_pcie/ep_pcie_core.c
index 4f915d7..055f026 100644
--- a/drivers/platform/msm/ep_pcie/ep_pcie_core.c
+++ b/drivers/platform/msm/ep_pcie/ep_pcie_core.c
@@ -68,6 +68,8 @@
{NULL, "pcie_0_slv_axi_clk", 0, true},
{NULL, "pcie_0_aux_clk", 1000000, true},
{NULL, "pcie_0_ldo", 0, true},
+ {NULL, "pcie_0_sleep_clk", 0, false},
+ {NULL, "pcie_0_slv_q2a_axi_clk", 0, false},
};
static struct ep_pcie_clk_info_t
@@ -82,13 +84,13 @@
};
static const struct ep_pcie_res_info_t ep_pcie_res_info[EP_PCIE_MAX_RES] = {
- {"parf", 0, 0},
- {"phy", 0, 0},
- {"mmio", 0, 0},
- {"msi", 0, 0},
- {"dm_core", 0, 0},
- {"elbi", 0, 0},
- {"iatu", 0, 0},
+ {"parf", NULL, NULL},
+ {"phy", NULL, NULL},
+ {"mmio", NULL, NULL},
+ {"msi", NULL, NULL},
+ {"dm_core", NULL, NULL},
+ {"elbi", NULL, NULL},
+ {"iatu", NULL, NULL},
};
static const struct ep_pcie_irq_info_t ep_pcie_irq_info[EP_PCIE_MAX_IRQ] = {
@@ -319,8 +321,8 @@
break;
}
EP_PCIE_DBG(dev,
- "PCIe V%d: set rate for clk %s.\n",
- dev->rev, info->name);
+ "PCIe V%d: set rate %d for clk %s.\n",
+ dev->rev, info->freq, info->name);
}
rc = clk_prepare_enable(info->hdl);
@@ -529,6 +531,47 @@
0xf, dev->link_speed);
}
+ if (dev->active_config) {
+ struct resource *dbi = dev->res[EP_PCIE_RES_DM_CORE].resource;
+ u32 dbi_lo = dbi->start;
+
+ EP_PCIE_DBG2(dev, "PCIe V%d: Enable L1.\n", dev->rev);
+ ep_pcie_write_mask(dev->parf + PCIE20_PARF_PM_CTRL, BIT(5), 0);
+
+ ep_pcie_write_mask(dev->parf + PCIE20_PARF_SLV_ADDR_MSB_CTRL,
+ 0, BIT(0));
+ ep_pcie_write_reg(dev->parf, PCIE20_PARF_SLV_ADDR_SPACE_SIZE_HI,
+ 0x200);
+ ep_pcie_write_reg(dev->parf, PCIE20_PARF_SLV_ADDR_SPACE_SIZE,
+ 0x0);
+ ep_pcie_write_reg(dev->parf, PCIE20_PARF_DBI_BASE_ADDR_HI,
+ 0x100);
+ ep_pcie_write_reg(dev->parf, PCIE20_PARF_DBI_BASE_ADDR,
+ dbi_lo);
+
+ EP_PCIE_DBG(dev,
+ "PCIe V%d: DBI base:0x%x.\n", dev->rev,
+ readl_relaxed(dev->parf + PCIE20_PARF_DBI_BASE_ADDR));
+
+ if (dev->phy_rev >= 6) {
+ struct resource *atu =
+ dev->res[EP_PCIE_RES_IATU].resource;
+ u32 atu_lo = atu->start;
+
+ EP_PCIE_DBG(dev,
+ "PCIe V%d: configure MSB of ATU base for flipping and LSB as 0x%x.\n",
+ dev->rev, atu_lo);
+ ep_pcie_write_reg(dev->parf,
+ PCIE20_PARF_ATU_BASE_ADDR_HI, 0x100);
+ ep_pcie_write_reg(dev->parf, PCIE20_PARF_ATU_BASE_ADDR,
+ atu_lo);
+ EP_PCIE_DBG(dev,
+ "PCIe V%d: LSB of ATU base:0x%x.\n",
+ dev->rev, readl_relaxed(dev->parf
+ + PCIE20_PARF_ATU_BASE_ADDR));
+ }
+ }
+
/* Read halts write */
ep_pcie_write_mask(dev->parf + PCIE20_PARF_AXI_MSTR_RD_HALT_NO_WRITES,
0, BIT(0));
@@ -647,13 +690,6 @@
dev->rev,
readl_relaxed(dev->parf + PCIE20_PARF_INT_ALL_MASK));
}
-
- if (dev->active_config) {
- ep_pcie_write_reg(dev->dm_core, PCIE20_AUX_CLK_FREQ_REG, 0x14);
-
- EP_PCIE_DBG2(dev, "PCIe V%d: Enable L1.\n", dev->rev);
- ep_pcie_write_mask(dev->parf + PCIE20_PARF_PM_CTRL, BIT(5), 0);
- }
}
static void ep_pcie_config_inbound_iatu(struct ep_pcie_dev_t *dev)
@@ -877,12 +913,10 @@
ret = of_property_read_u32_array(
(&pdev->dev)->of_node,
"max-clock-frequency-hz", clkfreq, cnt);
- if (ret) {
- EP_PCIE_ERR(dev,
- "PCIe V%d: invalid max-clock-frequency-hz property:%d\n",
+ if (ret)
+ EP_PCIE_DBG2(dev,
+ "PCIe V%d: cannot get max-clock-frequency-hz property from DT:%d\n",
dev->rev, ret);
- goto out;
- }
}
for (i = 0; i < EP_PCIE_MAX_VREG; i++) {
@@ -1385,18 +1419,8 @@
}
checkbme:
- if (dev->active_config) {
- ep_pcie_write_mask(dev->parf + PCIE20_PARF_SLV_ADDR_MSB_CTRL,
- 0, BIT(0));
- ep_pcie_write_reg(dev->parf, PCIE20_PARF_SLV_ADDR_SPACE_SIZE_HI,
- 0x200);
- ep_pcie_write_reg(dev->parf, PCIE20_PARF_SLV_ADDR_SPACE_SIZE,
- 0x0);
- ep_pcie_write_reg(dev->parf, PCIE20_PARF_DBI_BASE_ADDR_HI,
- 0x100);
- ep_pcie_write_reg(dev->parf, PCIE20_PARF_DBI_BASE_ADDR,
- 0x7FFFE000);
- }
+ if (dev->active_config)
+ ep_pcie_write_reg(dev->dm_core, PCIE20_AUX_CLK_FREQ_REG, 0x14);
if (!(opt & EP_PCIE_OPT_ENUM_ASYNC)) {
/* Wait for up to 1000ms for BME to be set */
diff --git a/drivers/platform/msm/ep_pcie/ep_pcie_phy.c b/drivers/platform/msm/ep_pcie/ep_pcie_phy.c
index 776ef08..f813bb9 100644
--- a/drivers/platform/msm/ep_pcie/ep_pcie_phy.c
+++ b/drivers/platform/msm/ep_pcie/ep_pcie_phy.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2015-2017, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -35,6 +35,11 @@
"PCIe V%d: PHY V%d: Initializing 10nm QMP phy - 100MHz\n",
dev->rev, dev->phy_rev);
break;
+ case 6:
+ EP_PCIE_DBG(dev,
+ "PCIe V%d: PHY V%d: Initializing 7nm QMP phy - 100MHz\n",
+ dev->rev, dev->phy_rev);
+ break;
default:
EP_PCIE_ERR(dev,
"PCIe V%d: Unexpected phy version %d is caught!\n",