[MIPS] Fix pipeline hazard.
In the the sequence:
ei
..
mfc0 $x, $status
the mfc0 may not see the SR_IE bit set. This was a deliberate bug in the
kernel code because we knew this was a safe thing to do on all R2 silicon
so far but new silicon is changing this.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
diff --git a/include/asm-mips/hazards.h b/include/asm-mips/hazards.h
index 5007315..e50c77e 100644
--- a/include/asm-mips/hazards.h
+++ b/include/asm-mips/hazards.h
@@ -52,6 +52,7 @@
_ehb
)
ASMMACRO(irq_enable_hazard,
+ _ehb
)
ASMMACRO(irq_disable_hazard,
_ehb