tree f28d7b59ee88fac428a96e2e321727de42b2185b
parent 921f168109d029e3b59459c3a2754f0e2a70fad3
author Dong Aisheng <b29396@freescale.com> 1414579524 +0800
committer Marc Kleine-Budde <mkl@pengutronix.de> 1416342905 +0100

can: m_can: add missing delay after setting CCCR_INIT bit

The spec mentions there may be a delay until the value written to INIT can be
read back due to the synchronization mechanism between the two clock domains.
But it does not indicate the exact clock cycles needed. The 5us delay is a
test value and seems ok.

Without the delay, CCCR.CCE bit may fail to be set and then the initialization
fail sometimes when do repeatly up and down.

Signed-off-by: Dong Aisheng <b29396@freescale.com>
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>