ARM: OMAP2+: Fix warnings for GPMC interrupt
Commit db97eb7dfe13f6c04f0a0e77c32e2691f563ab8b
(omap: gpmc: enable irq mode in gpmc) enabled interrupts for
GPMC (General Purpose Memory Controller). However, looks like
this patch only works on omap3. Fix the issues to avoid warnings
on omap4 during the boot.
GPMC: number of chip select is 8, CS0 to CS7. One less IRQ
allocated throws below warning at boot:
[ 0.429290] Trying to install type control for IRQ409
[ 0.429290] Trying to set irq flags for IRQ409
Resolve following warning messages in boot when irq chip is not set:
[ 0.429229] Trying to install interrupt handler for IRQ402
[ 0.429229] Trying to install interrupt handler for IRQ403
[ 0.429229] Trying to install interrupt handler for IRQ404
[ 0.429260] Trying to install interrupt handler for IRQ405
[ 0.429260] Trying to install interrupt handler for IRQ406
[ 0.429260] Trying to install interrupt handler for IRQ407
[ 0.429290] Trying to install interrupt handler for IRQ408
Resolve following warning in OMAP4:
[ 0.429290] gpmc: irq-20 could not claim: err -22
Signed-off-by: Balaji T K <balajitk@ti.com>
[tony@atomide.com: combined patches into one, updated comments]
Signed-off-by: Tony Lindgren <tony@atomide.com>
diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c
index 6741743..493505c 100644
--- a/arch/arm/mach-omap2/gpmc.c
+++ b/arch/arm/mach-omap2/gpmc.c
@@ -693,6 +693,7 @@
{
u32 l, irq;
int cs, ret = -EINVAL;
+ int gpmc_irq;
char *ck = NULL;
if (cpu_is_omap24xx()) {
@@ -701,12 +702,15 @@
l = OMAP2420_GPMC_BASE;
else
l = OMAP34XX_GPMC_BASE;
+ gpmc_irq = INT_34XX_GPMC_IRQ;
} else if (cpu_is_omap34xx()) {
ck = "gpmc_fck";
l = OMAP34XX_GPMC_BASE;
+ gpmc_irq = INT_34XX_GPMC_IRQ;
} else if (cpu_is_omap44xx()) {
ck = "gpmc_ck";
l = OMAP44XX_GPMC_BASE;
+ gpmc_irq = OMAP44XX_IRQ_GPMC;
}
if (WARN_ON(!ck))
@@ -739,16 +743,17 @@
/* initalize the irq_chained */
irq = OMAP_GPMC_IRQ_BASE;
for (cs = 0; cs < GPMC_CS_NUM; cs++) {
- set_irq_handler(irq, handle_simple_irq);
+ set_irq_chip_and_handler(irq, &dummy_irq_chip,
+ handle_simple_irq);
set_irq_flags(irq, IRQF_VALID);
irq++;
}
- ret = request_irq(INT_34XX_GPMC_IRQ,
+ ret = request_irq(gpmc_irq,
gpmc_handle_irq, IRQF_SHARED, "gpmc", gpmc_base);
if (ret)
pr_err("gpmc: irq-%d could not claim: err %d\n",
- INT_34XX_GPMC_IRQ, ret);
+ gpmc_irq, ret);
return ret;
}
postcore_initcall(gpmc_init);
@@ -757,8 +762,6 @@
{
u8 cs;
- if (irq != INT_34XX_GPMC_IRQ)
- return IRQ_HANDLED;
/* check cs to invoke the irq */
cs = ((gpmc_read_reg(GPMC_PREFETCH_CONFIG1)) >> CS_NUM_SHIFT) & 0x7;
if (OMAP_GPMC_IRQ_BASE+cs <= OMAP_GPMC_IRQ_END)