drm/msm/dsi-staging: add support for checking panel status
Panel health status can be read back from panel using DCS read
mechanism. This change adds support for the same along with
fixing various HW configuration issues related with read back
from MIPI peripherals.
Change-Id: I129f5c564dd4e4acda56031dc2f985267ee1a590
Signed-off-by: Sandeep Panda <spanda@codeaurora.org>
diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_catalog.c b/drivers/gpu/drm/msm/dsi-staging/dsi_catalog.c
index 38a6e47..5d9d21f 100644
--- a/drivers/gpu/drm/msm/dsi-staging/dsi_catalog.c
+++ b/drivers/gpu/drm/msm/dsi-staging/dsi_catalog.c
@@ -60,6 +60,8 @@
ctrl->ops.setup_misr = dsi_ctrl_hw_cmn_setup_misr;
ctrl->ops.collect_misr = dsi_ctrl_hw_cmn_collect_misr;
ctrl->ops.debug_bus = dsi_ctrl_hw_cmn_debug_bus;
+ ctrl->ops.get_cmd_read_data = dsi_ctrl_hw_cmn_get_cmd_read_data;
+ ctrl->ops.clear_rdbk_register = dsi_ctrl_hw_cmn_clear_rdbk_reg;
switch (version) {
case DSI_CTRL_VERSION_1_4:
diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_catalog.h b/drivers/gpu/drm/msm/dsi-staging/dsi_catalog.h
index 84448ec..186a5b5 100644
--- a/drivers/gpu/drm/msm/dsi-staging/dsi_catalog.h
+++ b/drivers/gpu/drm/msm/dsi-staging/dsi_catalog.h
@@ -170,6 +170,12 @@
bool enable);
void dsi_ctrl_hw_22_phy_reset_config(struct dsi_ctrl_hw *ctrl,
bool enable);
+u32 dsi_ctrl_hw_cmn_get_cmd_read_data(struct dsi_ctrl_hw *ctrl,
+ u8 *rd_buf,
+ u32 read_offset,
+ u32 rx_byte,
+ u32 pkt_size, u32 *hw_read_cnt);
+void dsi_ctrl_hw_cmn_clear_rdbk_reg(struct dsi_ctrl_hw *ctrl);
/* Definitions specific to 1.4 DSI controller hardware */
int dsi_ctrl_hw_14_wait_for_lane_idle(struct dsi_ctrl_hw *ctrl, u32 lanes);
diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_ctrl.c b/drivers/gpu/drm/msm/dsi-staging/dsi_ctrl.c
index 4be5069..43ab5a4 100644
--- a/drivers/gpu/drm/msm/dsi-staging/dsi_ctrl.c
+++ b/drivers/gpu/drm/msm/dsi-staging/dsi_ctrl.c
@@ -884,6 +884,11 @@
buf[3] |= BIT(6);
buf[3] |= BIT(7);
+
+ /* send embedded BTA for read commands */
+ if ((buf[2] & 0x3f) == MIPI_DSI_DCS_READ)
+ buf[3] |= BIT(5);
+
*buffer = buf;
*size = len;
@@ -1026,6 +1031,7 @@
{
int rc = 0;
u8 tx[2] = { (u8)(size & 0xFF), (u8)(size >> 8) };
+ u32 flags = DSI_CTRL_CMD_FETCH_MEMORY;
struct mipi_dsi_msg msg = {
.channel = rx_msg->channel,
.type = MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE,
@@ -1033,24 +1039,77 @@
.tx_buf = tx,
};
- rc = dsi_message_tx(dsi_ctrl, &msg, 0x0);
+ rc = dsi_message_tx(dsi_ctrl, &msg, flags);
if (rc)
pr_err("failed to send max return size packet, rc=%d\n", rc);
return rc;
}
+/* Helper functions to support DCS read operation */
+static int dsi_parse_short_read1_resp(const struct mipi_dsi_msg *msg,
+ unsigned char *buff)
+{
+ u8 *data = msg->rx_buf;
+ int read_len = 1;
+
+ if (!data)
+ return 0;
+
+ /* remove dcs type */
+ if (msg->rx_len >= 1)
+ data[0] = buff[1];
+ else
+ read_len = 0;
+
+ return read_len;
+}
+
+static int dsi_parse_short_read2_resp(const struct mipi_dsi_msg *msg,
+ unsigned char *buff)
+{
+ u8 *data = msg->rx_buf;
+ int read_len = 2;
+
+ if (!data)
+ return 0;
+
+ /* remove dcs type */
+ if (msg->rx_len >= 2) {
+ data[0] = buff[1];
+ data[1] = buff[2];
+ } else {
+ read_len = 0;
+ }
+
+ return read_len;
+}
+
+static int dsi_parse_long_read_resp(const struct mipi_dsi_msg *msg,
+ unsigned char *buff)
+{
+ if (!msg->rx_buf)
+ return 0;
+
+ /* remove dcs type */
+ if (msg->rx_buf && msg->rx_len)
+ memcpy(msg->rx_buf, buff + 4, msg->rx_len);
+
+ return msg->rx_len;
+}
+
static int dsi_message_rx(struct dsi_ctrl *dsi_ctrl,
const struct mipi_dsi_msg *msg,
u32 flags)
{
int rc = 0;
- u32 rd_pkt_size;
- u32 total_read_len;
- u32 bytes_read = 0, tot_bytes_read = 0;
- u32 current_read_len;
+ u32 rd_pkt_size, total_read_len, hw_read_cnt;
+ u32 current_read_len = 0, total_bytes_read = 0;
bool short_resp = false;
bool read_done = false;
+ u32 dlen, diff, rlen = msg->rx_len;
+ unsigned char *buff;
+ char cmd;
if (msg->rx_len <= 2) {
short_resp = true;
@@ -1066,6 +1125,7 @@
total_read_len = current_read_len + 6;
}
+ buff = msg->rx_buf;
while (!read_done) {
rc = dsi_set_max_return_size(dsi_ctrl, msg, rd_pkt_size);
@@ -1075,24 +1135,79 @@
goto error;
}
+ /* clear RDBK_DATA registers before proceeding */
+ dsi_ctrl->hw.ops.clear_rdbk_register(&dsi_ctrl->hw);
+
rc = dsi_message_tx(dsi_ctrl, msg, flags);
if (rc) {
pr_err("Message transmission failed, rc=%d\n", rc);
goto error;
}
+ dlen = dsi_ctrl->hw.ops.get_cmd_read_data(&dsi_ctrl->hw,
+ buff, total_bytes_read,
+ total_read_len, rd_pkt_size,
+ &hw_read_cnt);
+ if (!dlen)
+ goto error;
- tot_bytes_read += bytes_read;
if (short_resp)
+ break;
+
+ if (rlen <= current_read_len) {
+ diff = current_read_len - rlen;
read_done = true;
- else if (msg->rx_len <= tot_bytes_read)
- read_done = true;
+ } else {
+ diff = 0;
+ rlen -= current_read_len;
+ }
+
+ dlen -= 2; /* 2 bytes of CRC */
+ dlen -= diff;
+ buff += dlen;
+ total_bytes_read += dlen;
+ if (!read_done) {
+ current_read_len = 14; /* Not first read */
+ if (rlen < current_read_len)
+ rd_pkt_size += rlen;
+ else
+ rd_pkt_size += current_read_len;
+ }
}
+
+ if (hw_read_cnt < 16 && !short_resp)
+ buff = msg->rx_buf + (16 - hw_read_cnt);
+ else
+ buff = msg->rx_buf;
+
+ /* parse the data read from panel */
+ cmd = buff[0];
+ switch (cmd) {
+ case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT:
+ pr_err("Rx ACK_ERROR\n");
+ rc = 0;
+ break;
+ case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE:
+ case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE:
+ rc = dsi_parse_short_read1_resp(msg, buff);
+ break;
+ case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE:
+ case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE:
+ rc = dsi_parse_short_read2_resp(msg, buff);
+ break;
+ case MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE:
+ case MIPI_DSI_RX_DCS_LONG_READ_RESPONSE:
+ rc = dsi_parse_long_read_resp(msg, buff);
+ break;
+ default:
+ pr_warn("Invalid response\n");
+ rc = 0;
+ }
+
error:
return rc;
}
-
static int dsi_enable_ulps(struct dsi_ctrl *dsi_ctrl)
{
int rc = 0;
@@ -2300,8 +2415,8 @@
if (flags & DSI_CTRL_CMD_READ) {
rc = dsi_message_rx(dsi_ctrl, msg, flags);
- if (rc)
- pr_err("read message failed, rc=%d\n", rc);
+ if (rc <= 0)
+ pr_err("read message failed read length, rc=%d\n", rc);
} else {
rc = dsi_message_tx(dsi_ctrl, msg, flags);
if (rc)
diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_ctrl_hw.h b/drivers/gpu/drm/msm/dsi-staging/dsi_ctrl_hw.h
index 57bccfb..714a450 100644
--- a/drivers/gpu/drm/msm/dsi-staging/dsi_ctrl_hw.h
+++ b/drivers/gpu/drm/msm/dsi-staging/dsi_ctrl_hw.h
@@ -520,11 +520,17 @@
* get_cmd_read_data() - get data read from the peripheral
* @ctrl: Pointer to the controller host hardware.
* @rd_buf: Buffer where data will be read into.
- * @total_read_len: Number of bytes to read.
+ * @read_offset: Offset from where to read.
+ * @rx_byte: Number of bytes to be read.
+ * @pkt_size: Size of response expected.
+ * @hw_read_cnt: Actual number of bytes read by HW.
*/
u32 (*get_cmd_read_data)(struct dsi_ctrl_hw *ctrl,
u8 *rd_buf,
- u32 total_read_len);
+ u32 read_offset,
+ u32 rx_byte,
+ u32 pkt_size,
+ u32 *hw_read_cnt);
/**
* wait_for_lane_idle() - wait for DSI lanes to go to idle state
@@ -710,6 +716,11 @@
*/
void (*set_timing_db)(struct dsi_ctrl_hw *ctrl,
bool enable);
+ /**
+ * clear_rdbk_register() - Clear and reset read back register
+ * @ctrl: Pointer to the controller host hardware.
+ */
+ void (*clear_rdbk_register)(struct dsi_ctrl_hw *ctrl);
};
/*
diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_ctrl_hw_cmn.c b/drivers/gpu/drm/msm/dsi-staging/dsi_ctrl_hw_cmn.c
index 8278ada..2959e94 100644
--- a/drivers/gpu/drm/msm/dsi-staging/dsi_ctrl_hw_cmn.c
+++ b/drivers/gpu/drm/msm/dsi-staging/dsi_ctrl_hw_cmn.c
@@ -16,6 +16,7 @@
#include <linux/delay.h>
#include <linux/iopoll.h>
+#include "dsi_catalog.h"
#include "dsi_ctrl_hw.h"
#include "dsi_ctrl_reg.h"
#include "dsi_hw.h"
@@ -709,6 +710,22 @@
}
/**
+ * clear_rdbk_reg() - clear previously read panel data.
+ * @ctrl: Pointer to the controller host hardware.
+ *
+ * This function is called before sending DSI Rx command to
+ * panel in order to clear if any stale data remaining from
+ * previous read operation.
+ */
+void dsi_ctrl_hw_cmn_clear_rdbk_reg(struct dsi_ctrl_hw *ctrl)
+{
+ DSI_W32(ctrl, DSI_RDBK_DATA_CTRL, 0x1);
+ wmb(); /* ensure read back register is reset */
+ DSI_W32(ctrl, DSI_RDBK_DATA_CTRL, 0x0);
+ wmb(); /* ensure read back register is cleared */
+}
+
+/**
* get_cmd_read_data() - get data read from the peripheral
* @ctrl: Pointer to the controller host hardware.
* @rd_buf: Buffer where data will be read into.
@@ -719,16 +736,16 @@
u32 dsi_ctrl_hw_cmn_get_cmd_read_data(struct dsi_ctrl_hw *ctrl,
u8 *rd_buf,
u32 read_offset,
- u32 total_read_len)
+ u32 rx_byte,
+ u32 pkt_size,
+ u32 *hw_read_cnt)
{
u32 *lp, *temp, data;
- int i, j = 0, cnt;
+ int i, j = 0, cnt, off;
u32 read_cnt;
- u32 rx_byte = 0;
u32 repeated_bytes = 0;
u8 reg[16] = {0};
- u32 pkt_size = 0;
- int buf_offset = read_offset;
+ bool ack_err = false;
lp = (u32 *)rd_buf;
temp = (u32 *)reg;
@@ -737,28 +754,49 @@
if (cnt > 4)
cnt = 4;
- if (rx_byte == 4)
- read_cnt = 4;
- else
- read_cnt = pkt_size + 6;
+ read_cnt = (DSI_R32(ctrl, DSI_RDBK_DATA_CTRL) >> 16);
+ ack_err = (rx_byte == 4) ? (read_cnt == 8) :
+ ((read_cnt - 4) == (pkt_size + 6));
+
+ if (ack_err)
+ read_cnt -= 4;
+ if (!read_cnt) {
+ pr_err("Panel detected error, no data read\n");
+ return 0;
+ }
if (read_cnt > 16) {
- int bytes_shifted;
+ int bytes_shifted, data_lost = 0, rem_header = 0;
- bytes_shifted = read_cnt - 16;
- repeated_bytes = buf_offset - bytes_shifted;
+ bytes_shifted = read_cnt - rx_byte;
+ if (bytes_shifted >= 4)
+ data_lost = bytes_shifted - 4; /* remove DCS header */
+ else
+ rem_header = 4 - bytes_shifted; /* remaining header */
+
+ repeated_bytes = (read_offset - 4) - data_lost + rem_header;
}
- for (i = cnt - 1; i >= 0; i--) {
- data = DSI_R32(ctrl, DSI_RDBK_DATA0 + i*4);
- *temp++ = ntohl(data);
+ off = DSI_RDBK_DATA0;
+ off += ((cnt - 1) * 4);
+
+ for (i = 0; i < cnt; i++) {
+ data = DSI_R32(ctrl, off);
+ if (!repeated_bytes)
+ *lp++ = ntohl(data);
+ else
+ *temp++ = ntohl(data);
+ off -= 4;
}
- for (i = repeated_bytes; i < 16; i++)
- rd_buf[j++] = reg[i];
+ if (repeated_bytes) {
+ for (i = repeated_bytes; i < 16; i++)
+ rd_buf[j++] = reg[i];
+ }
- pr_debug("[DSI_%d] Read %d bytes\n", ctrl->index, j);
- return j;
+ *hw_read_cnt = read_cnt;
+ pr_debug("[DSI_%d] Read %d bytes\n", ctrl->index, rx_byte);
+ return rx_byte;
}
/**
diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_display.c b/drivers/gpu/drm/msm/dsi-staging/dsi_display.c
index 117fdc1..bc2e541 100644
--- a/drivers/gpu/drm/msm/dsi-staging/dsi_display.c
+++ b/drivers/gpu/drm/msm/dsi-staging/dsi_display.c
@@ -125,6 +125,282 @@
return rc;
}
+static int dsi_display_cmd_engine_enable(struct dsi_display *display)
+{
+ int rc = 0;
+ int i;
+ struct dsi_display_ctrl *m_ctrl, *ctrl;
+
+ if (display->cmd_engine_refcount > 0) {
+ display->cmd_engine_refcount++;
+ return 0;
+ }
+
+ m_ctrl = &display->ctrl[display->cmd_master_idx];
+
+ rc = dsi_ctrl_set_cmd_engine_state(m_ctrl->ctrl, DSI_CTRL_ENGINE_ON);
+ if (rc) {
+ pr_err("[%s] failed to enable cmd engine, rc=%d\n",
+ display->name, rc);
+ goto error;
+ }
+
+ for (i = 0; i < display->ctrl_count; i++) {
+ ctrl = &display->ctrl[i];
+ if (!ctrl->ctrl || (ctrl == m_ctrl))
+ continue;
+
+ rc = dsi_ctrl_set_cmd_engine_state(ctrl->ctrl,
+ DSI_CTRL_ENGINE_ON);
+ if (rc) {
+ pr_err("[%s] failed to enable cmd engine, rc=%d\n",
+ display->name, rc);
+ goto error_disable_master;
+ }
+ }
+
+ display->cmd_engine_refcount++;
+ return rc;
+error_disable_master:
+ (void)dsi_ctrl_set_cmd_engine_state(m_ctrl->ctrl, DSI_CTRL_ENGINE_OFF);
+error:
+ return rc;
+}
+
+static int dsi_display_cmd_engine_disable(struct dsi_display *display)
+{
+ int rc = 0;
+ int i;
+ struct dsi_display_ctrl *m_ctrl, *ctrl;
+
+ if (display->cmd_engine_refcount == 0) {
+ pr_err("[%s] Invalid refcount\n", display->name);
+ return 0;
+ } else if (display->cmd_engine_refcount > 1) {
+ display->cmd_engine_refcount--;
+ return 0;
+ }
+
+ m_ctrl = &display->ctrl[display->cmd_master_idx];
+ for (i = 0; i < display->ctrl_count; i++) {
+ ctrl = &display->ctrl[i];
+ if (!ctrl->ctrl || (ctrl == m_ctrl))
+ continue;
+
+ rc = dsi_ctrl_set_cmd_engine_state(ctrl->ctrl,
+ DSI_CTRL_ENGINE_OFF);
+ if (rc)
+ pr_err("[%s] failed to enable cmd engine, rc=%d\n",
+ display->name, rc);
+ }
+
+ rc = dsi_ctrl_set_cmd_engine_state(m_ctrl->ctrl, DSI_CTRL_ENGINE_OFF);
+ if (rc) {
+ pr_err("[%s] failed to enable cmd engine, rc=%d\n",
+ display->name, rc);
+ goto error;
+ }
+
+error:
+ display->cmd_engine_refcount = 0;
+ return rc;
+}
+
+static bool dsi_display_validate_reg_read(struct dsi_panel *panel)
+{
+ int i, j = 0;
+ int len = 0, *lenp;
+ int group = 0, count = 0;
+ struct dsi_display_mode *mode;
+ struct drm_panel_esd_config *config;
+
+ if (!panel)
+ return false;
+
+ config = &(panel->esd_config);
+
+ lenp = config->status_valid_params ?: config->status_cmds_rlen;
+ mode = panel->cur_mode;
+ count = mode->priv_info->cmd_sets[DSI_CMD_SET_PANEL_STATUS].count;
+
+ for (i = 0; i < count; i++)
+ len += lenp[i];
+
+ for (i = 0; i < len; i++)
+ j += len;
+
+ for (j = 0; j < config->groups; ++j) {
+ for (i = 0; i < len; ++i) {
+ if (config->return_buf[i] !=
+ config->status_value[group + i])
+ break;
+ }
+
+ if (i == len)
+ return true;
+ group += len;
+ }
+
+ return false;
+}
+
+static int dsi_display_read_status(struct dsi_display_ctrl *ctrl,
+ struct dsi_panel *panel)
+{
+ int i, rc = 0, count = 0, start = 0, *lenp;
+ struct drm_panel_esd_config *config;
+ struct dsi_cmd_desc *cmds;
+ u32 flags = 0;
+
+ if (!panel)
+ return -EINVAL;
+
+ config = &(panel->esd_config);
+ lenp = config->status_valid_params ?: config->status_cmds_rlen;
+ count = config->status_cmd.count;
+ cmds = config->status_cmd.cmds;
+ flags = (DSI_CTRL_CMD_FETCH_MEMORY | DSI_CTRL_CMD_READ);
+
+ for (i = 0; i < count; ++i) {
+ memset(config->status_buf, 0x0, SZ_4K);
+ cmds[i].msg.rx_buf = config->status_buf;
+ cmds[i].msg.rx_len = config->status_cmds_rlen[i];
+ rc = dsi_ctrl_cmd_transfer(ctrl->ctrl, &cmds[i].msg, flags);
+ if (rc <= 0) {
+ pr_err("rx cmd transfer failed rc=%d\n", rc);
+ goto error;
+ }
+
+ memcpy(config->return_buf + start,
+ config->status_buf, lenp[i]);
+ start += lenp[i];
+ }
+
+error:
+ return rc;
+}
+
+static int dsi_display_validate_status(struct dsi_display_ctrl *ctrl,
+ struct dsi_panel *panel)
+{
+ int rc = 0;
+
+ rc = dsi_display_read_status(ctrl, panel);
+ if (rc <= 0) {
+ goto exit;
+ } else {
+ /*
+ * panel status read successfully.
+ * check for validity of the data read back.
+ */
+ rc = dsi_display_validate_reg_read(panel);
+ if (!rc) {
+ rc = -EINVAL;
+ goto exit;
+ }
+ }
+
+exit:
+ return rc;
+}
+
+static int dsi_display_status_reg_read(struct dsi_display *display)
+{
+ int rc = 0, i;
+ struct dsi_display_ctrl *m_ctrl, *ctrl;
+
+ pr_debug(" ++\n");
+
+ m_ctrl = &display->ctrl[display->cmd_master_idx];
+
+ rc = dsi_display_cmd_engine_enable(display);
+ if (rc) {
+ pr_err("cmd engine enable failed\n");
+ return -EPERM;
+ }
+
+ rc = dsi_display_validate_status(m_ctrl, display->panel);
+ if (rc <= 0) {
+ pr_err("[%s] read status failed on master,rc=%d\n",
+ display->name, rc);
+ goto exit;
+ }
+
+ if (!display->panel->sync_broadcast_en)
+ goto exit;
+
+ for (i = 0; i < display->ctrl_count; i++) {
+ ctrl = &display->ctrl[i];
+ if (ctrl == m_ctrl)
+ continue;
+
+ rc = dsi_display_validate_status(ctrl, display->panel);
+ if (rc <= 0) {
+ pr_err("[%s] read status failed on master,rc=%d\n",
+ display->name, rc);
+ goto exit;
+ }
+ }
+
+exit:
+ dsi_display_cmd_engine_disable(display);
+ return rc;
+}
+
+static int dsi_display_status_bta_request(struct dsi_display *display)
+{
+ int rc = 0;
+
+ pr_debug(" ++\n");
+ /* TODO: trigger SW BTA and wait for acknowledgment */
+
+ return rc;
+}
+
+static int dsi_display_status_check_te(struct dsi_display *display)
+{
+ int rc = 0;
+
+ pr_debug(" ++\n");
+ /* TODO: wait for TE interrupt from panel */
+
+ return rc;
+}
+
+int dsi_display_check_status(void *display)
+{
+ struct dsi_display *dsi_display = display;
+ struct dsi_panel *panel;
+ u32 status_mode;
+ int rc = 0;
+
+ if (dsi_display == NULL)
+ return -EINVAL;
+
+ panel = dsi_display->panel;
+
+ status_mode = panel->esd_config.status_mode;
+
+ dsi_display_clk_ctrl(dsi_display->dsi_clk_handle,
+ DSI_ALL_CLKS, DSI_CLK_ON);
+
+ if (status_mode == ESD_MODE_REG_READ) {
+ rc = dsi_display_status_reg_read(dsi_display);
+ } else if (status_mode == ESD_MODE_SW_BTA) {
+ rc = dsi_display_status_bta_request(dsi_display);
+ } else if (status_mode == ESD_MODE_PANEL_TE) {
+ rc = dsi_display_status_check_te(dsi_display);
+ } else {
+ pr_warn("unsupported check status mode\n");
+ panel->esd_config.esd_enabled = false;
+ }
+
+ dsi_display_clk_ctrl(dsi_display->dsi_clk_handle,
+ DSI_ALL_CLKS, DSI_CLK_OFF);
+
+ return rc;
+}
+
int dsi_display_soft_reset(void *display)
{
struct dsi_display *dsi_display;
@@ -1211,87 +1487,6 @@
return rc;
}
-static int dsi_display_cmd_engine_enable(struct dsi_display *display)
-{
- int rc = 0;
- int i;
- struct dsi_display_ctrl *m_ctrl, *ctrl;
-
- if (display->cmd_engine_refcount > 0) {
- display->cmd_engine_refcount++;
- return 0;
- }
-
- m_ctrl = &display->ctrl[display->cmd_master_idx];
-
- rc = dsi_ctrl_set_cmd_engine_state(m_ctrl->ctrl, DSI_CTRL_ENGINE_ON);
- if (rc) {
- pr_err("[%s] failed to enable cmd engine, rc=%d\n",
- display->name, rc);
- goto error;
- }
-
- for (i = 0; i < display->ctrl_count; i++) {
- ctrl = &display->ctrl[i];
- if (!ctrl->ctrl || (ctrl == m_ctrl))
- continue;
-
- rc = dsi_ctrl_set_cmd_engine_state(ctrl->ctrl,
- DSI_CTRL_ENGINE_ON);
- if (rc) {
- pr_err("[%s] failed to enable cmd engine, rc=%d\n",
- display->name, rc);
- goto error_disable_master;
- }
- }
-
- display->cmd_engine_refcount++;
- return rc;
-error_disable_master:
- (void)dsi_ctrl_set_cmd_engine_state(m_ctrl->ctrl, DSI_CTRL_ENGINE_OFF);
-error:
- return rc;
-}
-
-static int dsi_display_cmd_engine_disable(struct dsi_display *display)
-{
- int rc = 0;
- int i;
- struct dsi_display_ctrl *m_ctrl, *ctrl;
-
- if (display->cmd_engine_refcount == 0) {
- pr_err("[%s] Invalid refcount\n", display->name);
- return 0;
- } else if (display->cmd_engine_refcount > 1) {
- display->cmd_engine_refcount--;
- return 0;
- }
-
- m_ctrl = &display->ctrl[display->cmd_master_idx];
- for (i = 0; i < display->ctrl_count; i++) {
- ctrl = &display->ctrl[i];
- if (!ctrl->ctrl || (ctrl == m_ctrl))
- continue;
-
- rc = dsi_ctrl_set_cmd_engine_state(ctrl->ctrl,
- DSI_CTRL_ENGINE_OFF);
- if (rc)
- pr_err("[%s] failed to enable cmd engine, rc=%d\n",
- display->name, rc);
- }
-
- rc = dsi_ctrl_set_cmd_engine_state(m_ctrl->ctrl, DSI_CTRL_ENGINE_OFF);
- if (rc) {
- pr_err("[%s] failed to enable cmd engine, rc=%d\n",
- display->name, rc);
- goto error;
- }
-
-error:
- display->cmd_engine_refcount = 0;
- return rc;
-}
-
static int dsi_display_ctrl_host_enable(struct dsi_display *display)
{
int rc = 0;
diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_display.h b/drivers/gpu/drm/msm/dsi-staging/dsi_display.h
index 4d7a0b8..da4f5eb 100644
--- a/drivers/gpu/drm/msm/dsi-staging/dsi_display.h
+++ b/drivers/gpu/drm/msm/dsi-staging/dsi_display.h
@@ -489,6 +489,12 @@
int dsi_display_set_backlight(void *display, u32 bl_lvl);
/**
+ * dsi_display_check_status() - check if panel is dead or alive
+ * @display: Handle to display.
+ */
+int dsi_display_check_status(void *display);
+
+/**
* dsi_display_soft_reset() - perform a soft reset on DSI controller
* @display: Handle to display
*
diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_panel.c b/drivers/gpu/drm/msm/dsi-staging/dsi_panel.c
index 693295f..6718156 100644
--- a/drivers/gpu/drm/msm/dsi-staging/dsi_panel.c
+++ b/drivers/gpu/drm/msm/dsi-staging/dsi_panel.c
@@ -2495,6 +2495,7 @@
static void dsi_panel_esd_config_deinit(struct drm_panel_esd_config *esd_config)
{
+ kfree(esd_config->status_buf);
kfree(esd_config->return_buf);
kfree(esd_config->status_value);
kfree(esd_config->status_valid_params);
@@ -2621,6 +2622,10 @@
goto error3;
}
+ esd_config->status_buf = kzalloc(SZ_4K, GFP_KERNEL);
+ if (!esd_config->status_buf)
+ goto error4;
+
rc = of_property_read_u32_array(of_node,
"qcom,mdss-dsi-panel-status-value",
esd_config->status_value, esd_config->groups * status_len);
@@ -2632,6 +2637,8 @@
return 0;
+error4:
+ kfree(esd_config->return_buf);
error3:
kfree(esd_config->status_value);
error2:
diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_panel.h b/drivers/gpu/drm/msm/dsi-staging/dsi_panel.h
index f80dea2..f63fd27 100644
--- a/drivers/gpu/drm/msm/dsi-staging/dsi_panel.h
+++ b/drivers/gpu/drm/msm/dsi-staging/dsi_panel.h
@@ -135,7 +135,8 @@
u32 *status_cmds_rlen;
u32 *status_valid_params;
u32 *status_value;
- unsigned char *return_buf;
+ u8 *return_buf;
+ u8 *status_buf;
u32 groups;
};