| commit | 79cf95c763a11d4b365cd5a627fd1ab4dca67890 | [log] [tgz] |
|---|---|---|
| author | Tuomas Tynkkynen <ttynkkynen@nvidia.com> | Wed May 13 17:58:43 2015 +0300 |
| committer | Thierry Reding <treding@nvidia.com> | Thu Jul 16 10:40:20 2015 +0200 |
| tree | c314059d2be0ef328cb28b533cb2e66fbe414b97 | |
| parent | c38864a703f3fe50e2b87883a0def392dd5bf26f [diff] |
clk: tegra: Add the DFLL as a possible parent of the cclk_g clock The DFLL clocksource was missing from the list of possible parents for the fast CPU cluster. Add it to the list. Signed-off-by: Tuomas Tynkkynen <ttynkkynen@nvidia.com> Signed-off-by: Mikko Perttunen <mikko.perttunen@kapsi.fi> Acked-by: Michael Turquette <mturquette@linaro.org> Signed-off-by: Thierry Reding <treding@nvidia.com>