tree c314059d2be0ef328cb28b533cb2e66fbe414b97
parent c38864a703f3fe50e2b87883a0def392dd5bf26f
author Tuomas Tynkkynen <ttynkkynen@nvidia.com> 1431529123 +0300
committer Thierry Reding <treding@nvidia.com> 1437036020 +0200

clk: tegra: Add the DFLL as a possible parent of the cclk_g clock

The DFLL clocksource was missing from the list of possible parents for
the fast CPU cluster. Add it to the list.

Signed-off-by: Tuomas Tynkkynen <ttynkkynen@nvidia.com>
Signed-off-by: Mikko Perttunen <mikko.perttunen@kapsi.fi>
Acked-by: Michael Turquette <mturquette@linaro.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>