| commit | 7b337e61a4104d5a0abde1e733916de2208800e6 | [log] [tgz] |
|---|---|---|
| author | Geert Uytterhoeven <geert+renesas@glider.be> | Sat Jan 16 15:17:36 2016 +0100 |
| committer | Simon Horman <horms+renesas@verge.net.au> | Fri Feb 05 10:43:42 2016 +0100 |
| tree | e3c0ceee12a7ad506f0c3d4418051462da32f9ec | |
| parent | a3fc85e27b7e3c29b30909929bc64737a19fd251 [diff] |
arm64: dts: r8a7795: Add L2 cache-controller nodes Add device nodes for the L2 caches, and link the CPU node to its L2 cache node. The L2 cache for the Cortex-A57 CPU cores is 2 MiB large (organized as 128 KiB x 16 ways). Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Dirk Behme <dirk.behme@gmail.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>